JPS6254806A - Read circuit for magnetic storage device - Google Patents

Abstract

PURPOSE:To improve the phase detection margin of a read means by providing a variable resistor between an output of a delay line and a common potential so as to prevent an undershoot from being caused at the trailing edge of the waveform after equalization. CONSTITUTION:A variable resistor circuit 11 changing a resistance between an output terminal of the delay line 4 and ground is added. The variable resistor circuit 11 is provided with resistors 12, 13, 14 and analog switches 15, 16 and 17. Resistor setting signals 20 being three output signals of a storage circuit 19 are fed respectively to on/off control input terminals of the analog switches 15, 16 and 17 and address signals 18 selecting a magnetic head of a magnetic disc device are inputted to 4 input terminals of the storage circuit 19.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a read circuit for a magnetic storage device such as a magnetic disk device and a magnetic tape device.

Here, the cosine equalizer is an equalizer whose frequency characteristics are represented by a cosine function, and is used to perform waveform transmission with less code amount interference.

〔overview〕

In a readout circuit having means for cosine equalizing a readout signal of a magnetic storage device read out by a magnetic head, the phase of the readout means can be improved by preventing undershoot from occurring at the trailing edge of the equalized waveform. This is designed to improve the detection margin.

[Conventional technology]

FIG. 3 shows the configuration of a conventional reflective cosine equalization circuit used for amplitude equalization in readout circuits of magnetic disk drives, magnetic tape drives, and the like. This reflective cosine equalization circuit includes a buffer circuit 2 having a high output impedance that inputs a read signal 1 from a magnetic disk device, a delay line 4 for delaying a buffer circuit output signal 20, and an amplitude of the buffer circuit output signal 20. A differential amplifier 6 inputs a delay line output signal 21 and an attenuator output signal 22, and a resistor 7 having the same value as the characteristic impedance of the delay line 4.

FIG. 4 is a time chart showing waveforms at various parts in FIG. In this figure, the attenuator output signal 22 is shown as a signal - with the polarity reversed. The waveform shown in FIG. 4 is a solitary wave in which adjacent magnetization reversals are separated. Further, the symbol τ indicates the delay time of the delay line 4.

Generally, the time relationship between the leading edge T'ws and the trailing edge Tw6 of the half-width of a solitary wave reproduced from a magnetic storage medium by a wire-wound magnetic head is T8. Set to ≧T1,6.

This time relationship changes depending on the state of impedance matching between the magnetic head and the read circuit. When the impedance matching state is greatly disturbed due to variations in the characteristic impedance of the magnetic head and variations in the input impedance of the readout circuit, and the time difference between the leading edge TwS and the trailing edge TW6 of the solitary wave half-width becomes large, the fourth The solitary wave shown in the figure is reproduced. Therefore, the amplitude of the output signal 22 is adjusted by varying the amount of attenuation of the attenuator 8, and the output signal 23 of the differential amplifier is adjusted.
When the leading edge of the differential amplifier output signal 23 is set to a critical condition on the verge of undershooting, an undershoot 24 occurs at the trailing edge of the differential amplifier output signal 23. Due to this undershoot 24, in the amplitude detection operation of the readout signal, the amplitude detection margin against leakage noise is reduced, and if adjacent magnetization reversals are close to each other, the reproduced signal is distorted and the phase detection margin is reduced. descend.

[Problem that the invention seeks to solve]

In such a conventional circuit, when amplitude equalization is performed using a reflection type cosine equalization circuit, impedance matching between the magnetic head and the readout circuit is difficult due to variations in the characteristic impedance of the magnetic head and variations in the input impedance of the readout circuit. In the case of a large deviation, a larger undershoot occurs at the trailing edge of the waveform in the read isolated waveform equalizer than at the leading edge, and this undershoot has the drawback of lowering the signal detection margin.

SUMMARY OF THE INVENTION It is an object of the present invention to overcome these drawbacks, and to provide a readout circuit for a magnetic storage device in which undershoot is less likely to occur at the trailing edge of the equalizer waveform.

[Means for solving problems]

The present invention provides a readout circuit for a magnetic storage device comprising an input terminal for inputting readout signals of a magnetic storage device having a plurality of magnetic heads, and a cosine equalization circuit having a delay line, which is common to the output of the delay line. The magnetic head is characterized by comprising a variable resistance means inserted between the magnetic head and the magnetic head, and a setting means for setting the resistance value of the variable resistance means in correspondence with the magnetic head.

[Effect]

The reflected wave at the output end of the delay line of the cosine equalization layer affects the output signal waveform of this equalization layer.

Normally, the leading edge of this output signal is set at a critical condition where an undershoot occurs, but in this case, the trailing edge may be accompanied by an undershoot.

The present invention controls the amplitude of reflected waves by changing the resistance value of the variable resistance means in accordance with the magnetic head used. This prevents undershoot from occurring at the trailing edge.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS A circuit according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block configuration diagram showing the configuration of a circuit according to an embodiment of the present invention. FIG. 2 is a waveform diagram showing the waveforms of signals at various parts in FIG.

First, the configuration of a circuit according to an embodiment of the present invention will be explained based on FIG.

This embodiment device includes a buffer circuit 2 having high output impedance, a delay line 4, a differential amplifier 6,
It includes a resistor 7, an attenuator 8, a variable resistance circuit 1), and a memory circuit 19. Here, the variable resistance circuit 1) includes resistors 12.13 and 14 and an analog switch 15.1.
6 and 17. A read signal is input to the input terminal of the buffer circuit 2, and the buffer circuit output signal 3, which is the output of the buffer circuit 2, is applied to the input terminal of the delay line 4 and the input terminal of the attenuator 8. grounded through. Attenuator output signal 9, which is the output signal of attenuator 8, is applied to the input terminal of differential amplifier 6, and D-line output signal 5, which is the output signal of delay line 4, is applied to the other input terminal of differential amplifier 6. and resistor 12
and grounded via analog switch 15, grounded via resistor 13 and analog switch 16, and grounded via resistor 14 and analog switch 17. Resistance value setting signals 20, which are three output signals of the memory circuit 19, are applied to the on/off control input terminals of the analog switches 15, 16 and 17, respectively.
An address signal 18 for selecting a magnetic head of a magnetic disk device is input to four input terminals 9. The present invention is characterized by the addition of a variable resistance circuit 1) that can change the resistance value between the output terminal of the delay line 4 and ground.

Next, the operation of the circuit according to the embodiment of the present invention will be explained based on FIGS. 1 and 2.

The memory circuit 19 is a non-volatile memory circuit, and stores resistance value setting information for setting the resistance value of the variable resistance circuit 1) suitable for the readout waveform of the magnetic helix designated by the input address signal 1. Information stored at the address (storage location) specified by the input address signal 18 is output as the resistance value setting signal 20. Setting of this resistance value setting information is carried out by examining the waveform of the read signal of each magnetic head during the manufacturing process of the magnetic disk device, and determining a value suitable for each. This information is output in the form of 3-bit binary information and input to the on/off control input terminals of analog switches 15, 16 and 17, respectively.
The analog switches 15, 16 and 17 are controlled on and off to change the resistance value between the output terminal of the delay line 4 and the ground.

The read signal 1 of the magnetic disk device generally has a solitary wave shape, and the magnitude relationship between the leading edge TWI and the trailing edge T, 42 of the half width is TWI≧Tw2. FIG. 2(a) shows a case where the leading edge TWI is slightly larger than the trailing edge T8□. The delay line output signal 5 is a signal delayed from the read signal 1 of the magnetic disk device by the delay time between the buffer circuit 2 and the delay line 4, and has the same waveform as the read signal 1. The output signal 3 of the buffer circuit is a composite signal of the readout signal 1 and the reflected wave reflected at the output end of the delay line 4, and the attenuated output signal 9 of the attenuator 8 has the amplitude of the buffer circuit output signal 3. This is an attenuated signal.

Here, the amplitude of the reflected wave of the delay line 4 is controlled by a variable resistance circuit 1) provided at the output end of the delay line 4. That is, with the attenuated output signal 9 which is a composite signal,
The amplitude V2 generated by the reflected wave of the delay line 4 can be made smaller than the amplitude V1 generated by the read signal 1. In variable resistance circuit 1), delay line 4
When the resistance value between the output terminal and the ground is controlled, and the resistance value is sufficiently large compared to the characteristic impedance of the delay line, the amplitude V of the attenuator output signal 9 and the amplitude V2 become almost equal, and the resistance value is the same value as the characteristic impedance of the delay line, the amplitude V of the attenuator output signal 9
The peak of 2 will disappear. Therefore, when the delay line output signal 5 and the attenuator output signal 9 are subtracted by the differential amplifier 6, the amount of subtraction at the trailing edge of the delay line output signal 5 becomes smaller, and the output signal 10 of the differential amplifier 6 becomes smaller. Both the leading edge and the trailing edge can be compensated equally.

The ratio of the amplitudes V1 and 2 of the two peaks of the attenuator output signal 9 shown in FIG. 2(a) is set so that the memory circuit 19
The resistance value of the variable resistance circuit 1) is determined by the resistance value of the variable resistance circuit 1) controlled by the resistance value setting signal 20 output from the variable resistance circuit 1). As a result, both the leading and trailing edges of the output signal 10 of the differential amplifier 6 can be amplitude-equalized to a critical condition on the verge of causing undershoot.

Fig. 2(b) shows that another magnetic head is selected and Fig. 2(a) shows that another magnetic head is selected.
Furthermore, the impedance matching between the magnetic head and the reading circuit breaks down, leading to the leading edge Tw3 and trailing edge Tw3 of the isolated waveform half width.
This is a case where the difference with W4 is even larger. In this case, as in the case of FIG. 2(a), the ratio of the two peak amplitudes 3 and V4 of the attenuator output signal 9 is equal to the isolated waveform of the read signal 1 of the selected magnetic head. The resistance value of the variable resistance circuit 1) is determined by the resistance value of the variable resistance circuit 1) controlled by the resistance value setting signal 20 which is the output from the memory circuit 19.

In the case of FIG. 2(b), the reflected wave amplitude 4 in the attenuator output signal 9 is set to be quite small. Therefore, the equalized output signal 10 of the differential amplifier 6 is amplitude-equalized to the critical condition as in the case of FIG. 2(a).

In the circuit of this embodiment, the memory circuit 19 has four input address signals 18, but the present invention can also be practiced by increasing or decreasing the number of input address signals depending on the number of magnetic heads mounted on the magnetic disk device. be able to. Further, the present invention can be practiced even if the number of resistance value setting signals 20 is increased or decreased depending on the performance of the magnetic disk device.

〔Effect of the invention〕

As explained above, even if the asymmetry of the leading and trailing edges of the isolated waveform of the read signal varies due to variations in the characteristic interface of the magnetic head and variations in the input impedance of the readout circuit, the present invention compensates the waveform evenly for both the leading and trailing edges. There is an effect that can be done.

Therefore, it is possible to reduce read errors in a magnetic storage device using the read circuit of the present invention and increase the reliability of information read.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the configuration of a circuit according to an embodiment of the present invention. FIG. 2 is a waveform diagram showing the waveforms of the main signals in FIG. FIG. 3 is a block configuration diagram showing the configuration of a conventional circuit. FIG. 4 is a waveform diagram showing waveforms of main signals in the circuit of FIG. 3. 2... Buffer circuit, 4... Delay line, 6...
...Differential amplifier, 8...Attenuator, 1)...Variable resistance circuit, 7.12.13.14...Resistor, 15.16
．． 17...analog switch, 19...memory circuit.

Claims (1)

[Claims] (1) In a readout circuit for a magnetic storage device comprising an input terminal for inputting readout signals of a magnetic storage device having a plurality of magnetic heads and a cosine equalization circuit having a delay line, a common potential with the output of the delay line is provided. A read circuit for a magnetic storage device, comprising: a variable resistance means inserted between the magnetic head; and a setting means for setting a resistance value of the variable resistance means in correspondence with the magnetic head.