JPS62128575A - Semiconductor photodetector - Google Patents

Semiconductor photodetector

Info

Publication number
JPS62128575A
JPS62128575A JP60269710A JP26971085A JPS62128575A JP S62128575 A JPS62128575 A JP S62128575A JP 60269710 A JP60269710 A JP 60269710A JP 26971085 A JP26971085 A JP 26971085A JP S62128575 A JPS62128575 A JP S62128575A
Authority
JP
Japan
Prior art keywords
type
layer
region
current
depletion layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60269710A
Other languages
Japanese (ja)
Inventor
Minoru Kubo
実 久保
Yoichi Sasai
佐々井 洋一
Mototsugu Ogura
基次 小倉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP60269710A priority Critical patent/JPS62128575A/en
Publication of JPS62128575A publication Critical patent/JPS62128575A/en
Pending legal-status Critical Current

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  • Light Receiving Elements (AREA)

Abstract

PURPOSE:To form a Pin structure easily on a multilayer films on a semi- insulating substrate without shallow control of the depth direction of P-type diffusion by a method wherein P-type regions are formed on an N<-> type InGaAs layer successively and periodically with the space between adjacent P-type regions about the width of a depletion layer when a reverse voltage is applied. CONSTITUTION:An N<-> type InP layer 8 with an N-type carrier concentration of about 1X10<16>cm<-3>, an N<-> type InP layer 9 with a carrier concentration of about 1X10<15>cm<-3> and an N<-> type InGaAs layer 10 with a carrier concentration of also about 1X10<15>cm<-3> are formed on a semi-insulating substrate 7. Then a comb-shape P-type region 11 is formed by ion implantation of Zn and a P-type electrode Au/Zn 12 and an N-type electrode 13 are formed. The mutual space l between the comb teeth of the P-type region 11 is about the width of a depletion layer which is expanded when a reverse voltage is applied. As carriers induced by an incident light perform as a diffusion current in the P-type region 11 and as a drifting current in the depletion layer region 20, excess carriers induced near the surface perform as the drifting current so that the influence of the rate-determination by the diffusion current can be reduced.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、光集積回路等に適した構造の半導体受光素子
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor light receiving element having a structure suitable for optical integrated circuits and the like.

従来の技術 従来のInGaAs/InP系のPin−フォトダイオ
ードを第2図に示す。n型InP基板1上に、n−1n
P層2 、 n−InGaAs層3を形成し、メサエッ
チングを施したのちL等のP型不純物による拡散やイオ
ン注入によりP型領域4を形成し、さらに電極5を形成
したものである。前記Pinフォトダイオードにおいて
は、素子特性、特に童子効率は、P型頭域の深さの制御
性に大きく左右さ九るものである。
2. Description of the Related Art A conventional InGaAs/InP-based Pin-photodiode is shown in FIG. On the n-type InP substrate 1, n-1n
After forming a P layer 2 and an n-InGaAs layer 3 and performing mesa etching, a P type region 4 is formed by diffusion using a P type impurity such as L or ion implantation, and an electrode 5 is further formed. In the Pin photodiode, the device characteristics, especially the Doji efficiency, are greatly influenced by the controllability of the depth of the P-type head region.

また受光時発生したキャリアは、P型頭域では拡散電流
として、空乏層領域ではドリフト電流として振うもので
あり、高速動作のためには素子容量とともにP型領域形
成も重要な問題の1つとなる。
Furthermore, the carriers generated during light reception behave as a diffusion current in the P-type head region and as a drift current in the depletion layer region, and the formation of the P-type region is one of the important issues in addition to element capacitance for high-speed operation. Become.

発明が解決しようとする問題点 前記のPinフォトダイオードを光集積回路等への応用
を考えた場合、半絶縁性基板上へ形成する必要があり、
その際のP型領域形成プロセスの制御性及び前記メサ型
構造の集積化等の問題があった。また、ペテロ接合等に
おける2次元電子をキャリアとして用い高速化を計る際
に、各層厚が非常に薄くなり、P型領域形成によるPi
n構造形成の制御性や、量子効率等に問題があった。
Problems to be Solved by the Invention When considering the application of the above-mentioned Pin photodiode to optical integrated circuits, etc., it is necessary to form it on a semi-insulating substrate.
At that time, there were problems such as controllability of the P-type region formation process and integration of the mesa structure. In addition, when trying to increase the speed by using two-dimensional electrons as carriers in a Peter junction, etc., the thickness of each layer becomes extremely thin, and the Pi
There were problems with controllability of n-structure formation, quantum efficiency, etc.

問題点を解決するための手段 本発明はかかる問題点を解決するために、nn−InC
laA層上に形成するP型頭域を、隣接するP型領域間
の間隔が逆方向電圧印加時の空乏層幅程度で連続した周
期的な領域として形成して、半導体受光素子とするもの
である。
Means for Solving the Problems The present invention solves the problems by using nn-InC.
The P-type head region formed on the laA layer is formed as a continuous periodic region in which the interval between adjacent P-type regions is about the width of the depletion layer when a reverse voltage is applied, thereby forming a semiconductor light-receiving element. be.

作  用 上記手段を用いる事により、多層薄膜上へのPin構造
形成においても、P型拡散の深さ方向の浅い制御を必要
とせず、容易に半絶縁性基板上の多層薄膜上に形成が可
能である0また、連続したP型頭域からの空乏層の拡り
は、隣接するP型頭域に及ぶ程度の間隔であり、P型頭
域の周期的部分には電極を形成していないので量子効率
が低下せず、キャリアの拡散電流としての影響を低減で
き、ヘテロ接合界面の2次元電子を用いるため、高速化
が図れるものである。
Effect By using the above method, even when forming a pin structure on a multilayer thin film, it is possible to easily form a pin structure on a multilayer thin film on a semi-insulating substrate without requiring shallow control of the depth direction of P-type diffusion. In addition, the depletion layer spreads from continuous P-type head regions at intervals that extend to adjacent P-type head regions, and no electrodes are formed in periodic parts of the P-type head regions. Therefore, the quantum efficiency does not decrease, the influence of carrier diffusion current can be reduced, and since two-dimensional electrons at the heterojunction interface are used, high speed can be achieved.

実施例 本発明の一実施例を第1図a、bに示す、 InGaA
s/InP系受光素子を用いて説明する。半絶縁性In
P基板7上にn型キャリア濃度が1×101奮3程度の
n−InP層8と、1×1−瞥3 程度のn”InP層
9と、やはF) I X 10”cm−”程度のn−I
nGaAs層1Qを、各々2000人、50人、100
00人ずつ形成する。次に第1図aに示すように、くし
形のP型領域11をムのイオン注入により、第1図すに
示すように、5OOQ八程度へ深さまで形成し、P型電
極Au/Zn12とn型電極13を形成する。P型領域
11の相互間隔lは逆方向印加時に拡がる空乏層幅程度
である。受光部はくし形のP型領域11と、その間隔に
拡がっている逆方向電圧印加時に拡がった空乏層領域2
oである。
Embodiment An embodiment of the present invention is shown in FIGS. 1a and 1b. InGaA
This will be explained using an s/InP light receiving element. Semi-insulating In
On the P substrate 7, there is an n-InP layer 8 with an n-type carrier concentration of about 1 x 10 cm and an n'' InP layer 9 with an n-type carrier concentration of about 1 x 1 cm. degree n-I
2000, 50, and 100 layers of nGaAs layer 1Q, respectively.
00 people each. Next, as shown in FIG. 1a, a comb-shaped P-type region 11 is formed by ion implantation to a depth of approximately 5OOQ8, as shown in FIG. An n-type electrode 13 is formed. The mutual spacing 1 between the P-type regions 11 is approximately the width of the depletion layer that expands when voltage is applied in the reverse direction. The light-receiving part includes a comb-shaped P-type region 11 and a depletion layer region 2 that expands when a reverse voltage is applied, which spreads between the comb-shaped P-type regions 11.
It is o.

従って、入射光によって生じたキャリアは、P型領域1
1では拡散電流として、また空乏層領域20ではドリフ
ト電流として振うので、表面近傍の発生キャリアの多い
分が、ドリフト電流として振舞い拡散電流による律速の
影響が減少し、高速化が図れる。
Therefore, carriers generated by the incident light are transferred to the P-type region 1
1 as a diffusion current and in the depletion layer region 20 as a drift current, the more carriers generated near the surface behave as a drift current, reducing the rate-limiting influence of the diffusion current and increasing the speed.

電子についてはへテロ界面の2次元電子ガスによシ高移
動度が実現可能であり、高速・高量子効率で、ヘテロ接
合の2次元電子ガスを用いた電気素子等の集積も容易な
、半導体受光素子が得られるものである。
As for electrons, high mobility can be achieved by the two-dimensional electron gas at the heterojunction, and semiconductors are fast, have high quantum efficiency, and are easy to integrate electrical devices using the two-dimensional electron gas at the heterojunction. A light receiving element is obtained.

なお、P型領域11はくし型状に限らず格子状でもよい
Note that the P-type region 11 is not limited to a comb-like shape but may be a lattice-like shape.

発明の効果 以上のように本発明によれば、表面での受光によって発
生したキャリアを、くし型又は格子状のP型頭域を形成
しておく事によりラテラルのPinフォトダイオードの
構造で空乏層での吸収を効率よく用い、かつ、拡散電流
成分すなわち高速動作時の律速成分を減少させるもので
あり、またへテロ接合における2次元電子ガスによる電
子の移動度の向上がはかれる。従って本発明によれば、
高速・高効率で、半絶縁性基板上にプレーナの、集積化
に適した受光素子を得る事が可能である。
Effects of the Invention As described above, according to the present invention, carriers generated by light reception on the surface are transferred to a depletion layer in the lateral Pin photodiode structure by forming a comb-shaped or lattice-shaped P-type head region. This method efficiently utilizes the absorption at the junction and reduces the diffusion current component, that is, the rate-determining component during high-speed operation, and also improves the mobility of electrons due to the two-dimensional electron gas in the heterojunction. According to the invention, therefore:
It is possible to obtain a planar light-receiving element suitable for integration on a semi-insulating substrate at high speed and with high efficiency.

【図面の簡単な説明】[Brief explanation of drawings]

第1図aは本発明の一実施例における半導体受光素子の
平面図、第1図すは第1図aのA −A’線断面図、第
2図は従来の半導体受光素子の断面図である。 7・・・・・・半絶縁性InP基板、8・・・・・・n
”’InP層、9・・・・・・n−InP層、10・・
・・・・n−InGaAs層、11・・・・・・P型頭
域。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名7一
−−卓kl#M=rrlplH 8−・へYハP−11 9・−八−・ 第1図     Lo−’n’rnGtJIs4”−’
−Zn 1r)tn、)、p ’!14 +L’+2−
.4u/l−ソに +j−−%/Sh T穫 第2図 1−−− n’l ’fnP:4;1 2−0−丁。2層 3−、−丁n&a、As”4 +−−−/)フ島貢瓜 5−電糧
FIG. 1a is a plan view of a semiconductor photodetector according to an embodiment of the present invention, FIG. 1 is a sectional view taken along the line A-A' in FIG. be. 7...Semi-insulating InP substrate, 8...n
``'InP layer, 9... n-InP layer, 10...
...n-InGaAs layer, 11...P-type head area. Name of agent: Patent attorney Toshio Nakao and one other person
-Zn 1r)tn,),p'! 14 +L'+2-
.. 4u/l-So+j--%/Sh T 2nd Figure 1 --- n'l'fnP: 4; 1 2-0-t. 2 layers 3-, -ding n&a, As”4 +----/) Fu Island Gourd 5-Electric food

Claims (1)

【特許請求の範囲】 半絶縁性InP基板上に、一方導電型InP層とIn_
xGa_1_−_xAs_yP_1_−_y層(0≦x
≦1、0≦y≦1)を有し、他方導電型領域が、前記一
方導電型 In_xGa_1_−_xAs_yP_1_−_y層表
面においてくし形もしくは格子状に周期的に形成され、
隣接する前記他方導電型領域間隔が、逆方向電位印加時
の空乏層幅程度とすることを特徴とする半導体受光素子
[Claims] On a semi-insulating InP substrate, one conductivity type InP layer and an In_
xGa_1_-_xAs_yP_1_-_y layer (0≦x
≦1, 0≦y≦1), and the other conductivity type regions are periodically formed in a comb shape or a lattice shape on the surface of the one conductivity type In_xGa_1_-_xAs_yP_1_-_y layer,
A semiconductor light-receiving device characterized in that an interval between adjacent regions of the other conductivity type is approximately the width of a depletion layer when a reverse potential is applied.
JP60269710A 1985-11-29 1985-11-29 Semiconductor photodetector Pending JPS62128575A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60269710A JPS62128575A (en) 1985-11-29 1985-11-29 Semiconductor photodetector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60269710A JPS62128575A (en) 1985-11-29 1985-11-29 Semiconductor photodetector

Publications (1)

Publication Number Publication Date
JPS62128575A true JPS62128575A (en) 1987-06-10

Family

ID=17476095

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60269710A Pending JPS62128575A (en) 1985-11-29 1985-11-29 Semiconductor photodetector

Country Status (1)

Country Link
JP (1) JPS62128575A (en)

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