JPS62126783U - - Google Patents

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Publication number
JPS62126783U
JPS62126783U JP12917186U JP12917186U JPS62126783U JP S62126783 U JPS62126783 U JP S62126783U JP 12917186 U JP12917186 U JP 12917186U JP 12917186 U JP12917186 U JP 12917186U JP S62126783 U JPS62126783 U JP S62126783U
Authority
JP
Japan
Prior art keywords
display
main memory
speed clock
detection signal
ray tube
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12917186U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12917186U priority Critical patent/JPS62126783U/ja
Publication of JPS62126783U publication Critical patent/JPS62126783U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案による画像表示装置の一例を
示すブロツク図、第2図はその表示状態の一例を
示す図、第3図は第2図のマーカ信号発生部分の
動作を説明するための波形図、第4図はマーカ信
号を書込む部分の例を示すブロツク図、第5図は
微分回路56の一例を示すブロツク図、第6図は
マーカ表示の他の例を示す図、第7図はマーカ表
示信号発生及びその書込み発生部分の他の例を示
すブロツク図、第8図はその更に他の例を示すブ
ロツク図、第9図はマーカの他の例を示す図、第
10図はマーカ信号の挿入の他の例を示すブロツ
ク図、第11図はシフト動作におけるトリガ信号
を得る回路を示すブロツク図である。 11:陰極線管、12:主発振器、13:分周
器、16:主メモリ、22:トリガ端子、23:
入力信号端子、18:カラー変換回路、24,3
6:バツフアメモリ、55:マーカ発生用分周器
、56:微分回路、57:ゲート、54:マーカ
FIG. 1 is a block diagram showing an example of an image display device according to this invention, FIG. 2 is a diagram showing an example of its display state, and FIG. 3 is a waveform diagram for explaining the operation of the marker signal generating portion of FIG. 2. 4 is a block diagram showing an example of a portion where a marker signal is written, FIG. 5 is a block diagram showing an example of the differentiation circuit 56, FIG. 6 is a diagram showing another example of marker display, and FIG. 8 is a block diagram showing another example of the marker display signal generation and its write generation part, FIG. 9 is a block diagram showing still another example, FIG. 9 is a diagram showing another example of the marker, and FIG. FIG. 11 is a block diagram showing another example of marker signal insertion. FIG. 11 is a block diagram showing a circuit for obtaining a trigger signal in a shift operation. 11: Cathode ray tube, 12: Main oscillator, 13: Frequency divider, 16: Main memory, 22: Trigger terminal, 23:
Input signal terminal, 18: Color conversion circuit, 24, 3
6: Buffer memory, 55: Marker generation frequency divider, 56: Differential circuit, 57: Gate, 54: Marker.

補正 昭61.9.24 実用新案登録請求の範囲を次のように補正する
Amendment September 24, 1986 The scope of claims for utility model registration is amended as follows.

【実用新案登録請求の範囲】 走査形の表示用陰極線管の表示面の走査と同期
してデジタル主メモリを読出し、その読出し出力
を上記表示用陰極線管へ表示信号として供給し、
魚群探知機からの探知信号を上記主メモリに入力
するごとに、上記表示用陰極線管の表示面の一端
にその入力した探知信号を1本の表示線として表
示すると共に、古い表示線を順次他端側へずらし
、かつ最も古い探知信号を上記主メモリから消去
する魚群探知機用画像表示装置であつて、 上記表示用陰極線管はカラー陰極線管であり、 上記探知信号が供給され、これをデジタル信号
に変換するAD変換器と、 そのAD変換器を動作させる低速クロツクを発
生する低速クロツク発生器と、 上記AD変換器よりのデジタル信号を上記主メ
モリへ転送するための、上記低速クロツクより速
い高速クロツクを発生する高速クロツク発生器と
、 上記主メモリを読出すための 読出しクロツクを
発生する読出しクロツク発生器と上記主メモリか
ら読出された探知信号のレベルを示すデジタル信
号をこれと対応する色信号に変換して上記カラー
陰極線管へ供給するカラー変換回路と
を具備する
魚群探知機用画像表示装置。
[Scope of utility model registration request] Scanning and synchronization of the display surface of a scanning type display cathode ray tube
to read out the digital main memory and read out the readout output.
is supplied to the display cathode ray tube as a display signal,
Input the detection signal from the fish finder into the main memory above.
Each time, one end of the display surface of the above display cathode ray tube is
The input detection signal is displayed as one display line.
At the same time, the old display line is sequentially shifted to the other end.
, and the oldest detection signal is deleted from the main memory above.
An image display device for a fish finder, The above display cathode ray tube is a color cathode ray tube, The above detection signal is supplied, and this is converted into a digital signal.
an AD converter that converts into Generates a low-speed clock that operates the AD converter.
a low-speed clock generator that generates The digital signal from the AD converter above is
To MoriForwardfaster than the above slow clock for
A high-speed clock generator that generates a high-speed clock
, To read the above main memory read clock
The read clock generator anda color conversion circuit that converts a digital signal indicating the level of the detection signal read from the main memory into a corresponding color signal and supplies the same to the color cathode ray tube;be equipped with
Image display device for fish finders.

Claims (1)

【実用新案登録請求の範囲】 走査形の表示用陰極線管の表示面の走査と同期
してデジタル主メモリを読出し、その読出し出力
を上記表示用陰極線管へ表示信号として供給し、
魚群探知機からの探知信号を上記主メモリに入力
するごとに、上記表示用陰極線管の表示面の一端
にその入力した探知信号を1本の表示線として表
示すると共に、古い表示線を順次他端側へずらし
、かつ最も古い探知信号を上記主メモリから消去
する魚群探知機用画像表示装置であつて、 上記探知信号が供給され、これをデジタル信号
に変換するAD変換器と、 そのAD変換器を動作させる低速クロツクを発
生する低速クロツク発生器と、 上記AD変換器よりのデジタル信号を上記主メ
モリへ書込むための、上記低速クロツクより速い
高速クロツクを発生する高速クロツク発生器と、 上記主メモリを読出すための、上記高速クロツ
クより更に速い読出しクロツクを発生する読出し
クロツク発生器とを具備する魚群探知機用画像表
示装置。
[Claims for Utility Model Registration] Reading out a digital main memory in synchronization with the scanning of the display surface of a scanning cathode ray tube for display, and supplying the readout output to the cathode ray tube for display as a display signal,
Every time a detection signal from the fish finder is input into the main memory, the input detection signal is displayed as one display line on one end of the display screen of the display cathode ray tube, and the old display lines are sequentially replaced with the other display lines. An image display device for a fish finder that shifts the detection signal toward the end and erases the oldest detection signal from the main memory, the AD converter being supplied with the detection signal and converting it into a digital signal, and the AD converter. a low-speed clock generator that generates a low-speed clock to operate the device; a high-speed clock generator that generates a high-speed clock faster than the low-speed clock for writing digital signals from the AD converter to the main memory; A read clock generator for generating a read clock faster than the high speed clock for reading a main memory.
JP12917186U 1986-08-25 1986-08-25 Pending JPS62126783U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12917186U JPS62126783U (en) 1986-08-25 1986-08-25

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12917186U JPS62126783U (en) 1986-08-25 1986-08-25

Publications (1)

Publication Number Publication Date
JPS62126783U true JPS62126783U (en) 1987-08-11

Family

ID=31025508

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12917186U Pending JPS62126783U (en) 1986-08-25 1986-08-25

Country Status (1)

Country Link
JP (1) JPS62126783U (en)

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