JPS62125578A - Reproduction clock generating device - Google Patents

Abstract

PURPOSE:To simplify the overall constitution of a reproduction circuit by using a latch means and an adder means to constitute the frame synchronizing signal and the code synchronizing signal necessary for demodulation. CONSTITUTION:The time-divided clock (a), data (b) and track number (c) are inputted to terminals CK, DATA and TRUCK NO. respectively. The data (b) is distributed to a shift register 2 for each track by the clock (d). The output (e) of the register 2 is outputted to a detector 5 for synchronizing pattern and a decoder 10. The detector 5 outputs the SYNC detecting signal (f) after detecting the signal SYNC. The signal (f) is used as the clear signal of a symbol clock generator 3 and a frame counter generator 4 respectively. A generator 3-1 outputs the data (h) of L bits and the data (h) receives +1 from an adder 6. Then the data (h) is inputted again to the generator 3-1. Here if the signal (f) is outputted, the adder 6 is cleared. While an adder 7 is also cleared by the signal (f). The output (i) of the adder 7 is latched by a frame counter generator 4-1 and also outputted to the next stage.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a digital magnetic recording and reproducing system, particularly a multi-track modulation system that has a plurality of tracks and converts N-bit data into an M-bit code word. The present invention relates to a reproduction clock signal generation circuit that generates a code synchronization signal (hereinafter referred to as a symbol clock) and a frame synchronization signal necessary for demodulation in a track-type digital magnetic recording/sickle reproduction apparatus.

<Prior art> In recent years, analog signals such as audio are converted into digital signals, which are then modulated using a predetermined modulation method to generate self-clockable digital signals, which are then recorded on magnetic recording media such as magnetic tape. A device for reproducing the information has also been developed. When converting an analog signal into a digital signal, a digital magnetic recording/reproducing device requires a much wider frequency band than a conventional analog magnetic recording/reproducing device.

A multi-track digital magnetic recording/reproducing device is designed to reduce the recording density per track by distributing digital signals to a plurality of tracks.

FIG. 3 is a block diagram showing a schematic configuration on the playback side of a conventional n-track digital magnetic recording and playback device.

In FIG. 3, a constant current is passed through a magnetoresistive element 12 from a constant current source 11 to obtain a voltage signal due to a change in magnetoresistance. The capacitor 13 is a DC cut capacitor that prevents the direct current of the constant current source 11 from flowing into the amplifier circuit 15 side, and also forms a low-pass filter in combination with the resistor 14. The signal is then amplified to a required level by the amplifier circuit 15 to obtain an amplified signal. after that,
The reproduced signal characteristics are equalized by the equalizer 16, phase synchronized with the data by clock synchronization, demodulated and reproduced by the decoder 18 by frame synchronization, entered into the buffer 7 memory 20, and the signals from each track are multiplexed by the multiplexer 21. The signal is then input to the digital signal processing circuit 22, where it undergoes signal processing such as error correction, and is converted into an analog signal by the D/A converter 23 and output as an analog audio signal.

In FIG. 3, numerals 1 to n of the elements of each block are assigned corresponding to the respective tracks.

However, in the multi-track type digital magnetic recording/reproducing apparatus configured in this way, as the number of tracks N increases, n pieces of the above-mentioned reproducing circuits are required, and the circuit configuration becomes very large. In order to reduce the circuit scale as much as possible for such a multi-track reproduction system, a digital reproduction system including time division processing as shown in FIG. 4 has been proposed.

In FIG. 4, circuits up to the amplifier circuit 15 are provided for n tracks, and reproduction is performed from each track.

The amplified reproduction signal is input to the analog multiplexer 24, which selects and outputs the signal sequentially in a time-division manner. That is, the circuits after the analog multiplexer 24 are shared between the tracks.

The reproduced signals sequentially selected by the analog multiplexer 24 are converted into digital signals by the A/D converter 25, and the digital waveform equalization circuit 26 digitally converts the reproduced signals into waveforms to reduce distortion and waveform interference. . The waveform-equalized digital signal is digital P
The signal is input to the LL circuit 27 and the demodulation circuit 28, and a reproduced clock and reproduced data are extracted. In addition, digital PLL
The circuit 27 is described in detail in, for example, Japanese Unexamined Patent Publication No. 59-92410, and its explanation will be omitted. The reproduced data for each track thus obtained is input to the digital signal processing circuit 22, where it undergoes signal processing such as error correction, and is then converted into an analog signal by the D/A converter 23.
Output as an analog audio signal.

<Problems to be Solved by the Invention> However, even in the conventional configuration shown in FIG. It is necessary to provide a plurality of counters to generate , which poses a problem in that the circuit configuration becomes large-scale.

The present invention was devised in view of the above points, and relates to the above demodulation circuit, which has a plurality of tracks and has N
A reproduced clock generator capable of obtaining symbol clocks and frame synchronization signals necessary for demodulation with a simple circuit configuration in a code modulation type multi-track digital magnetic recording and reproducing device that converts bit data into M-bit code words. is intended to provide.

<Means to Solve the Problems> In order to achieve the above object, the recovered clock generator of the present invention has a format that is divided into certain blocks and a synchronization pattern is added to each block, N
In a multi-track digital magnetic recording and reproducing device that records digital signals on a finite number of tracks using a code modulation method that converts bit data into M-bit code words and transmits them, a 1st
a launch means, a first addition means for changing the memory contents of the first latch means in response to each track signal, and outputting a code synchronization signal in response to the memory contents of the first launch means. a second launch means provided corresponding to each track; and a second launch means for changing the memory contents of the second launch means in response to the code synchronization signal.
and means for generating a frame synchronization signal based on the contents stored in the second latch means.

Function> With the above configuration, the stored contents of the first latch means provided corresponding to each track are added by 11+1 by the first addition means according to the corresponding track signal, and It is determined whether the content stored in the first latch means has reached a predetermined value, and a code synchronization signal (symbol clock) is output in response to the predetermined value. The memory contents of the second launch means provided corresponding to each track are added by 1+1'' by the second adder according to the corresponding code synchronization signal, and the memory contents of the second launch means are also added. Then, a frame synchronization signal is output.

<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a detailed circuit of a main part of an embodiment of the present invention.

FIG. 2 shows an example of a recording format recorded on a magnetic tape used in a multi-track digital magnetic recording device in which the present invention is implemented, in which a digital signal is divided into pieces of data in parallel. Configure multiple tracks and add a synchronization pattern (hereinafter 5YN) to each channel data.
C) is added and recorded, and it is still 5YNC to 5YN.
The frame up to C (hereinafter referred to as a frame) consists of 5YNC, data, and parity for error correction, and the data is the N-pit data converted into an M-bit code word as described above, and the M-bit code. Words are referred to as symbols below. Therefore, this example shows an example in which the number of tracks is 20 and one frame is composed of 30 symbols.

In the reproduction circuit using time division processing to which the present invention is applied, as shown in FIG. 4, the digital PLL circuit 27 performs time division processing as described above.
As output data from the L circuit 27, data and track number are output for each bit.

The time-divided clock a, data b, and rack number c (k bits) outputted from the digital PLL circuit 27 are input to the terminals CK, DATA, and TRUCK No. in FIG. 1, respectively. In this example, the track number C is 5 bits, for example, track number 1.
．． 2, 3.4-20 as N 00000, 00001", '00010,
00011, ~'10011''. The data sent from the digital PLL circuit 27 is distributed to each track according to this track number.The multiplexer (MPX) 1 (1-1 to 1-n) receives the clock a and Clock d (d-1 to d) for inputting track number 〇 and distributing data b to each track
-n), and data b is distributed to each track and input to the M-bit shift registers 2 (2-1 to 2-n) of each track by clock d. Output e (e-1 to e-n) of M-bit shift register 2 (2-1 to 2-n)
) is distributed to each track and M-bit shift register 2
The input data was outputted in M-bit parallel format. This signal is output to a synchronization pattern (SYNC) detector 5 and decoder 10.

The 5YNC detector 5 detects a synchronization pattern (SYNC) in the format shown in FIG. 2. When 5YNC is detected, the 5YNC detector 5 outputs a SYNCNC detection signal amount. This is symbol clock generator 3, which will be described later.
'(3-1 to 3-n), frame counter generator 4 (
4-1 to 4-n). The symbol clock generator 3 (3-1 to 3-n) is composed of an L-bit latch and a tristite. The L bits are associated with an M bit codeword, for example M = 10 bits, = 4
Pit is fine.

To explain the signal flow regarding the signals distributed by MPXI-1, the symbol clock generator 3-1 is controlled by the clock d-1 distributed to each tiger, and outputs the data of the L pit. L bit data h
is added by +1 through the adder 6, and inputted again to the 7-volt clock generator 3-1. At this time, 5YNC detector 5
5YNC is detected by 5YNC detector 5, and 5YNC is detected by 5YNC detector 5.
When the YNC detection signal f is output, the adder 6 is cleared, the output g of the adder 6 becomes 'oooo', and 0000'' is latched in the symbol clock generator 3-1.

Next, when data b enters the M-bit shift register 2-1, the output of the symbol clock generator 3-1 becomes 0000.
", and this value is added by 1 in the adder 6, and the output g becomes '0001' again, and the symbol clock generator 3-
It is latched to 1. Each time data enters the M-pit shift register 2-1, the data is added in sequence. For example, if M=10 bits, the data is added until the signal becomes '1001'. When the signal becomes 1.001, the symbol clock detection circuit 8 detects 1001 and outputs the symbol clock k.The output of this symbol clock is sent to the adder 6, adder 7, and the next stage digital signal. Processing circuit (
22) in FIG. The symbol clock is given to the adder 6 as a clear signal, and the output g of the adder 6 becomes "oooo" again. The symbol clock also serves as a clock for latching the demodulated data 1 which has been demodulated into N-bit data through the decoder 10 by the M-bit data output e-1 of the M-bit shift register 2-1.

The frame counter generator 4-1 is composed of a Q-bit latch and a tristite. Assuming that one frame has 30 symbols as in this example, Q bits are Q=5 pits, for example, frame number 0°1.2.・・・、29ゝo
oooo",'00001".

It is expressed as 'oooio'',..., ゝ11101　.

The frame counter generator 4-1, like the symbol clock generator 3-1, is controlled by the clock d-1.

Like the adder 6, the adder 7 is cleared when 5YNC is detected by the 5YNC detector 5 and the 5YNC detection signal f is output, and the output i of the adder 7 becomes 500000''.
It is latched by the frame counter generator 4-1. Next, when data enters the M-bit shift register 2-1, the frame counter generator 4-1 outputs "ooooo" as the output j, and enters the adder 7. It is configured to add Q + 1'' only when symbol clock k is output, and does not add anything else. That is, addition and operation are performed for each symbol. Therefore, in the above case, the output i of the adder 7 is ``ooooo'' and is latched into the frame counter generator 4-1.In this way, data is sequentially entered into the M-bit shift register 2-1, and the symbol clock k is The output i of the adder 7 is 'oooooo' until the symbol clock k is detected, and when the symbol clock k is detected, the adder 7 adds 1+1", and the output i becomes 100001".From then on, every time the symbol clock k is detected, the output i of the adder 7 is 'ooooo'. The adder 7 adds, and the output j of the frame counter generator 4-1 is, in this example,
'11101 Increase at t. When the frame counter detection circuit 9 detects 11101#, the frame counter detection circuit 9 outputs an output n, the adder 7 is cleared, and the output i becomes ``ooooo''.

Furthermore, when the frame counter i and track number which are the outputs of the adder 7 are latched by the aforementioned symbol clock k, demodulated data 1, track number 〇, and 7 frame counter i are sent to the next stage digital signal processing circuit. be able to.

Note that although the above description has been made regarding the signals distributed by MPXl-1, the same applies to MPXl-2 to MPXl-8.

<Effects of the Invention> As described above, in the present invention, in a code modulation type multi-track digital magnetic recording/reproducing device having a plurality of tracks and converting N-bit data into an M-bit code word, demodulation The code synchronization signal (symbol clock) and frame synchronization signal necessary for the system can be constructed with a simple circuit of a launch means and an addition means, and the structure of the entire reproduction circuit can be simplified, making it suitable for LSI implementation. becomes.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram of a demodulation circuit including a reproduced clock generator according to an embodiment of the present invention, FIG. 2 is a recording format diagram used in an embodiment of the present invention, and FIG. 3 is a conventional reproduction circuit. Block diagram showing the configuration of 1-1~n...Multiplexer (MPX), 2-1~
n...M pit shift register, 3-1~n...Symbol clock generation 5.4-1~n...Frame counter generator, 5...Synchronization pattern (SYNC) detector, 6... - Adder; 7... Adder; 8... Symbol clock detector; 9... Frame counter detector; 10... Decoder.

Claims (1)

[Claims] 1. A code modulation method that has a format that is divided into fixed blocks and adds a synchronization pattern to each block, and that converts N-bit data into an M-bit code word and transmits it. In a multi-track digital magnetic recording and reproducing device in which digital signals are recorded on a finite plurality of tracks using a first addition means for changing the signal in response to a track signal; a means for outputting a code synchronization signal in response to the stored content of the first latch means; and a second latch provided corresponding to each track. means, second adding means for changing the stored contents of the second latch means in response to the code synchronization signal, and generating a frame synchronization signal based on the stored contents of the second latch means. 1. A regenerated clock generation device comprising: means for generating a clock; and a means for generating a clock.