JPS62124774U - - Google Patents
Info
- Publication number
- JPS62124774U JPS62124774U JP1986012164U JP1216486U JPS62124774U JP S62124774 U JPS62124774 U JP S62124774U JP 1986012164 U JP1986012164 U JP 1986012164U JP 1216486 U JP1216486 U JP 1216486U JP S62124774 U JPS62124774 U JP S62124774U
- Authority
- JP
- Japan
- Prior art keywords
- terminals
- insulating
- leads
- periphery
- large number
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005476 soldering Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 4
- 239000000853 adhesive Substances 0.000 claims description 2
- 230000001070 adhesive effect Effects 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 claims description 2
- 239000011295 pitch Substances 0.000 claims 1
- 239000010408 film Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Multi-Conductor Connections (AREA)
- Combinations Of Printed Boards (AREA)
Description
第１図は本考案に係る半田付け構体の一実施例
を示す部分平面図、第２図は第１図のＡ―Ａ線断
面図、第３図は第２図のＢ―Ｂ線断面図、第４図
は第１図の半田付構体の半田付前における基板側
の部分断面図である。第５図は従来の多端子の半
田付構体を有する薄膜ＥＬマトリクス型デイスプ
レイパネルの断面図で、左半分はＸ方向の断面図
、右半分はＹ方向の断面図、第６図は第５図のパ
ネルの要部拡大平面図、第７図は第５図のＣ―Ｃ
線拡大部分断面図、第８図は第７図の半田付構体
の半田付前の断面図である。第９図乃至第１１図
は本考案の前提となる多端子半田付構体を説明す
るためのもので、第９図は部分拡大平面図、第１
０図は第９図のＤ―Ｄ線断面図、第１１図は第１
０図のＥ―Ｅ線断面図である。
１……絶縁基板（ガラス基板）、４……フレキ
シブルリード、１０……端子、１３……フイルム
、１４……外部リード、１５……半田、１７……
絶縁層、１８……接着剤。
Fig. 1 is a partial plan view showing an embodiment of the soldering structure according to the present invention, Fig. 2 is a sectional view taken along the line AA in Fig. 1, and Fig. 3 is a sectional view taken along the line BB in Fig. 2. , FIG. 4 is a partial sectional view of the soldering structure of FIG. 1 on the board side before soldering. Fig. 5 is a sectional view of a thin film EL matrix type display panel having a conventional multi-terminal soldered structure, the left half is a sectional view in the X direction, the right half is a sectional view in the Y direction, and Fig. Figure 7 is an enlarged plan view of the main parts of the panel shown in Figure 5.
FIG. 8 is a cross-sectional view of the soldering structure of FIG. 7 before soldering. 9 to 11 are for explaining the multi-terminal soldering structure which is the premise of the present invention. FIG. 9 is a partially enlarged plan view, and FIG.
Figure 0 is a sectional view taken along the line DD in Figure 9, and Figure 11 is a cross-sectional view of Figure 1.
0 is a sectional view taken along the line E-E in FIG. 1... Insulating substrate (glass substrate), 4... Flexible lead, 10... Terminal, 13... Film, 14... External lead, 15... Solder, 17...
Insulating layer, 18...Adhesive.
Claims (1)
ストライプ状に形成された端子と、絶縁性フイル
ムの周辺部に前記端子と対応させて多数の外部リ
ードを形成したフレキシブルリードの前記外部リ
ードとを、予備半田を介して重ね合せて半田付け
したものにおいて、 前記絶縁基板の端子間の中央部に端子より突出
する所定膜厚の絶縁層を形成し、この絶縁層を前
記フレキシブルリードのフイルムの外部リード間
に絶縁性接着剤で固着したことを特徴とする多端
子の半田付構体。[Claims for Utility Model Registration] A large number of striped terminals formed at minute regular pitches on the periphery of an insulating substrate, and a large number of external leads formed in correspondence with the terminals on the periphery of an insulating film. The external leads of the flexible leads are overlapped and soldered together via preliminary solder, and an insulating layer of a predetermined thickness is formed in the center between the terminals of the insulating substrate and protrudes from the terminals, and this insulating layer is A multi-terminal soldering structure characterized in that a layer is fixed between the outer leads of the flexible lead film with an insulating adhesive.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986012164U JPS62124774U (en) | 1986-01-29 | 1986-01-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986012164U JPS62124774U (en) | 1986-01-29 | 1986-01-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62124774U true JPS62124774U (en) | 1987-08-07 |
Family
ID=30800041
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986012164U Pending JPS62124774U (en) | 1986-01-29 | 1986-01-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62124774U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0832195A (en) * | 1994-07-11 | 1996-02-02 | Nippondenso Co Ltd | Connection structure of composite printed board |
| JP2006277971A (en) * | 2005-03-28 | 2006-10-12 | Alps Electric Co Ltd | Contact board and its manufacturing method |
| WO2019146252A1 (en) * | 2018-01-23 | 2019-08-01 | 株式会社村田製作所 | Substrate bonding structure and substrate bonding method |
-
1986
- 1986-01-29 JP JP1986012164U patent/JPS62124774U/ja active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0832195A (en) * | 1994-07-11 | 1996-02-02 | Nippondenso Co Ltd | Connection structure of composite printed board |
| JP2006277971A (en) * | 2005-03-28 | 2006-10-12 | Alps Electric Co Ltd | Contact board and its manufacturing method |
| JP4541205B2 (en) * | 2005-03-28 | 2010-09-08 | アルプス電気株式会社 | Contact board and manufacturing method thereof |
| WO2019146252A1 (en) * | 2018-01-23 | 2019-08-01 | 株式会社村田製作所 | Substrate bonding structure and substrate bonding method |
| JPWO2019146252A1 (en) * | 2018-01-23 | 2020-12-17 | 株式会社村田製作所 | Substrate bonding structure and substrate bonding method |
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