JPS62122275A - Mis type semiconductor device - Google Patents
Mis type semiconductor deviceInfo
- Publication number
- JPS62122275A JPS62122275A JP26274985A JP26274985A JPS62122275A JP S62122275 A JPS62122275 A JP S62122275A JP 26274985 A JP26274985 A JP 26274985A JP 26274985 A JP26274985 A JP 26274985A JP S62122275 A JPS62122275 A JP S62122275A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- interface
- amorphous
- mis type
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 13
- 230000000694 effects Effects 0.000 abstract description 7
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000002747 voluntary effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
- H01L29/78687—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/1604—Amorphous materials
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、固体撮像素子のスイッチング素子や、液晶
ディスプレイの駆動素子に用いられる非晶質半導体を用
いたＭＩＳ型半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a MIS type semiconductor device using an amorphous semiconductor used as a switching element of a solid-state image sensor or a driving element of a liquid crystal display.
第 ３ 図はエレクトυニクス レークズ（Ｅｌｅｃｔ
ｒｏｎｉｃｓ Ｌｅｔｔｅｒｓ）ｖｏｌ、１８ （
１９８２）Ｐ５９９に示された従来の非晶質半導体を用
いたＭＩＳ型ＦＥＴの断面図であり、図において、１は
ゲート絶縁膜、３は非晶質シリコン、５は絶縁基板、６
はチャネルを制御するゲート電極、７，８は電流を取り
出すソース、ドレイン電極である。Figure 3 shows the elect
ronics Letters) vol, 18 (
1982) is a cross-sectional view of a MIS type FET using a conventional amorphous semiconductor shown in P599, in which 1 is a gate insulating film, 3 is amorphous silicon, 5 is an insulating substrate, and 6
Reference numerals 7 and 8 indicate a gate electrode for controlling the channel, and source and drain electrodes for extracting current.
次に動作について説明する。ドレイン電極８から、ソー
ス電極７に達する電流通路を矢印で示しである。電流は
非晶質シリコン３中を一度縦方向に通り、ゲート絶縁膜
１の界面に達する。その後、電流は絶縁膜−半導体の界
面に形成されたチャネルを通りソース部に達し、再び縦
方向に流れ、ソース電極７より外部に取り出される。Next, the operation will be explained. The current path from the drain electrode 8 to the source electrode 7 is indicated by an arrow. The current passes once through the amorphous silicon 3 in the vertical direction and reaches the interface of the gate insulating film 1. Thereafter, the current passes through the channel formed at the insulating film-semiconductor interface, reaches the source portion, flows vertically again, and is taken out from the source electrode 7.
従来のＭＩＳ型半導体装置は以上のように構成され、動
作しているので、界面準位の影響を強く受け、ドレイン
電流が長時間にわたり減少型のドリフトを示す等の問題
点があった。Since the conventional MIS type semiconductor device is configured and operated as described above, it is strongly influenced by interface states and has problems such as the drain current exhibiting a decreasing drift over a long period of time.
この発明は、上記のような問題点を解消するためになさ
れたもので、チャネル領域を絶縁膜−半導体界面から遠
ざけ、界面準位の影響をなくすことができる非晶質半導
体を用いたＭＩＳ型半導体装置を得ることを目的とする
。This invention was made in order to solve the above-mentioned problems, and it is an MIS type using an amorphous semiconductor that can move the channel region away from the insulating film-semiconductor interface and eliminate the influence of interface states. The purpose is to obtain a semiconductor device.
この発明に係る非晶質半導体を用いたＭＩＳ型半導体装
置は、非晶質半導体の組成を変化させ、絶縁膜−半導体
界面より内部に禁制帯幅の最小値をもたせたものである
。The MIS type semiconductor device using an amorphous semiconductor according to the present invention is one in which the composition of the amorphous semiconductor is changed so that the minimum value of the forbidden band width is provided inside the insulating film-semiconductor interface.
この発明においては、非晶質半導体の禁制帯幅の変化に
より、絶縁膜−半導体界面から離れたところにポテンシ
ャルの井戸が形成される。キャリア電荷は、この部分に
存在するため、界面準位の影響を受けないようにする。In this invention, a potential well is formed away from the insulating film-semiconductor interface due to a change in the forbidden band width of the amorphous semiconductor. Since carrier charges exist in this portion, they should not be affected by the interface level.
第１図はこの発明の一実施例である非晶質半導体を用い
たＭＩＳ型ＦＥＴの断面図であり、第２図はこの発明に
おけろ特徴的なバンド図である。FIG. 1 is a sectional view of a MIS type FET using an amorphous semiconductor, which is an embodiment of the present invention, and FIG. 2 is a characteristic band diagram of the present invention.
第１図において、１はゲート絶Ｒ膜、２，４は非晶質半
導体、例えば非晶質炭化シリコンであり、３は非晶質シ
リコンである。絶縁基板５上にゲー）・電極６を形成し
、ゲーｊ・絶縁膜１．非晶質半導体すなわちノ（ミ晶質
炭化シリコン２，４および非晶質シリコン３を同一の成
膜槽内で堆積した後、ソース、ドレイン電極７，８を形
成する。In FIG. 1, reference numeral 1 indicates a gate isolation film, 2 and 4 are amorphous semiconductors, for example, amorphous silicon carbide, and 3 is amorphous silicon. A gate electrode 6 is formed on an insulating substrate 5, and a gate electrode 6 is formed on an insulating film 1. After depositing an amorphous semiconductor, ie, amorphous silicon carbide 2, 4 and amorphous silicon 3 in the same film forming bath, source and drain electrodes 7, 8 are formed.
第２図に示したように、絶縁膜−半導体界面に禁制帯幅
の異なるアモルファス半導体を形成することにより、ポ
テンシャルの井戸が形成される。As shown in FIG. 2, a potential well is formed by forming amorphous semiconductors having different forbidden band widths at the insulating film-semiconductor interface.
するとキャリア電荷は、この井戸に存在するため、界面
準位の影響を受けないようになる。Then, since carrier charges exist in this well, they are not affected by the interface state.
このような構造をもつＭＩＳ型ＦＥＴにおいては、電流
通路は第１図の矢印のごとくなり、やはり界面準位の影
響を受けないようになる。なお、第２図で、Ｅζは伝導
帯、Ｅνは価電子帯、ＥＦはフェルミレベルを示す。In a MIS type FET having such a structure, the current path is as shown by the arrow in FIG. 1, and is not affected by the interface state. In FIG. 2, Eζ is a conduction band, Eν is a valence band, and EF is a Fermi level.
なお、上記実施例では、非晶質半導体として非晶質炭化
シリコンおよび非晶質シリコンを用いたものを示したが
、禁制帯幅の大きな半導体に非晶質窒化シリコン、禁制
帯幅の小さな半導体に非晶質シリコンゲルマニウム、非
Ｂ’ＪＲシリコンススヲ用いてもよい。さらに禁制帯幅
の変化は、段階的なものではなく、連続的なものでもよ
い。In the above example, amorphous silicon carbide and amorphous silicon are used as amorphous semiconductors, but amorphous silicon nitride is used as a semiconductor with a large band gap, and a semiconductor with a small band gap is used. Alternatively, amorphous silicon germanium or non-B'JR silicon may be used. Furthermore, the change in the forbidden band width may be continuous rather than stepwise.
また上記実施例ではゲート電極６とソース電極７、ドｔ
・イン電極８が絶縁膜−半導体界面をはさむスタガ電極
構造のＭＩＳ型ＦＥＴの場合について説明したが、ゲー
ト電極６とソース電極７．ドレイン電極８が、同じ側に
あるコプレーナ電極構造のＭＩＳ型ＦＥＴやＣＯＤ等の
他のＭＩＳ型半導体装置であってもよく、上記実施例と
同様の効果を奏する。Further, in the above embodiment, the gate electrode 6 and the source electrode 7,
- Although the case of a MIS type FET with a staggered electrode structure in which the in-electrode 8 sandwiches the insulating film-semiconductor interface has been described, the gate electrode 6 and the source electrode 7. Other MIS type semiconductor devices such as a MIS type FET or COD having a coplanar electrode structure in which the drain electrode 8 is located on the same side may be used, and the same effects as in the above embodiments can be obtained.
この発明は以上説明しｔコとおり、Ｍ工Ｓ構造を禁制帯
幅の異なる非晶質半導体で形成し禁制帯幅の最小値が絶
縁膜−半導体界面より内部にもたせたので、界面準位の
影響をなくすことができ、信頼性の高い半導体装置が得
られる効果がある。As explained above, in this invention, the M/S structure is formed of amorphous semiconductors with different forbidden band widths, and the minimum value of the forbidden band width is located inside the insulating film-semiconductor interface. This has the effect of eliminating the influence and providing a highly reliable semiconductor device.
第１図はこの発明の一実施例によるＭＩＳ型ＦＥＴを示
す断面図、第２図はこの発明における特徴的なバンド図
、第３図は従来のアモルファス半導体ＭＩＳ型ＦＥＴを
示す断面図である。
図において、１はゲート絶縁膜、２，４は禁制帯幅の大
きな非晶質半導体、３は禁制帯幅の小さな非晶質シリコ
ンである。
なお、各図中の同一符号は同一または相当部分を示す。
代理人 大 岩 増 雄 （外２名）第２図
手続補正書（自発）
１・事件の表示 特願昭８０−２８２７４９号２、
発明（１）名称Ｍ Ｉ Ｓ型半導体装置３、補正をす
る者
事件との関係 特許出願人
代表者志岐守哉
４、代理人
５、補正の対象
明細書の発明の詳細な説明の欄
６、補正の内容
（１）明細書第１頁２０行の「レータズ」を、「レター
ズ」と補正する。
（２）同じく第２頁ｌＯ行の「ゲート絶縁膜１の界面」
を、「ゲート絶縁膜１との界面」と補正する。
（３）同じく第３頁１４行の「受けないようにする。」
を、「受けないようになる。」と補正する。
（４）同じく第５頁１４行の「最少値が」を、「最少値
を」と補正する。
以上FIG. 1 is a sectional view showing a MIS type FET according to an embodiment of the present invention, FIG. 2 is a characteristic band diagram of the present invention, and FIG. 3 is a sectional view showing a conventional amorphous semiconductor MIS type FET. In the figure, 1 is a gate insulating film, 2 and 4 are amorphous semiconductors with a large band gap, and 3 is amorphous silicon with a small band gap. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Diagram 2 procedural amendment (voluntary) 1. Indication of case Patent Application No. 1980-282749 2,
Invention (1) Name M I S type semiconductor device 3, Relationship with the case of the person making the amendment Moriya Shiki, representative of the patent applicant 4, Agent 5, Detailed description of the invention in the specification subject to amendment 6, Contents of the amendment (1) "Ratazu" in line 20 of page 1 of the specification is amended to "Letters". (2) “Interface of gate insulating film 1” also on page 2, row 10
is corrected as "the interface with the gate insulating film 1". (3) Also on page 3, line 14, “I will try not to accept it.”
is corrected by saying, ``I will no longer receive it.'' (4) Similarly, on page 5, line 14, "minimum value" is corrected to "minimum value". that's all
Claims (2)
るＭＩＳ型半導体装置において、前記非晶質半導体の組
成を変化させ絶縁膜−半導体界面より内部に禁制帯幅の
最小値をもたせたことを特徴とするＭＩＳ型半導体装置
。(1) In a MIS type semiconductor device consisting of an amorphous semiconductor, a gate insulating film, and a gate electrode, the composition of the amorphous semiconductor is changed to provide a minimum value of the forbidden band width inside the insulating film-semiconductor interface. An MIS type semiconductor device characterized by:
が最小であることを特徴とする特許請求の範囲第（１）
項記載のＭＩＳ型半導体装置。(2) Claim (1) characterized in that the amorphous semiconductor consists of three layers, and the forbidden band width of the central layer is the smallest.
The MIS type semiconductor device described in .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26274985A JPS62122275A (en) | 1985-11-22 | 1985-11-22 | Mis type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26274985A JPS62122275A (en) | 1985-11-22 | 1985-11-22 | Mis type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62122275A true JPS62122275A (en) | 1987-06-03 |
Family
ID=17380049
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26274985A Pending JPS62122275A (en) | 1985-11-22 | 1985-11-22 | Mis type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62122275A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0383743A2 (en) * | 1989-02-17 | 1990-08-22 | International Business Machines Corporation | Thin film transistor |
| US5221631A (en) * | 1989-02-17 | 1993-06-22 | International Business Machines Corporation | Method of fabricating a thin film transistor having a silicon carbide buffer layer |
| US5272361A (en) * | 1989-06-30 | 1993-12-21 | Semiconductor Energy Laboratory Co., Ltd. | Field effect semiconductor device with immunity to hot carrier effects |
| EP0587520A1 (en) * | 1992-08-10 | 1994-03-16 | International Business Machines Corporation | A SiGe thin film or SOI MOSFET and method for making the same |
| US6731531B1 (en) | 1997-07-29 | 2004-05-04 | Micron Technology, Inc. | Carburized silicon gate insulators for integrated circuits |
| US6835638B1 (en) | 1997-07-29 | 2004-12-28 | Micron Technology, Inc. | Silicon carbide gate transistor and fabrication process |
| US7005344B2 (en) | 1997-07-29 | 2006-02-28 | Micron Technology, Inc. | Method of forming a device with a gallium nitride or gallium aluminum nitride gate |
-
1985
- 1985-11-22 JP JP26274985A patent/JPS62122275A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0383743A2 (en) * | 1989-02-17 | 1990-08-22 | International Business Machines Corporation | Thin film transistor |
| US5221631A (en) * | 1989-02-17 | 1993-06-22 | International Business Machines Corporation | Method of fabricating a thin film transistor having a silicon carbide buffer layer |
| US5272361A (en) * | 1989-06-30 | 1993-12-21 | Semiconductor Energy Laboratory Co., Ltd. | Field effect semiconductor device with immunity to hot carrier effects |
| EP0587520A1 (en) * | 1992-08-10 | 1994-03-16 | International Business Machines Corporation | A SiGe thin film or SOI MOSFET and method for making the same |
| US5461250A (en) * | 1992-08-10 | 1995-10-24 | International Business Machines Corporation | SiGe thin film or SOI MOSFET and method for making the same |
| US6731531B1 (en) | 1997-07-29 | 2004-05-04 | Micron Technology, Inc. | Carburized silicon gate insulators for integrated circuits |
| US6835638B1 (en) | 1997-07-29 | 2004-12-28 | Micron Technology, Inc. | Silicon carbide gate transistor and fabrication process |
| US7005344B2 (en) | 1997-07-29 | 2006-02-28 | Micron Technology, Inc. | Method of forming a device with a gallium nitride or gallium aluminum nitride gate |
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