JPS62121646U - - Google Patents
Info
- Publication number
- JPS62121646U JPS62121646U JP973286U JP973286U JPS62121646U JP S62121646 U JPS62121646 U JP S62121646U JP 973286 U JP973286 U JP 973286U JP 973286 U JP973286 U JP 973286U JP S62121646 U JPS62121646 U JP S62121646U
- Authority
- JP
- Japan
- Prior art keywords
- computer
- interrupt signal
- shift
- register
- shift clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Safety Devices In Control Systems (AREA)
Description
第１図はこの考案の一実施例を示すブロツク結
線図、第２図は従来のブロツク結線図、第３図は
従来の装置の動作を説明するためのタイミング図
である。
図において１はＣＰＵ、４はメモリ、５は出力
インタフエース回路、７はシフトクロツク発生回
路、１０，１２，１４はレジスタ、１６は多数決
回路、１８は割込み信号発生回路である。なお、
各図中同一符号は同一または相当部分を示す。
FIG. 1 is a block wiring diagram showing an embodiment of this invention, FIG. 2 is a conventional block wiring diagram, and FIG. 3 is a timing diagram for explaining the operation of the conventional device. In the figure, 1 is a CPU, 4 is a memory, 5 is an output interface circuit, 7 is a shift clock generation circuit, 10, 12, and 14 are registers, 16 is a majority circuit, and 18 is an interrupt signal generation circuit. In addition,
The same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
込み信号発生回路と、上記割込み信号により初期
化され所定のプログラムを実行する計算機と、計
算機から出力される制御データをシフトクロツク
により読込む３段のシフトレジスタと、計算機の
コントロールバスを入力されてシフトクロツクを
上記シフトレジスタへ供給するシフトクロツク発
生回路と、上記３段のシフトレジスタの出力が入
力されて、多数決論理出力を生成する多数決回路
を有することを特徴とする制御装置。 An interrupt signal generation circuit that generates an interrupt signal three times at regular time intervals, a computer that is initialized by the interrupt signal and executes a predetermined program, and a three-stage shift that reads control data output from the computer using a shift clock. A register, a shift clock generation circuit that receives a control bus of a computer and supplies a shift clock to the shift register, and a majority circuit that receives the outputs of the three-stage shift register and generates a majority logic output. control device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP973286U JPS62121646U (en) | 1986-01-27 | 1986-01-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP973286U JPS62121646U (en) | 1986-01-27 | 1986-01-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62121646U true JPS62121646U (en) | 1987-08-01 |
Family
ID=30795322
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP973286U Pending JPS62121646U (en) | 1986-01-27 | 1986-01-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62121646U (en) |
-
1986
- 1986-01-27 JP JP973286U patent/JPS62121646U/ja active Pending
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