JPS6211970A - Address generating circuit - Google Patents

Abstract

PURPOSE:To produce an address suited to a virtual shift with small instruction length by providing a means which clears the 2nd counter to '0' with the control signal of the 1st counter and an adder which adds the outputs of both counters. CONSTITUTION:When the shift average filtering is carried out, a base counter load command is supplied to a control part 4 via control input terminals 7, 8 and 9 for a base counter 1 which produces first the value of a base pointer. The part 4 delivers a load command to the counter 1 and a clear instruction to an index counter 2. Then the counter 1 is set to the data 0Fh applied to a data bus input terminal 6 with the rise of the clock applied to a clock input terminal 5. While the counter 2 is cleared. Both outputs 0Fh and 00h of counters 1 and 2 are added together by an adder 3 and an effective address 0Fh is delivered. Thus the reference is possible to the present input sample.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a digital signal 9n and an address generation circuit for a ring processor.

(Previous Technology Point) A digital signal processing processor is generally composed of an input section, an arithmetic section, a storage section, a control section, etc., and includes a modem, a digital filter, and a codec (CODEC).

It is used in various fields such as echo cancellers, speech recognition, speech synthesis, and speech analysis.

In these application fields, especially in filtering, when performing calculations on past several sample data, it is necessary to move the sampled data in the memory every 111L times. However, with current signal processing processor architectures, memory-to-memory transfers take a very long time, so they are actually achieved by moving data pointers without moving the data using virtual shifts. FIG. 2 is a diagram explaining the concept of virtual shift.

For example, y(t)=(x(t-3) x(t-2)+x(t-1
)+x(t))/4 In the case of the moving average filter represented by (1), the past three samples x(t-3) are used to calculate the output y(t) at a certain time t.

Assume that x(t-2), x(t-1) and current data x(t) are in memory. And then pointer DP
is assumed to point to x(t). At this time, if indirect addressing using pointer DP is possible as the addressing mode, each sample is
It can be read by incrementing by -1.

However, since the pointer DP has been moved, the address for storing the input data x(t+1) at time t+1 must have another pointer or must be calculated separately based on the number of data used in the calculation. If you have another pointer, a two-step operation is required: incrementing the value of that pointer to store new data, and loading the value of the other pointer as initial data into the previous pointer. . Further, if the initial data of the pointer 10 is to be calculated separately from the number of data, a complicated circuit must be provided to subtract n from the pointer 10.

As a way to solve these drawbacks, Fujitsu's signal processing processor (MB8764 General Purpose Digital Signal Processing LSI User Manual, published in April 1982) outputs an effective address by the sum of the pointer value and the literal feed of the instruction. It uses so-called index-qualified addressing. Although index-qualified addressing provides maximum efficiency in terms of instruction execution, it has the additional disadvantage of increasing the overall instruction length by requiring a literal field to provide an offset value from the pointer during the instruction. . For example, it is fine if one processor has only one memory, but if the system has a pointer mechanism with 11 points for several memories, an instruction field is required for each, and the instruction length becomes very large. becomes longer.

In order to keep the instruction length short, an address generation circuit having two pointers can be used as a conventional method.

In this case, there are a method of using two pointers separately and a method of referencing the memory by the sum of the values of the two pointers. Intel 80, a general-purpose microcomputer
86 (published by The 8086 Book Sanpo Publishing in March 1983)
In this case, the former two pointers are SI and DI, and the latter two pointers have an indirect addressing mode such as BX+Sr. The former two-pointer is convenient for transferring data between memories, but it contradicts the fact that the architecture of signal processing processors is designed to minimize the number of transfers between memories. The virtual shift described above is relatively efficiently realized by the latter indirect addressing using two pointers. First, set the base pointer BX to have a pointer value indicating the current input data,
Reference to past data is an index pointer SI
is referenced by incrementing by -1 from zero. According to this addressing method, a program for obtaining one output only needs to sequentially change the index pointer SI from zero, and is no longer dependent on the actual address of data in memory.

After one output has been calculated, the base pointer BX is incremented by one and the index pointer SI is set to zero, so that the next output can be calculated. This method is successfully implemented in general-purpose microcomputers, but signal processing microprocessors use a pipeline architecture to speed up calculations, making it possible to supply data to the calculation unit without interruption. This is a way to make the most of the processor's capabilities.

Therefore, in the previous example of filtering using BX+ST addressing, when the calculation of one output is completed, the base pointer BX and index pointer S
The problem is that each of them needs to be updated.

(Object of the Invention) An object of the present invention is to provide an address generation circuit that can shorten the instruction length and efficiently implement the virtual shift.

(Structure of the Invention) The present invention includes a first counter, a second counter, means for clearing the contents of the second counter to zero by a control signal of the first counter, and and the output of the second counter.

(Principle of the Invention) FIG. 3 shows an example of the order of memory access when performing the moving average filtering shown in equation (1) above. y(
t), the current input sample x(t) is stored at address 2, and the values of the past three samples, x(t-
1), x(t-2), and x(t-3) are sequentially referenced and accumulated. Next, to calculate y(t+1), set the address to x
Move (t+1) to address Z+1 where it should be stored, input and store the input sample x(t+1.), and similarly store x(t).
, x(t-11x(t-2)) in order.

In such memory access, the starting address of the sample in the memory required to calculate the output at a certain time (
In calculating y(t), x(t), y(t+1.)
For x(t+1.), similarly, for y7t+2. ), x(t+2)) is indicated by a base pointer, and the remaining samples are referenced by modifying the value of the base pointer with an index pointer giving an offset from the base pointer. In such indirect addressing using the sum of two pointers, only the index pointer is updated in most steps. Furthermore, when the base pointer is changed, the index pointer is often set to zero.

Focusing on this, by connecting the increment signal of the counter that holds the base pointer value to the clear terminal of the counter that holds the index pointer value, the index pointer will automatically change when the base pointer is updated. By clearing to zero, all pointer movements can be realized with one instruction, and since either of the two pointers -JjL, or l- is not changed, the instruction length is the field for one pointer and which pointer is changed. Only one bit is required to indicate.

(Example) FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, 1 is a base counter, 2 is an index counter, 3 is an adder, 4 is a control section, 5 is a clock input terminal of the counter, 6 is a data bus input terminal for loading the counter value, and 7.8.9 is a data bus input terminal for loading the counter value. This is a control input terminal. Base counter 1 is an up/down counter that loads, +], or -1 at the rising edge of the clock when any of the load, up, or down signals is at a low level. , and an up/down counter with a clear function. The control unit 4 will be described in detail later.

When performing the moving average filtering shown in equation (1) above, the circuit shown in Figure 1 uses two counters, an adder,
The operation when the bit length of the output effective address is all 8 bits will be explained with reference to FIG. All numerical values used in the following explanation with (h) added at the end are hexadecimal numbers. As shown in FIG. 4, x(t) is located at address 0F(h) of memory L.
) address x(t-1), on(h) address x(t-2)
) is assumed to have x(t-3) at address oc(h). First, base counter 1 generates the value of the base pointer.
A base counter load command is input to the control unit 4 through the control input terminals 7.8.9, and the control unit 4 outputs a load command to the base counter 1 and a clear command to the index counter 2. Based on the rise and fall of the clock applied to the tarlock input terminal 5, the base counter 1 receives the data ``0'' applied to the data bus input terminal 6.
F(h)" and the index counter 2 is cleared. Then, the output of the base counter 1 is "0F(h)".
``'' and the output ``oo(h)'' of the index counter 2 are added together by an adder 3, and an effective address ``0F(h)'' is output, which allows x(t) to be referenced. Next, a command to decrement the index pointer is input via the control input terminal 7.8.9, and only a down command to the index counter 2 is generated from the control unit 4, and the clock applied to the tarock input terminal 5 is At the rising edge, the index counter 2 is incremented by 11 steps and becomes "FF(h
)".Adder 3 outputs base counter 1's output "0F(h)" and index counter 2's output "0F(h)".
FF(h)" and outputs "0E(h)" as the effective address. In this way, x(t-1,) can be referenced. Similarly, next time, control input terminals 7 and 8 A command to decrement the index pointer is input through the input terminal 9, and only a down command to the index counter 2 is issued from the control unit 4. is incremented by one step and becomes "EE(h)". Then, adder 3 adds the output "0F(h)" of base counter 1 and the output "FE(h)" of the index counter.
0D(h)" as an effective address. In this way, x(t-2) can be referenced.

Similarly, a command to decrement the index pointer is input via the control input terminals 7.8.9, and only a down command to the index counter 2 is generated from the control section 4, which is applied to the tally input terminal 5. As the clock rises and falls, the index counter 2 is incremented by 11 steps and becomes "FD(h)". Then, the adder 3 adds the output "0F(b)'" of the base counter 1 and the output "FD(h)" of the index counter to form 'oc(h)'.
” as the effective address. In this way, x
(t-3) can be referred to. In this way, x(t),
x(t-1), x(t-2), and x(t-3) are referenced, and the moving average filter output y(t) is determined by calculating the sum of these and dividing by 4. Next, in order to obtain the output of y(t+1), x(t+1) is input and needs to be stored at address '10''h in the memory. An increment command is input, and the control unit 4 generates an up signal to the base counter 1 and a clear signal to the index counter 2.The contents of the base counter 1 are changed by the rising edge of the clock applied to the clock input terminal 5. At the same time, the index counter 2 is commanded to clear.By this clear signal, the contents of the index counter 2 are set to 'on(h)''.
)”, and in adder 3, the output of base counter 1 is “1”.
0(h)”Output of index counter 2”00(h)
'' is added and the effective address ``10(h)'' is output. With this - instruction, the address that previously indicated 'oc(h)' where x(t-3) was stored is changed to x(t+
1) is changed to 'to(h)', which is the storage address.After that, the index counter 2 is decremented to x(t), x(t-1) in the same way as for light.

By referring to x(t-2), three values necessary for calculating y(t+1) can be extracted.

FIG. 5 is a diagram showing an example of the configuration of the control section 4 shown in FIG. 1. 1
00.101 is a 2-4 decoder (Texas Instruments 74LS139 or equivalent), 102
is an inverter, 103 is an OR of negative logic input and negative logic output.
Gate (Texas Instruments 74.LSl)
1 or its equivalent) and 7.8.9 is the control input terminal,
107.1.08°109 are control signal terminals to the base counter, UP, DOWN, LOAD+, respectively.
, : connection sale, 110.111. .

112 and 113 are control signal terminals to the index counter, respectively UP, DOWN, LOAD,
Connected to CLEAR. Control input terminal 9 is the first
It is connected via an inverter 102 to the enable terminal of a 2-4 decoder 100 that generates a control signal to the base counter 1 in the figure, and directly to the enable terminal of a 2-4 decoder 101 that generates a control signal to the index counter 2. Connected. The control input terminal 9 is a bit for selecting update of the base counter and index counter,
When terminal 9 is '0'', the index counter is 11.
When it is 111, the base counter is selected.

Control input terminals 7 and 8 are 2 bits that indicate mode control of the counter; when +40011, the counter value is not updated (NOP), and when it is "01", the data bus value is loaded into the counter (LOAD). ), when it is "10", the counter is incremented by one step (DOWN), and when it is "11", the counter is incremented by +1 (UP). 2-4 decoder that generates the control signal to the base counter. 1 Yl, Y
2. The Y3 output is connected as a clear signal to the index counter via an OR gate 103 with negative logic input and negative logic output, and when the base counter is updated, the index counter is automatically cleared. .

The present invention can be implemented in the following manner.

In the above embodiment, the base counter is incremented;
The virtual shift was realized by decrementing the index counter, but by reversing the memory address assignment method, it is also possible to change the base counter to be decremented and the index counter to be incremented.

In addition, instead of having the base pointer have the address of the current input sample, by having the address of the most past sample to be referenced, the base counter,
Both index counters can be referenced by counters that increment by +1. According to this method, the two counters can be implemented as unidirectional counters instead of up/down counters.

Furthermore, even when two pointers are moved in the same direction, by reversing the allocation of memory addresses, both the base counter and the index counter can be realized by counters that increment by -1. All these modifications are included in the present invention.

(Effects of the Invention) An advantage of the present invention is that by using the control signal to the base counter as a clear signal to the index counter, it is no longer necessary to lengthen the instant action length. Another advantage is that an address suitable for virtual shift, which is often used for filtering, etc., can be generated without inserting an extra instruction for updating two pointers.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a diagram explaining virtual shift, FIG. 3 is a diagram explaining details of the present invention, and FIG. 4 is a diagram showing necessary explanations of the embodiment. FIG. 5 is a detailed view of a part of the embodiment. In the figure, 1 is a base counter, 2 is an index counter, 3 is an adder, 4 is a control section, 5 is a clock input terminal, 6 is a data bus input terminal for loading the counter value, 7.8.9 is a control This is an input terminal. A-1 Figure 71-2

Claims (1)

[Claims] a first counter, a second counter, means for clearing the contents of the second counter to zero by a count control signal for the first counter, and an output of the first counter and the second counter; an address generation circuit comprising at least an adder that adds the outputs of the address generation circuit;