JPS6257067A - Address generating circuit - Google Patents

Abstract

PURPOSE:To attain generation of address suitable for vertual shift used frequently in filtering by using a control signal to a base counter as a clear signal to an index counter selectively. CONSTITUTION:In the case of the indirect addressing mode, the level of a mode input terminal 10 goes to 0. When a load instruction of the base counter 1 is inputted via control inputs 7, 8, 9, the base counter 1 is set to a data fed to a data bus input terminal 6 at the leading of a clock. When the load instruction to an index counter 2 via the control inputs 7, 8, 9, the load instruction to the index counter 2 from a control section 4 is outputted and the index counter 2 is set to a data fed to a data bus input terminal 6 at the leading of the clock. The adder 3 adds the outputs of the base counter 1 and the index counter 2 to output an effective address. As to the mode realizing efficiently the virtual shift, the level of the mode input terminal 10 is brought into 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an address generation circuit for a digital signal processor.

[Conventional technology]

Digital signal processing processors generally consist of an input section, a calculation section, a storage section, a control section, etc., and are used in various fields such as modems, digital filters, codecs, echo cancellers, speech recognition, speech synthesis, and speech analysis. It is used.

In these application fields, particularly in filtering, when performing operations on past several sample data, it is necessary to move the sampled data on memory every unit time.

However, in the current architecture of signal processing processors, memory-to-memory transfer takes a very long time, so it is actually achieved by moving the data pointer without moving the data using a virtual shift.

FIG. 2 is a diagram explaining the concept of virtual shift.

For example, y(L)=(x(L-3)+x(t-2)+x(t-1
)+x(t))/4 In the case of a moving average filter expressed as (1), in order to calculate the output y(t) at a certain time t, the past three samples x(t-3), x(t-2 >,
Assume that x(t, -1> and current data X(shi) are on the memory.

It is assumed that the pointer DP is pointing to x(t) at that time. At this time, if indirect addressing using the pointer DP is possible as the addressing mode, each sample can be read by incrementing the pointer DP by 1. However, because the pointer DP has been moved, the input data x(t+
1> must have another pointer, or the data used for calculation must be calculated separately from the number of items.

If you have another pointer, a two-step operation is required: incrementing the value of that pointer to store new data, and loading the value of the other pointer as initial data into the previous pointer DP. be. Furthermore, if the initial data of the pointer DP is calculated separately from the number of data items, a complicated circuit must be provided to subtract n from the pointer DP.

As a method for solving these drawbacks, a known signal processor (for example, MB8764 manufactured by Fujitsu) employs so-called index-qualified addressing in which an effective address is output by the sum of a pointer value and an instruction field. Although index-qualified addressing provides maximum efficiency in terms of instruction execution, it has another drawback: it requires a literal field to provide an offset value from the pointer during the instruction, which increases the overall instruction length. 4 For example, it is fine if one processor has only one memory, but if the system has a pointer mechanism with individual targets for several memories, an instruction field is required for each, and the instruction length is It becomes very long.

In order to keep the instruction length short, an address generation circuit having two pointers can be used as a conventional method.

In this case, there are a method of using two pointers separately and a method of referencing the memory by the sum of the values of the two pointers. Intel 808, a general-purpose microcomputer
6 has SI and DI as the former two pointers, and has an indirect addressing mode such as BX+SI as the latter two pointers.

The former two-pointer is convenient for transferring data between memories, but it contradicts the fact that the architecture of signal processing processors is designed to minimize the number of transfers between memories.

The virtual shift described above is relatively efficiently realized by the latter indirect addressing using two pointers. First, the base pointer BX has a pointer value indicating the current input data, and past data is referenced by incrementing the index pointer SI by -1 from zero. According to this addressing method, a program to obtain one output uses index pointer S
It is only necessary to change I sequentially from zero, and it is no longer dependent on the actual address of the data in memory. After one output has been calculated, the base pointer BX is incremented by one and the index pointer Zl is set to zero, so that the next output can be calculated.

[Problem that the invention seeks to solve]

In general-purpose microcomputers, the conventional method described above can be successfully implemented, but in order to speed up the calculations, signal processing microprocessors adopt a big-line architecture, which supplies data to the calculation unit without interruption. There must be.

Therefore, in the previous example of filtering by BX + SI atrage, when the calculation of one output is completed, the base pointer BX and index pointer S
The problem is that each of I needs to be updated.

An object of the present invention is to provide an address generation circuit that can shorten the instruction length and efficiently implement the virtual shift.

[Means for solving problems]

The circuit of the present invention includes a first counter, a second counter, clearing means for selectively clearing the contents of the second counter to zero by a counting control signal for the first counter, and [Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 3 shows an example of the order of memory access when performing the moving average filtering shown in equation (1) above. y(
At the time of calculation of t), the current input sample x(t) is stored at address 2, and the values of the past three samples, x(t
-1>, x (t-2>, x(t-3>) are referred to in order and accumulated. Next, for the calculation of y(t+1>, the address is set to address z+1 where x(t+1) should be stored. , enter and store the input sample x(t+1), and similarly x(t
), x (t-1), x (t-2>) are sequentially referenced and accumulated. In such memory access, the first address ( In calculating y(t), X(t), y(t
+1>, then x(t+1); similarly, y(t+2>
In, x(t, +2>) is indicated by a base pointer,
The remaining samples are referenced by modifying the value of the base pointer with an index pointer that provides an offset from the base pointer. In such indirect addressing using the sum of two pointers, only the index pointer is updated in most steps. Furthermore, when the base pointer is changed, the index pointer is often set to zero. Focusing on this, by connecting the increment signal of the counter that holds the base pointer value and the clear terminal of the counter that holds the index pointer value through a switch, when this switch is open, This is an address generation circuit using two pointers. Furthermore, when the switch is closed and the base pointer is updated, the index pointer is automatically cleared to zero, so all pointer movement can be achieved with one instruction. Since only one of the pointers is changed, the instruction length only requires a field for one pointer and two bits indicating which pointer to change and whether to open or close the switch. Furthermore, since the bit for opening or closing the switch is not normally required for each instruction, it is not necessarily necessary to allocate the field of the instruction by connecting the mode flip-flop tab.

FIG. 1 is a block diagram showing one embodiment of the present invention. The address generation circuit of FIG. 1 includes a base counter 1, an index counter 2, an adder 3, a control section 4, a clock input terminal 5 of the counter, a data bus input terminal 6 for loading the counter value, and a control section 4. Input terminals 7.8 and 9
and a mode input terminal 10. When the load, up, or down signal is low level, base counter 1 is loaded and +1 at the rising edge of the clock.
, -1, and the index counter 2 is also an up/down counter with load, up, down, and clear functions. The control unit 4 will be described in detail later.

First, an indirect addressing mode using two pointers similar to the Intel 8086 BX1S[ mentioned above will be explained. In this case, mode input terminal 10 is set to °°0'°
When a load command for the base counter 1 is input through the control unit cuff 8.9, the base counter 1 is set to the data applied to the data bus input terminal 6 at the rising edge of the clock.

Next, when a load command for index pointer 2 is input through the control unit cuff 8.9, a load command for index counter 2I\ is output from the control unit 4, and index counter 2 is loaded with data by the rising edge of the clock. It is set to the data applied to the bus input terminal 6.

Adder 3 adds the outputs of base counter 1 and index counter 2 and outputs an effective address.

Next, a mode that can efficiently implement a virtual shift will be described. In this case, the mode input terminal 10 is set to ``1°''.As an example, when performing the moving average filtering shown in equation (+) above, the circuit shown in Figure 1 uses two counters, an adder, and an output signal. The operation will be explained when the bit length of all effective addresses is 8 bits.The numerical values used in the following explanation are all hexadecimal numbers with (h) added at the end.

As shown in Figure 4, x(t
) is at address 0E(h) and x(t-1> is 0E)(h)
x(t-2) at address oc(h), x(t-3>
Suppose that is stored.

゛ First, the base counter 1 that generates the value of the base pointer receives the base counter load and index counter clear commands to the control unit 4 through the control input terminals 7, 8, and 9, and the control unit 4 outputs the base counter 1. A load command to index counter 1 and a clear command to index counter 2 are output, and with the rise of the clock applied to clock input terminal 5, base counter 1 outputs the data “OF” (h) applied to data bus input terminal 6. ), and index counter 2 is cleared.

And the output “OF” (h) of base counter 1,
The output "00" (h) of the index counter 2 is added by the adder 3, and an effective address "'OF' (I]) is outputted so that x (t) can be referred to.

Next, a command to decrement the index pointer is input through the control input terminals 7, 8.9, and only a down command to the index counter 2 is generated from the control unit 4, and the clock applied to the clock input terminal 5 is At the rising edge, the inte-sock counter 2 is incremented by one step and becomes "FF" (h), and the adder 3 outputs the output "OF" (l) of the base counter 1 and the output "FF" of the index counter 2. (h) is added and “OR” (h
) as an effective address, and output X(
t-1> can be referenced.

Next, similarly, a command to decrement the index pointer is input via the control input terminals 7.8.9, and only a down command to the index counter 2 is generated from the control unit 4, which is applied to the clock input terminal 5. At the rising edge of the clock, inte-sock counter 2 is incremented by one step and becomes "l?E" (h), and in adder 3, the output "'OF" (h) of base counter 1 and the output of index counter are incremented by one step. Add “FB” (h) and “OD”
" (h) is output as an effective address. In this way, X (t-2) can be referenced.

Next, similarly, a command to decrement the index pointer is input via the control input terminals 7, 8.9, and the control unit 4 generates only a down command to the index counter 2, which is applied to the clock input terminal 5. With the rise of the clock, the index counter 2 is incremented by one step and becomes "F D" (h)2, and the adder 3 uses the output "OF" (h) of the base counter 1 and the integer. The output "FD" (h) of the sox counter is added and "Oc" (h) is output as an effective address. In this way, x(t-3) can be referenced.

In this way, x (t), x (t-1), x(
t-2>, x (t, -3) are referenced, and the moving average filter output y (t) is found by calculating the sum of these and dividing by 4.

Next, in order to find out how y(t+1>), use X(t+1)
is input and needs to be stored at address '10' (h) in memory.Then, base pointer increment and index counter clear commands are input via control input terminals 7, s, and 9.10, and control v4F4 is input. An up signal for the base counter 11\- and a clear signal for the index counter 2 are generated, and the content of the base counter 1 is advanced one step by the rising edge of the clock applied to the clock input terminal 5, and becomes "1o" ( At the same time as h), the index counter 2 is commanded to clear.

With this clear signal, the content of index counter 2 becomes °“00” (l), and adder 3 converts the output of base counter 1 “1o” (h) and the output of index counter 2 “oo” (h). Add the effective address “
10" (h). With this - instruction, the address that was pointing to the °'QC" (h) address where x(t-3) was stored until now is now the storage address of X(t+1). The address is changed to a certain "1o" (1) address.

After that, index counter 2 is decremented in the same way as for light, and x (t), x (t-1), x (t knee 2>
3 required to calculate y (t+1) by referring to
One value can be retrieved.

FIG. 5 is a detailed example of the control section 4 shown in FIG. 1. Reference number 1
00.101 is a 2-4 decoder (equivalent to Texas Instruments' 74LS139), reference number 102 is an inverter, reference number 103 is an OR gate with negative logic input (equivalent to Texas Instruments' 74LS10)
, reference number 104 is a NAND gate (equivalent to Texas Instruments' 74LSOO), reference number 7.8.
Reference numeral 9 is a control input terminal, reference numeral 10 is a mode input terminal, reference numerals 107, 108, and 109 are control signal terminals to the base counter 1, respectively.

Connected to DOWN, LOAD, reference numeral 11o.

111, 112, and 113 are control signal terminals for index counter 2, respectively UP, DOWN, and LOA.
D. Connected to CLEAR.

The control input terminal 9 is connected via an inverter 102 to an enable terminal of a 2-4 decoder 100 which generates a control signal to the base counter 1 of FIG.

2-4 generating a control signal to index counter 2;
It is directly connected to the enable terminal of decoder 101.

The control input terminal 9 is a bit input for selecting the update of the base counter 1 and the index counter 2, and when the control input terminal 9 is "0'', the index counter 1 is input, and when the control input terminal 9 is "1", the base counter 1 is input. Counter 2 is selected. Control input terminals 7 and 8 indicate mode control of the counter 2.
When the bit is “00”, the counter value is not updated (
NOP), when "01", load the data bus value to the counter (LOAD), when "10", load the counter by -1
Y1, Y2 . of the 2-4 decoder 100 generates a control signal to the base counter 1. Y3 output is passed through OR gate 103 with negative logic input, and then N
It is connected as a clear signal to the index counter 2 via an AND gate 104. NAND gate 1
The other input of 04 is connected to control terminal input 10, and when "1" is added to control input terminal 10 and base counter 1 is updated, the index counter is automatically cleared. It is done.

In the above embodiment, the base counter is incremented;
A virtual shift was achieved by decrementing the index counter.

By reversing the way memory addresses are assigned, it is possible to change the base counter to be decremented and the index counter to be incremented.9Also, it is possible to make the base pointer hold the address of the current input sample. By providing the address of the most past sample to be referenced, both the base counter and the index counter can be referenced by a counter that increments by +1. According to this method, the two counters can be implemented as unidirectional counters instead of up/down counters. Furthermore, even if the two pointers do not move in the same direction, by reversing the allocation of memory addresses, both the base counter and the index counter can be realized by counters that increment by -1. All these modifications are included in the present invention.

In the above embodiment, the number of control input signal lines from the outside is four, but if encoded control input signals are used and the control circuit has a built-in 7 lip-flop for mode conversion, the control of two counters can be performed. In addition to the 7 types of signals for mode conversion, there are 8 types in total, including the control signal for mode conversion, and only 3 signal lines are required.

〔Effect of the invention〕

In the present invention, by selectively using the control signal to the base counter as a clear signal to the index counter, there is no need to increase the instruction length.
Another advantage is that an address suitable for virtual shift, which is often used for filtering, etc., can be generated without inserting an extra instruction to update two pointers.

Brief explanation of screen images FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a diagram explaining virtual shift, FIG. 3 is a diagram explaining the principle,
FIG. 4 is a diagram showing the state of data storage in the memory, and FIG. 5 is a detailed diagram of a part of the embodiment.

DESCRIPTION OF SYMBOLS 1...Base counter, 2...Index counter, 3...Adder, 4...Control unit, 5...Tarlock input terminal, 6...Data bus input terminal, 7.8.9
...Control input terminal, 10...Mode input terminal.

Plan 1 52 diagrams J-t vf 亥J尼子l
Address Address Empire
Tian Chen-” Takuboshi l’1 PJ5 illustration input

Claims (1)

[Scope of Claims] A first counter, a second counter, clearing means for selectively clearing the contents of the second counter to zero by a counting control signal for the first counter, and the first counter. An address generation circuit comprising: an adder that adds the output of the counter and the output of the second counter.