JPS6211953A - Interface circuit - Google Patents

Abstract

PURPOSE:To attain the normal working of an interface circuit to a signal varying in both positive and negative directions and at the same to omit another power supply, by connecting two input terminals to an output terminal via diodes respectively and connecting a switch means to one of both diodes. CONSTITUTION:A switch SW is turned on when no signal of an H level is supplied to a terminal IN02 and the application level of a terminal IN01 is delivered to a terminal OUT01. Then the SW is turned on and off in response to the data applied to a data terminal when no signal of an H level is supplied to the IN01. When the signal applied from a data terminal 3 is kept at an L level, the SE is turned on and the L level of a data terminal 2 is applied to a computer 4 connected to the terminal OUT01. When the signal applied from the terminal 3 is kept under an H level, the SE is turned off and the H level applied from the terminal 3 is applied to the device 4 via a diode D02. When the signal applied from the IN01 is kept at an H level, the SE is turned off and the signal of an H level is applied to the OUT01 via a diode D01 to obtain an equal output waveform.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an interface circuit for computers and the like, and more particularly to an interface circuit for connecting a plurality of devices and other devices.

[Conventional technology]

The computer system has an input/output terminal for connecting the main unit and the terminal device. The main unit and the terminal device are connected through these terminals.

Data is sent and received. In addition to the shape of the connector to which this input/output terminal is connected, the electrical level output to the terminal and the control method differ depending on the device. In order to eliminate such differences in input/output terminals, most computer systems now have standardized interfaces. For example, a modem interface is a standard interface that allows data transmission between a computer system and between a terminal and a computer system via a modem, a public line, and a modem. Furthermore, personal computers and the like are also equipped with the modem interface described above.

For example, the R5232C standard has been adopted.

As mentioned above, a modem interface is provided in each computer system, and is a very effective interface for data transmission between different types of computers. However, for reasons described later, only one device can be connected to one interface circuit, so when connecting a plurality of terminal devices, a special circuit has been provided for connection. Figure 7.

FIG. 8 is a circuit diagram of a conventional circuit. In FIG. 7, diodes DI and D2 are connected to terminals INI and IN2 connected to each data output device to form a wired OR circuit and output to the data input device via the terminal OUT. With this configuration, when the signals applied to the terminals INI and IN2 are at positive voltage levels, a normal signal is output to OUT. For example, terminal TNI or terminal IN2
When +5V is applied to at least one of the terminals, the terminal OUT
Approximately +5■ is added to . (It actually decreases by the junction voltage of the diode.) In other words, if data is added from terminal TNI and no data is added from terminal rN2 (for example, ○N), the data added from terminal IN is output from terminal OUT. be done. In the opposite case, the data added from the terminal IN2 is output from the terminal OUT.

The input terminals of the devices connected to the terminals TNI and IN2 are commonly connected to the output terminals of the devices connected to the terminal OUT. Connecting one output to a plurality of inputs does not cause any problem because data is commonly added to the plurality of inputs. In contrast, adding multiple outputs to a single input results in data destruction. For example, when one output becomes +5 and the other output becomes OV, it is unclear which voltage level will be applied to one input, and as a result, data cannot be received. In order to prevent this, a circuit such as that shown in FIG. 7 is required. However, the circuit in FIG. 7 uses wired-OR logic, which means that the terminals INI,
This is a case where the voltage level of the signal applied from 1N2 changes in the positive direction, and a problem occurs when voltage levels in both positive and negative directions are applied. For example, when changing to +12V in the positive direction and -12V in the negative direction, both terminals INI and IN2
A negative voltage of -12V is applied to the diode D+.

When a reverse voltage is applied to D2, both are turned off and the terminal UT becomes open.

In the case of a modem interface, the signal voltage changes in both positive and negative directions, so the circuit shown in FIG. 7 described above cannot be used. Figure 8 shows a circuit that solves this problem. Terminal IN1.
The signal to be converted into +12V and -12V applied from IN2 is converted to TTL level by buffer Bufl and BaF2 and added to the OR gate OR, and furthermore, the TTL level signal is converted to +12V and -11 again by level conversion circuit Lve.
The signal level is converted to 2V and output to the terminal OUT. By this circuit, the signals applied from the terminals INI and IN2 are OR-added and output to the terminal OUT. This output naturally changes to +12V and -12V. The conventional circuit shown in Fig. 8 does not malfunction even with signals that change in both positive and negative directions, but in order to operate an OR gate, etc.
In addition, a +12V power supply is required to operate the level conversion circuit LVQ.

Furthermore, compared to the circuit shown in FIG. 7, the number of parts is large and the cost is high.

[Purpose of the invention]

In view of the above-mentioned drawbacks of the conventional art, it is an object of the present invention to provide an interface circuit that operates normally even with signals changing in one and both directions, does not require a special power supply, and is further cost-effective.

[Key points of the invention]

According to the present invention, the above object has at least a first and a second input terminal and one output terminal, and the first and second
The input terminal of . This is achieved by providing an interface circuit which is connected to the output terminal via a second diode and has a first switch means connected in parallel to the first diode.

[Embodiments of the invention]

The present invention will be described in detail using the following five drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention. 1
is an interface circuit according to an embodiment of the present invention. Data terminal 2 is connected to terminal lN0I, and data terminal 3 is connected to terminal lNOI.
2 are connected to each other. One terminal of the terminal lN0I is connected to one terminal of the terminal 0UT01 via a parallel circuit of a diode Do+ and a switch SW. Furthermore, one terminal of the terminal 0UTOI has a terminal lNO2.
One terminal of is connected via a diode DO2. The other terminals of terminals lN0L, lNO2, and 0UTOL are commonly grounded. The switch SW is turned on and off by a control circuit (not shown), and the condition for turning it on is when a negative level (low level) is input to both the inputs TNOI and 1N02, or when a negative signal is input to the terminal 1NO2. .

FIG. 2 is a timing chart of the embodiment of the present invention shown in FIG. 1. When a positive level (high level) is not input to the terminal TNO2 (data terminal 3 is not transmitting data, mode IN level> is output to m child 0UTOL.Also, high level is not input to terminal lN0I (data terminal 2 is not transmitting data/mode I NX 2
) Sometimes the switch SW turns on and off in response to data applied to the data terminal. When the signal applied from data terminal 3 is low level, switch SW is turned on, and terminal 0
The low level of the data terminal 2 is applied to the computer device 4 connected to the UTOI. When the signal applied from the data terminal 3 is high level, the switch SW is turned off, and the high level applied from the data terminal 3 is connected to the diode DQ.
2 to the computer device 4 (a load resistor R is connected to the input terminal of the computer device 4).

That is, when the signal applied from the data terminal 3 is low level, the low level of the data terminal 2 is applied to the computer device 4 via the switch SW, and the signals applied to each terminal are normally sent to the computer device 4.
It becomes like joining. In Fig. 2, the dotted line portion indicating on/off of the switch SW in mode INXI is the terminal l.
N0L.

This shows a case where the switch SW is controlled to be turned on only when both lNO2 become negative. When the signal applied from the terminal 1N0I is at high level, the switch SW is off unlike the above case, but since the high level is applied to the output terminal 0'UTO1 via the diode Do+, the output waveform is the same.

In the embodiment of the present invention shown in FIG. 1, OR addition is performed, so when signals are input from both terminals lN0I and lNO2 (mixed region INM I X), the result of the OR addition is output from terminal 0UTOI. Ru.

Some computer systems, especially those with modem interfaces (R3232C), cannot receive such signals, but this can be prevented by configuring the system so that no data is output from the data terminal at the same time.

FIG. 3 is a circuit configuration diagram of a second embodiment of the present invention. The switch of the first embodiment of the present invention shown in FIG.
It is composed of transistors Tr. Diode Dn+
Transistor Tr in parallel with.

The collector and emitter are connected, and the base is connected to the terminal lNO2 via a resistor. When a low level is applied to the terminal NO2, the transistor T is connected via the resistor R.
Since a low level is applied to the base of transistor T7
When a low level is applied to the terminal lN0I, -10= is turned on between the collector and emitter, and the low level is output to the terminal 0UTOI via the collector and emitter. on the other hand.

When a high level is applied to N0L, a reverse voltage is applied between the collector and emitter, so the transistor turns off and no current flows through the transistor, and a high level is output to terminal 0'UTM via the diode Do). . The on/off operation of the transistor T7 corresponds to the dotted line representing the on/off state of the switch SW in the timing chart described above. still.

When the transistor T7 is, for example, a MOS transistor, it corresponds to the solid line in the timing chart.

As mentioned above, in the embodiment of the present invention, signals that change in both positive and negative directions are logically summed without using a power supply, and the terminal 0UT is
It is output to OL.

FIG. 4 shows the first embodiment of the present invention. FIG. 7 is an applied configuration diagram of the second embodiment.

Interface circuits 1-1 to 1-5 according to embodiments of the present invention
One input is added to the input of the next stage, forming a total of five stages of series circuits. And the ink-face circuit 1-1
Connect the output of the data terminal 10 to the terminal lNO2-5 of the
The outputs of the data terminals 5 to 9 are connected to the other terminals lN0L-1 to lN0L-5 of the interface circuits 1-1 to 1-5 (7). The terminals 0UTO1 and -1 of the interface circuit 1-1 are commonly connected to the inputs of the data terminals 5 to 1o. For example, data output from the data terminal 1o sequentially passes through the interface circuits 1-5 to 1-1 and is applied to the inputs of the data terminals 5 to 10, respectively. With this configuration.

Data output from any data terminal is added to all data terminals. Each data terminal has an intelligent function such as a CPU, and by selecting and importing data to be added, the data is transmitted to the target data terminal. In other words, by using the interface circuit of the present invention, a simple LA
N (Local AreaNetwork) can be configured.

FIG. 5 shows the first embodiment of the present invention. FIG. 7 is another applied configuration diagram of the second embodiment. Similarly to FIG. 4, the interface circuits 1-6 to 1-9 of the embodiment of the present invention are connected in series, and the data outputs of the data terminals 1 to 5 are connected to the interface circuits 1-6 to 1-9.
It is connected to terminal lNO2-9 of. And terminals TNOI-6 to lN0 of interface circuits 1-6 to 1-9
The outputs of data terminals 11 to 14 are connected to L-9. As a result, data output from any data terminal is OR-added and output from terminals 0UTOL-6 of the interface circuit 1-6.

Join the shared computer 16. common computer 16
has an auxiliary storage device 17.1B, a printer 19.degree. magnetic tape device 20, and prints out, for example, required data using signals applied from one data terminal via each interface circuit. For example, when a command to read a program stored in the auxiliary storage device 17, 18 is added, it is read out by the shared computer 16, and the output of the shared computer 16 is commonly connected to the input of each data terminal 11 to 15. The program is output from the terminal that is connected to the program, and the data terminal that requested it receives the program program. Even if the data terminals are constituted by simple personal computers or the like, by using the embodiment of the present invention, the processing capabilities of the devices connected to the common computer 16 and the common computer 16 can be increased to the respective data terminals 11 to 15.
It can be used in Note that when one of the data terminals 11 to 15 is accessing the shared computer, no other device can access it. This application circuit can also be used to configure a system such as a LAN using a simple circuit as described above.

The above-mentioned 1. In the second embodiment, a switch means, for example, one transistor, is provided to turn on and off in response to two input levels. However, this first.
In the second embodiment.

It is configured such that a low level is output only when low level (negative voltage) is input to both inputs. Alternatively, one input is configured to be output by a switch when a low level is applied to the other input. Therefore, when one input is left unconnected, a problem arises in which a low level is not output. The resistor R' and diode Db indicated by the dotted line in Figure 3 solve this problem, and the terminal lNO
Even if 2 is not connected, when a low level is applied from the terminal lN0I, a negative voltage is applied to the base through the resistor Ri) and the diode Db, turning on the transistor T, and it operates so that a low level is applied to the output. .

FIG. 6 shows a third embodiment of the present invention in which the circuit shown in FIG. 3 (including the black line resistor Rb and diode D) is provided at both terminals lN0L and lNO2, and operates even if one of them is unconnected. FIG. 2 is a circuit configuration diagram of an example.

First, terminal lNl1. A case will be explained in which a data terminal or the like is also connected to the terminal lNl2. Terminal lN11, terminal I
At least one of NI 2 has a high level, e.g. 12V.
When added, diode DDI and diode D[1
When a high level is applied to the output 0UT12 via resistor R13, a low level applied to the terminal INI1 is applied to the base of transistors T and 2, and also to the resistor R14.
The low level applied to the terminal lNl2 via
The low levels applied to terminals INI and INI2 are output to terminal OUT12 via the collector-emitters of transistors T, I, T, and T2 (7), respectively, and the low levels applied to terminals INI and INI2 are outputted to terminal OUT12 through the collector-emitters of transistors T, I, T, and 2 (7), respectively. Second
The operation is similar to that of the embodiment.

Next, a case where a data terminal is connected only to terminal INI 1 will be explained. When a high level is applied to the terminal INI1, a high level is outputted to the terminal 0UT12 via the diode Da+. When a low level is applied to the terminal INI1, a low level is applied to the transistors T, -+ through the resistor R++ and the diode D, turning on the transistors T and l, in the same way as shown in FIG. As a result, the low level applied to the terminal INII is transferred to the transistor T.
, -+ are outputted to the terminal 0UT12 via the collector-emitter. Contrary to the above case, even when a data terminal is connected only to the terminal INI 2, the same operation as above is performed. That is, when a high level is input to the terminal lNl2, the diode
A high level is output to the terminal 0UT12 via the terminal D[12. and.

When a low level is input, a diode Db is connected to the resistor R.
A low level is applied to the transistor T,2 through z,
Transistors T and 2 were turned on. This allows the terminal lN
The low level applied to l2 is output to the terminal 0UT12 via the collector-emitter of the transistor Tr2.

Therefore, even if one of the terminals IN11.12 is not connected to a data terminal, the level of the connected data terminal is normally output to the terminal 0UT12. In addition, the resistance R11゜R
Diodes D, , connected in series to 12.

D and U prevent current from flowing through the resistors R14 and R13 when a high level is applied to one terminal and a low level is applied to the other terminal. For example, a data terminal is connected to both terminals INII and lNl2,
When a low level is applied to the terminal INII and a high level is applied to the terminal INII.

Diode DI,2 prevents current from flowing through resistor R12 and resistor R13.

All of the embodiments of the present invention described above are circuits that operate on positive logic signals. That is, this is a circuit that operates when a low level is always applied to the input when not transmitting data. The present invention is capable of similar operation not only for positive logic data but also for negative logic data. 9 and 10 show the fourth embodiment of the present invention which operates on negative logic data. It is a circuit block diagram of the 5th implementation side. In FIG. 9, the diodes Dn+ and Do2 of the second embodiment of the present invention in FIG. 2 are connected in opposite directions (D+ +, D+ 2), and the transistor T is replaced with an NPN transistor T,'. , all other configurations are the same as in FIG.

Further, FIG. 10 shows the diode DI>l+ Dbz+ Do 1. of the third embodiment of the present invention shown in FIG. Do
2 in the opposite direction (Db+ ', Dhz', D+
1゜DI2)L, and further transistor T y +
+ T r 2 to NPN) transistor T r l'
I T y'2', and all other configurations are the same as in FIG.

4 in Figures 9 and 10. In the fifth embodiment, a high level is added to both terminals INI1' and terminal INO2.
When a data signal (the level changes from high to low depending on the data) is added to the terminal TNO2', the data signal applied to the terminal TNO2' is output to the terminal 0UTOL. Conversely, a high level is added to the terminal TNO2', and the terminal lN
0I1. If a data signal is applied to ', the terminal lNO
2' is output to the data terminal OtJT. In this operation, transistors T, l and transistor T
, l, T, 2J are the second. It turns on and off in the same state as in the third embodiment. The fifth embodiment of the present invention shown in FIG. 10 differs from the third embodiment of the invention shown in FIG. 6 in that the data terminal is not connected to one terminal. Also works.

Connected to output input data from a data terminal.

The above description has been made using the embodiments of the present invention; however, the present invention has the following features:
In addition to outputting the output data of the data terminal to the 1+l1il output terminal, it is also possible to output print data from a plurality of computers to a printer or the like.

〔Effect of the invention〕

As described above, the present invention outputs data having both positive and negative voltage levels output from a plurality of data terminals to a single terminal using resistors, diodes, and even transistors. Since it is turned on and off depending on the level, the present invention operates normally even with signals that change in both positive and negative directions, does not require a separate power supply, and can provide an interface circuit at a lower cost.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of a first embodiment of the present invention. FIG. 2 is a time chart diagram of the first embodiment shown in FIG. FIG. 3 is a circuit configuration diagram of a second embodiment of the present invention. FIG. 4 and FIG. 5 are applied circuit configuration diagrams of an embodiment of the present invention. FIG. 6 is a circuit configuration diagram of a third embodiment of the present invention, which outputs a signal applied from the other terminal even if one terminal is not connected. 7 and 8 are circuit configuration diagrams of conventional interface circuits. 9 and 10 show the fourth embodiment of the present invention which operates with negative logic data. FIG. 3 is a circuit configuration diagram of a fifth embodiment. Dot, D[12, Do+', DO2'... Diode. Tf+ 'rr'l T, +, Tr2. Tyl'＋
Ty2'...transistor. SW...Switch. R, R++~R14...Resistance. Patent Applicant Casio Computer Co., Ltd. Figure 1

Claims (5)

[Claims] (1) It has at least first and second input terminals and one output terminal, the first and second input terminals are connected to the output terminal via the first and second diodes, and the first and second input terminals are connected to the output terminal via the first and second diodes. An interface circuit characterized in that a first switch means is connected in parallel to the first diode. (2) The interface circuit according to claim 1, wherein the first switch means has a switch control terminal, and the switch control terminal is connected to a second input terminal. (3) The first switch means includes a first transistor and a first resistor, and the switch control terminal is connected to the base of the first transistor via the first resistor. An interface circuit according to claim 2. (4) A second switch means is connected in parallel to the second diode, and a switch control terminal of the second switch means is connected to the first input terminal. The interface circuit according to item 2. (5) The first and second switch means are composed of second and third transistors, and second, third, fourth, and fifth resistors, and the second and third resistors are the second and third transistors. , connected to the collector and base of a third transistor, and the switch control terminals of the first and second switch means are connected to the bases of the second and third transistors via the fourth and fifth resistors. The interface circuit according to claim 4, characterized in that: