JPS6211945A - Debug system - Google Patents

Abstract

PURPOSE:To reduce the load of a host machine by providing a controller containing macroorder converting function which interpets a communication order and develops it to plural orders between a debug device and a device to be debugged. CONSTITUTION:An executing order for memory reading, for example, which is produced on a host machine 2 is delivered to an interface executing software 40 from an interface executing software 20 via a standard interface 3. The software 40 develops the received order into plural orders toward a target machine 6 and sends an order to set the addresses to be read into a console 60 on the machine 6. Then the software 40 sends an order to set an order to write the addresses set on the console 61 and finally sends an order to a console 62 to read out the information given from the written address. When the communication is through between a personal computer 4 and the machine 6, the software 40 sends the results of its execution to the software 20 via the interface 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a debug system that issues various communication orders from a debug device to a debug target device to control the debug target device.

[Conventional technology]

Year by year, the number of steps involved in debugging large-scale programs with various service functions on a debug target device is increasing. Therefore, work to support debugging of these programs is rapidly required.

Conventionally, this type of work has been performed by remote control by sending a communication order directly from the debug device to the device to be debugged via a special line between the debug device and the device to be debugged.

[Problem that the invention seeks to solve]

The conventional support work described above has the disadvantage that the communication protocol between the debug device and the device to be debugged is complicated, resulting in a heavy processing burden on the debug device side, and that it cannot provide sufficient support functions. If the debug device is a device that supports multi-fs=-za or multi-tanuta, the CPU is required to perform the above support functions.
The disadvantage is that it places a heavy burden on the user and interferes with other tasks.

[Means for solving problems]

A debugging system of the present invention includes a debugging device, a debugging device that issues a communication order to the debugged device to control the debugged device, and a debugging device that is located between the debugging device and the debugged device and receives communication orders from the debugged device. It has a control device that has a macro ordering function that interprets and develops multiple orders for debugged devices, and interfaces between the control device and the debugging device and between the control device and the debugged device, both of which are standard interfaces.

In this way, a communication control device is placed between the debug device and the device to be debugged, and this communication control device expands the l-order sent from the debug device into multiple orders for the device to be debugged, and processes the multiple orders. 1! While the communication protocol is not completed, communication remains between the communication control device and the debugged device, and once the communication protocol is completely completed, a response is returned to the debugging device. This ability reduces the burden on the host machine.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the debug system of the present invention.

This debug system includes a host machine 2 which is a general debug device that controls a device to be debugged, a target machine 6 which is a device to be debugged, a standard interface 8 connected to the host machine 2, and a standard interface 8 connected to the target machine 6. A personal computer 4, which is a control device that is interposed between the standard interface 5, the standard interface 8, and the r standard interface 5 and communicates directly with the target machine 6, and a disk file that is an external storage device of the host machine 2. Consists of l.

The host machine 2 is equipped with a disk file 1 and software 20 for interfacing with the standard interface 8, and the personal computer 4 is equipped with software 4 for interfacing with the standard interface 5.
0. The standard interface 8.5 was developed by CCITT (International Telegraph Consultative Committee) and EIA.
(Electronic Industries Association) standards, JIS (Japanese Industrial Standards)
It is a general-purpose standard interface that satisfies the following.

Next, the operation of this embodiment will be explained.

For example, an execution order for reading memory created on the host machine 2 is executed by the interface execution software 20.
The order is transferred to the interface execution software 40 via the standard interface 8, and the interface execution software 4 expands the order into multiple orders for the target machine 6, and the standard interface b
An order to set the address to be read is sent to the console Go on the target machine 6 via the console Go.
An order is sent to write the address set to 1, and an order is sent to the operation console 68 to continue writing information from the last written address. Like this K.

The interface execution software 4o expands the order from the interface execution software 20 into a plurality of orders, and obtains information about the target machine 6. After the communication between the personal computer 4 and the target machine 6 is completed, the interface execution software 40 transfers the execution results to the interface execution software 20 via the standard interface 8.
Send to. That is, the host machine 2 only needs to exchange very simple orders with the target machine 6, and the complicated procedures can be left to the personal computer, thereby reducing the sudden load on the host machine.

〔Effect of the invention〕

As explained above, the present invention uses a control device between a debug device and a device to be debugged, which has a macro ordering function that interprets communication orders from the debug device and expands them into multiple orders for the device to be debugged. By getting
This has the effect of reducing the load on the host machine and allowing other tasks on the debugging device to be executed smoothly.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the debug system of the present invention. 1...Disk file. 2...Host machine that is a debugging device. ]8 -6-8.5
...Standard interface. 4...Personal computer that is a control device. 6...Target machine. go, 40...Software for executing the interface. 60, 61.62 . . . Operation console of target machine 6, which is a device to be debugged.

Claims (1)

[Claims] A device to be debugged, a debug device that issues communication orders to the device to be debugged and controls the device to be debugged, and a device to be debugged that is located between the debug device and the device to be debugged and that interprets the communication orders from the debug device. A debugging system that has a control device that has a macro ordering function that expands to multiple orders for the target, and an interface between the control device and the debug device and between the control device and the device to be debugged, both of which are standard interfaces.