JPS62118559A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPS62118559A
JPS62118559A JP25886785A JP25886785A JPS62118559A JP S62118559 A JPS62118559 A JP S62118559A JP 25886785 A JP25886785 A JP 25886785A JP 25886785 A JP25886785 A JP 25886785A JP S62118559 A JPS62118559 A JP S62118559A
Authority
JP
Japan
Prior art keywords
film
silicon
silicon nitride
ta2o5
nitride film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25886785A
Other languages
Japanese (ja)
Inventor
Masanobu Yoshiie
善家 昌伸
Toshiyuki Shimizu
俊行 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP25886785A priority Critical patent/JPS62118559A/en
Publication of JPS62118559A publication Critical patent/JPS62118559A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To prevent silicide reaction between a metal oxide film such as a Ta2O5 film used in a capacitor part and a silicon substrate, to prevent reaction between the metal oxide such as Ta2O5 film and a polycrystalline silicon electrode located on the metal oxide film such as the Ta2O5 film, to reduce leaking currents and to prevent reduction in capacitance due to heat treatment, by providing a silicon nitride film. CONSTITUTION:A silicon nitride film 102 formed on the surface of a silicon substrate 101 is used to prevent silicide reaction between a Ta2O5 film and the silicon substrate when the Ta2O5 film is formed in the succeeding process. The diffusion coefficient of oxygen in the silicon substrate 101 is not oxidized through said Ta2O5, and the capacitance is not reduced. A silicon nitride film 104, which is formed on high dielectric-constant material, is formed by, e.g., a pressure reduced CVD method. Then, the silicon nitride film is thermally oxidized and a thin silicon oxide film 105 is formed. The best advantage of this oxidation is the fact that the basis film is grown by the oxidation of the surface of the silicon substrate 101 through pinholes in the Ta2O5 film 103 and the silicon nitride film 102.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特にダイナミックRAM等
において用いる情報蓄積容量部の構造に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of an information storage capacitor used in a dynamic RAM or the like.

〔従来の技術〕[Conventional technology]

半導体基板、特にシリコン半導体基板上に形成される集
積回路は高集積化、大容量化の一途をたどり、メモリー
素子の様な集積回路では1Mビット又はそれ以上へと集
積度が増大してきている。
Integrated circuits formed on semiconductor substrates, particularly silicon semiconductor substrates, are becoming increasingly highly integrated and have a large capacity, and the degree of integration of integrated circuits such as memory devices is increasing to 1 Mbit or more.

現在ダイナミックRAM(以後DRAMと記す)の様な
ICメモリーに於いては情報蓄積部(以下セルと記す)
を1個のトランジスターと1 個の情報蓄積容量部で構
成するのが最も小型化に適していると考えられる。この
方式での情報蓄積方式では半導体チップの大部分を前記
セルの情報蓄積容量部面積が占める。この種の装置は歩
留りとコストの点からチップサイズは極力小さくする必
要がある。従ってこの方式によるDR,AMの大容量化
は情報蓄積容量部面積の縮少が最も有効々手段となる。
Currently, in IC memories such as dynamic RAM (hereinafter referred to as DRAM), information storage units (hereinafter referred to as cells)
It is considered most suitable for miniaturization to consist of one transistor and one information storage capacitor. In this information storage method, the area of the information storage capacitor portion of the cell occupies most of the semiconductor chip. In this type of device, the chip size must be made as small as possible from the viewpoint of yield and cost. Therefore, the most effective means for increasing the capacity of DR and AM using this method is to reduce the area of the information storage capacity section.

しかし、この情報蓄積容量はα線によるンフトエラー等
によって引き起こされる誤動作に対する信頼性を確保す
るため50fF以上の容量が必要とされ、微細化により
1素子当りの面積が小さくなるからといって容量をあま
り小さくすることは許されない。従っ−C直I當をま情
報諷撰容編部面檀の縮少に伴い、誘電体膜の薄膜化に1
つ一〇′#i稍答足を確保する方法がとられる。しかし
、例えば従来用いられている比肋電率:3.9の7リコ
ン酸化膜をメガビット級D It A Mに適用し/こ
場合、シリコン酸化膜の膜厚Vi1oo八以下とへり、
このような薄膜の絶縁耐圧は電源電用5■に酬えられず
、使用は不可能であると予測される。この様な背景から
酸化膜厚は厚い址せ容鈑部σ11)*を実効的に広く確
保する手段として基板表面に溝を堀り溝側壁を容量部と
する構造が提案されている。しかしこの構造を用いたと
しても例えば4〜16メガビツト級DRAMでは溝の深
さは1. Q 7zmにもなり、後工程の1JL極形成
が困細になる等の問題が残されている。このため同一′
亀袷Ffti檀でも蓄槓芥景を大きくするために、絶縁
体と1〜で高誘電率材料を用いることが検討されており
、これを用いれば溝容量の溝深さも浅くすることが出来
るため、装置を製造するプロセスが容易となり、又いっ
そうの微細素子形成が可能となることが期待される。
However, this information storage capacity requires a capacity of 50 fF or more to ensure reliability against malfunctions caused by errors caused by alpha rays. It is not allowed to make it smaller. Therefore, due to the reduction in the size of the information collection section, the dielectric film has become thinner.
A method is taken to ensure that the answer is 10′#i. However, for example, if a conventional silicon oxide film with a specific electrical charge ratio of 3.9 is applied to a megabit class D It AM, the film thickness of the silicon oxide film is less than Vi1oo8,
The dielectric strength of such a thin film cannot meet the requirements for power supply (5), and it is predicted that it will be impossible to use it. Against this background, a structure has been proposed in which a groove is dug in the substrate surface and the sidewalls of the groove are used as a capacitive part as a means of effectively ensuring a large die capacity plate part σ11)* with a thick oxide film. However, even if this structure is used, for example, in a 4 to 16 megabit class DRAM, the depth of the groove is 1. Q 7zm, and there remain problems such as difficulty in forming a 1JL pole in the subsequent process. Therefore, the same
In order to increase the storage capacity of Kamibake Ffti Dan, the use of a high dielectric constant material for the insulator and 1~ is being considered, and if this is used, the groove depth of the groove capacitance can also be made shallow. It is expected that the process for manufacturing the device will become easier and that it will become possible to form even finer elements.

かかる高誘電率材料として最近特にTa205が取す」
二けられ、情報蓄積容量部への適用が試みられているが
、リーク電流が多く壕だ実用に供する特性が得られてい
ないのが現状である。
Recently, Ta205 has been particularly used as such a high dielectric constant material.
Attempts have been made to apply this to information storage capacitors, but the current situation is that the leakage current is large and the characteristics for practical use have not been achieved.

し発明が解決しようとする問題点〕 従来、高訪電率材料、例えばTa2 o5を用いた蓄積
容量部のリーク電流の大きい原因は情報蓄積容量部(以
下容量部と略す)の絶縁膜として用いたTa205膜が
、Si基板とシリサイド反応を起こしやすいこと、また
基板との対向電極として形成する多結晶シリコン電極と
反応を起こしやすいことのため、絶縁性が著しく低下す
るためと推定される。すなわち、Tag 05膜が熱処
理工程を経ることにより多結晶シリコン電極やSi基板
と固相反応を起こしたり、あるいはTa2o5膜が多結
晶化するなどにより、絶縁性が悪くなるものと発明者は
推定している。また、Ta205膜は、Ta205膜形
成後の熱酸化処理工程中に、Ta205膜中を酸素が容
易に拡散するためシリコン基板の表面が酸化され、容量
部の容量値が減少するという欠点もある。
[Problems to be Solved by the Invention] Conventionally, the cause of large leakage current in a storage capacitor using a material with a high current visiting rate, for example, Ta2O5, is that the material used as the insulating film of the information storage capacitor (hereinafter abbreviated as capacitor) This is presumed to be due to the fact that the Ta205 film that was used is likely to cause a silicide reaction with the Si substrate, and also with the polycrystalline silicon electrode formed as a counter electrode with the substrate, resulting in a significant decrease in insulation properties. In other words, the inventor presumes that the Tag 05 film undergoes a heat treatment process, causing a solid phase reaction with the polycrystalline silicon electrode or the Si substrate, or that the Ta2O5 film becomes polycrystalline, resulting in poor insulation properties. ing. Furthermore, the Ta205 film has the disadvantage that during the thermal oxidation process after the Ta205 film is formed, oxygen easily diffuses into the Ta205 film, so that the surface of the silicon substrate is oxidized and the capacitance value of the capacitive part is reduced.

本発明の目的は、’BitA部に用いるTa205膜等
の金属酸化膜とシリコン基板とのシリサイド反応を防ぎ
、’、[’a205膜等の金jg酸化膜とTa!O,膜
等の金属酸化膜上部に位置する多結晶シリコン電極との
反応を防き、かつ漏れ電流を低減し、さらにTa20B
膜等の金属酸化膜形成後の熱処理による容量の減少を防
いだ情報蓄積容量を具備した半導体装置を提供すること
にある。
The purpose of the present invention is to 'prevent the silicide reaction between the metal oxide film such as the Ta205 film used in the BitA part and the silicon substrate,' and ['to prevent the silicide reaction between the metal oxide film such as the Ta205 film and the Ta! It prevents reaction with the polycrystalline silicon electrode located on the top of the metal oxide film such as O, film, etc., reduces leakage current, and further improves the Ta20B
An object of the present invention is to provide a semiconductor device having an information storage capacity that prevents a decrease in capacity due to heat treatment after forming a metal oxide film such as a film.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体装置は、半導体基板や絶縁体基板上に設
けられた電極と、該電極上にシリコン窒化膜と、Ta1
05 、 ’1”iol 、 Nb206 、 HaT
i03のうちのいずれかの金属酸化膜と、シリコン窒化
膜と、シリコン酸化膜とを順次檀階形成した絶縁層と、
該絶縁層上に設けられた電極とから構成される容量を備
えて構成ざiする。
The semiconductor device of the present invention includes an electrode provided on a semiconductor substrate or an insulator substrate, a silicon nitride film on the electrode, and a Ta1
05, '1''iol, Nb206, HaT
an insulating layer in which a metal oxide film of i03, a silicon nitride film, and a silicon oxide film are sequentially formed;
and an electrode provided on the insulating layer.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
。第1図は本発明の一実施例の縦断面図である。
Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a longitudinal sectional view of an embodiment of the present invention.

第1図において、101はこの上に装置を形成するシリ
コン基板である。シリコン基板はP型−n型いずれの導
電性を有する基板であっても良い。
In FIG. 1, 101 is a silicon substrate on which a device is formed. The silicon substrate may be a substrate having either P-type or n-type conductivity.

102はシリコン基板101表面に形成したシリコン窒
化膜である。シリコン窒化膜は、Si基板を窒化する直
接熱窒化法、プラズマ直接熱窒化法、もしくは化学気相
成長法(CVD法)等により形成でき、30〜50A程
度形成するのが望ましい。
102 is a silicon nitride film formed on the surface of the silicon substrate 101. The silicon nitride film can be formed by a direct thermal nitriding method for nitriding a Si substrate, a plasma direct thermal nitriding method, a chemical vapor deposition method (CVD method), etc., and is preferably formed to a thickness of about 30 to 50 A.

このシリコン窒化膜は後の工程でTa20B膜を形成す
る際に当該Ta205膜とシリコン基板とのシリサイド
反応を防止するためのものである。さらに、このシリコ
ン窒化膜は、膜中の酸素の拡散係数が小さいため、Ta
205膜形成後の熱酸化処理工程中に、当該Ta205
膜を通してシリコン基板1010表面が酸化され、容量
が減少するのを防ぐ効果も持っている。103は高誘電
拐料であるTa205である。Ta205は金属Taを
スパッタリング法等の手法で形成した後熱酸化するか若
しくは高周波スパッタ法あるいは化学気相成生法(CV
D法)により直接1’az05を形成する等の方法によ
り形成できる。高誘電率拐料としてはチタy(Ti)、
=捌プ(N)))やジルコニウム(Z r )等の他の
酸化物廿たl(a ’l r 03等の複合酸化物を用
いても選択は自由であり、本発明の目的を達成すること
ができる。l 04 rJ二高l!8電率拐料上に形成
したシリコン窒化膜である、6シリコン窒化膜は例えば
減圧CVD法により形成する。次にこのシリコン窒化膜
を熱酸化I−薄いシリコン酸化膜105を形成する。シ
リコン窒化膜(,1,膜中の酸素の拡散係数が小さいた
め、はんのわずか酸化膜が形成されるのみである。しか
12、この酸化の銀天のj七所はシリコン窒化膜にピン
ホールが存在する場合、熱酸化によってTa205膜1
03及びシリコン窒化膜102絶縁膜のピンホールを埋
める点にある。このため極めて優れた耐圧特性を有する
容量が実現できる。
This silicon nitride film is for preventing a silicide reaction between the Ta205 film and the silicon substrate when forming the Ta20B film in a later step. Furthermore, this silicon nitride film has a small diffusion coefficient of oxygen in the film, so Ta
During the thermal oxidation treatment step after forming the Ta205 film, the Ta205
It also has the effect of preventing the surface of the silicon substrate 1010 from being oxidized through the film and reducing the capacitance. 103 is Ta205, which is a high dielectric material. Ta205 is formed by thermally oxidizing metal Ta by sputtering or other methods, or by high-frequency sputtering or chemical vapor deposition (CV).
It can be formed by a method such as directly forming 1'az05 by method D). Titanium (Ti) is used as a high dielectric constant material.
Other oxides such as zirconium (Zr) and complex oxides such as a'lr03 can be freely selected, and the purpose of the present invention can be achieved. The 6 silicon nitride film, which is a silicon nitride film formed on the 8 electric conductivity material, is formed by, for example, a low pressure CVD method.Next, this silicon nitride film is thermally oxidized. - Form a thin silicon oxide film 105.Silicon nitride film (1) Because the diffusion coefficient of oxygen in the film is small, only a small oxide film of the solder is formed. If there are pinholes in the silicon nitride film, the Ta205 film 1 is removed by thermal oxidation.
03 and silicon nitride film 102 to fill pinholes in the insulating film. Therefore, a capacitor having extremely excellent breakdown voltage characteristics can be realized.

またシリコン窒化膜自体はほとんど酸化されないため容
量は減少しない特徴も有している。106はシリコン基
板の対極となる多結晶シリコン電極である、1この電極
は多結晶シリコン層およびシリ本発明を用いて形成した
容量は、電極に7vの電圧を印力nした時の電流密度は
IOA/cm”になり、Ta205単層膜に比較して、
3桁以上リーク電流を低減でき、かつ’1.’a205
膜形成後の熱処理を経ても容量を形成している各層の膜
厚から推定される容量値とほぼ同じ容量値が得られてい
る。
Furthermore, since the silicon nitride film itself is hardly oxidized, the capacitance does not decrease. 106 is a polycrystalline silicon electrode that serves as a counter electrode to the silicon substrate.1 This electrode is made of a polycrystalline silicon layer and silicon.The capacitor formed using the present invention has a current density when a voltage of 7V is applied to the electrode. IOA/cm” compared to Ta205 single layer film.
Leakage current can be reduced by more than 3 orders of magnitude, and '1. 'a205
Even after heat treatment after film formation, a capacitance value that is almost the same as the capacitance value estimated from the film thickness of each layer forming the capacitor is obtained.

第2図は本発明の他の実施例の縦断面図で、容量形成法
を溝構造に適用したものである。膜形成法は第1図で説
明した方法とtlは同様であるが、溝内壁に均一な厚さ
の膜を形成する必要があることから、Ta205膜10
3はCVD法Kjり形成するのが好ましい。また、10
6の電極は、多結晶シリコンをCVD法で形成すれば、
溝内部に極めて容易に電極を埋めこむことができる。本
実施例によれば容量値を大きくすることが出来ると共に
第1図の実施例と同様リーク電流を大幅に低減した設計
値通りの容量が得ら肛る。
FIG. 2 is a longitudinal sectional view of another embodiment of the present invention, in which the capacitance formation method is applied to the groove structure. The film forming method is the same as the method explained in FIG.
3 is preferably formed by CVD method. Also, 10
If electrode 6 is formed from polycrystalline silicon by CVD method,
Electrodes can be embedded extremely easily inside the groove. According to this embodiment, it is possible to increase the capacitance value, and as with the embodiment shown in FIG. 1, it is possible to obtain a capacitance in accordance with the designed value with significantly reduced leakage current.

なお、上記実施例では、Si基板上に容量を形成したが
、他の電極H別系4)k」−に形成1.’tも例等制約
はない。
In the above embodiment, the capacitor was formed on the Si substrate, but the capacitor was formed on the other electrode H (4) k''-. There are no restrictions such as examples.

また、上部′電極に多結晶シリコンを用いたが、これに
限定されるものでな(、A、l、W、Mo等の金属を用
いてもよい。
Further, although polycrystalline silicon is used for the upper electrode, the present invention is not limited to this; metals such as A, L, W, and Mo may also be used.

〔発明の効果〕〔Effect of the invention〕

以上説明した様に本発明は、高誘電材料であるTa2o
s膜等の金属酸化膜とシリコン基板との間にシリコン窒
化膜を設けることにより、Ta206膜等の金属酸化膜
とシリコン基板との反応に防止することができる。また
、Ta205膜等の金属酸化膜形成後の熱酸化処理によ
るシリコン基板表面の酸化も抑える効果もある。また’
l’a20s膜等の金属酸化膜と多結Jilシリコン電
極との間にシリコン窒化膜を設けることにより゛、Ta
205膜等の金属酸化膜と多結晶シリコン電極との反応
を防止できる効果もある。さらにシリコン窒化膜はNa
等の不純物に対する拡散抑制効果が大きいことから、9
一 本発明になる容量は電気的安定性にも優れている。
As explained above, the present invention utilizes Ta2O, which is a high dielectric material.
By providing a silicon nitride film between a metal oxide film such as an S film and a silicon substrate, it is possible to prevent a reaction between a metal oxide film such as a Ta206 film and a silicon substrate. It also has the effect of suppressing oxidation of the silicon substrate surface due to thermal oxidation treatment after forming a metal oxide film such as a Ta205 film. Also'
By providing a silicon nitride film between a metal oxide film such as a l'a20s film and a polycrystalline Jil silicon electrode,
It also has the effect of preventing reactions between metal oxide films such as the 205 film and polycrystalline silicon electrodes. Furthermore, the silicon nitride film contains Na
9 because it has a large diffusion suppressing effect on impurities such as
The capacitor according to the present invention also has excellent electrical stability.

以上のように本発明の構造を用いれは高誘電率材料の性
質をいかすことが可能になり、単位面積当たり大きい容
量を有し、かつリーク電流の小さい情報蓄積容量部を形
成することができる。
As described above, by using the structure of the present invention, it becomes possible to take advantage of the properties of high dielectric constant materials, and it is possible to form an information storage capacitor section that has a large capacitance per unit area and a small leakage current.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一笑施例の縦断面図、第2図は本発明
の他の実施例の縦断面図である。 101゛・・°°゛シリコンJ[,102・・・・・・
シリコン窒化膜、103・・・・・’]、’a205膜
、104・・・・・・シリコン窒化膜、105・・・・
・・シリコン酸化膜、106・・・・・・多結晶シリコ
ン電極。 $ l 図 矛2 図 手続補正書(自発) 1、事件の表示   昭和60年 %許  願第258
867号2、発明の名称    半導体装置 3、補正をする者 事件との関係       出 願 大東に〔都泄区芝
/i I−1133番1シ)(423)   日本電気
株式会社 代表台 関本忠弘 4、代理人 TiO8東京都港区i’21t、丁1137番8シ〕・
 住友三田ビル11本電気株式会社内 5、補正の対象 明細書の特許請求の範囲の欄および発明の詳細な説明の
欄 6、補正の内容 (1)明細書の特許raIIt求の範囲のn11載?別
紙のとおり訂正いたし1す〇 (2)明細書第2頁、16r、r[lのf尼1y r 
141 V’−よる]を「線等による」と訂iEいたし
オす。 (3)明細書第5頁、11行目乃至12行目の記載「半
導体基板や絶縁体基板上に設けらn、た′[1!極と該
電極上」を1半導体基板もしくは電極と、該半導体基板
上もしくは該電極」:」と訂正いたし1す。 (4)明細書第6頁、20行目の記載「底生法」を「成
長法」とyj正いたし1す。 別紙 訂正後の特許請求の範囲 「半導体基板もしくけ電極と、該半導体基板上もしくは
該″tfi極上にシリコン窒化膜と、Ta205 。 TiO2、Nb2O5、Ba’l’i03のうちいずれ
かの金属酸化膜と、シリコン窒化膜と、シリコン酸化膜
と全順次積層形成した絶縁層と、該絶縁層上に設けられ
た電極と全具備せる容量金偏えたこと全特徴とする半導
体装置。」
FIG. 1 is a longitudinal sectional view of one embodiment of the invention, and FIG. 2 is a longitudinal sectional view of another embodiment of the invention. 101゛...°°゛Silicon J[,102...
Silicon nitride film, 103...'], 'a205 film, 104... Silicon nitride film, 105...
...Silicon oxide film, 106...Polycrystalline silicon electrode. $ l Illustration 2 Illustration procedure amendment (voluntary) 1. Indication of incident 1985 Percentage request No. 258
867 No. 2, Title of invention: Semiconductor device 3, Relationship with the amended person's case Application: Daito [Shiba, Toshiro-ku/i I-1133-1-shi] (423) NEC Corporation Representative Tadahiro Sekimoto 4; Agent TiO8 1137-8, i'21t, Minato-ku, Tokyo]・
Sumitomo Sanda Building 11 Hondenki Co., Ltd. 5, Claims column and Detailed Description of the Invention column 6 of the specification to be amended, content of the amendment (1) n11 of the scope of patent raIIt sought in the specification ? I have made the correction as shown in the attached sheet. 1su〇(2) Specification page 2, 16r, r
141 V'-by] has been amended to ``by line, etc.''. (3) The description on page 5, lines 11 and 12 of the specification "n, ta'[1! pole and the electrode provided on the semiconductor substrate or insulator substrate" is defined as one semiconductor substrate or electrode. ``On the semiconductor substrate or the electrode'':''1. (4) The statement "benthic method" on page 6, line 20 of the specification has been corrected to "growth method." The appended paper's revised claims include: ``A semiconductor substrate or a structured electrode, a silicon nitride film on the semiconductor substrate or on the TFI layer, and Ta205. Completely equipped with an insulating layer formed by sequentially laminating a metal oxide film of TiO2, Nb2O5, Ba'l'i03, a silicon nitride film, and a silicon oxide film, and an electrode provided on the insulating layer. A semiconductor device that is characterized by its capacitance being gold-biased. ”

Claims (1)

【特許請求の範囲】[Claims] 半導体基板や絶縁体基板上に設けられた電極と、該電極
上にシリコン窒化膜と、Ta_2O_5、TiO_2、
Nb_2O_5、BaTiO_3のうちいずれかの金属
酸化膜と、シリコン窒化膜と、シリコン酸化膜とを順次
積層形成した絶縁層と、該絶縁層上に設けられた電極と
から構成される容量を備えたことを特徴とする半導体装
置。
An electrode provided on a semiconductor substrate or an insulator substrate, a silicon nitride film on the electrode, Ta_2O_5, TiO_2,
Equipped with a capacitor consisting of an insulating layer formed by sequentially laminating a metal oxide film of Nb_2O_5 or BaTiO_3, a silicon nitride film, and a silicon oxide film, and an electrode provided on the insulating layer. A semiconductor device characterized by:
JP25886785A 1985-11-18 1985-11-18 Semiconductor device Pending JPS62118559A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25886785A JPS62118559A (en) 1985-11-18 1985-11-18 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25886785A JPS62118559A (en) 1985-11-18 1985-11-18 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS62118559A true JPS62118559A (en) 1987-05-29

Family

ID=17326135

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25886785A Pending JPS62118559A (en) 1985-11-18 1985-11-18 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS62118559A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004008544A1 (en) * 2002-07-16 2004-01-22 Nec Corporation Semiconductor device, production method and production device thereof
JP2005537652A (en) * 2002-09-02 2005-12-08 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド Semiconductor device having field effect transistor and passive capacitor with reduced leakage current and improved capacitance per unit area

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS538088A (en) * 1976-07-12 1978-01-25 Hitachi Ltd Production of semiconductor device
JPS61160155A (en) * 1985-01-05 1986-07-19 Nec Corp Timer control system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS538088A (en) * 1976-07-12 1978-01-25 Hitachi Ltd Production of semiconductor device
JPS61160155A (en) * 1985-01-05 1986-07-19 Nec Corp Timer control system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004008544A1 (en) * 2002-07-16 2004-01-22 Nec Corporation Semiconductor device, production method and production device thereof
JP2005537652A (en) * 2002-09-02 2005-12-08 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド Semiconductor device having field effect transistor and passive capacitor with reduced leakage current and improved capacitance per unit area

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