KR100224656B1 - Capacitor manufacturing method of semiconductor memory device - Google Patents
Capacitor manufacturing method of semiconductor memory device Download PDFInfo
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- KR100224656B1 KR100224656B1 KR1019960003062A KR19960003062A KR100224656B1 KR 100224656 B1 KR100224656 B1 KR 100224656B1 KR 1019960003062 A KR1019960003062 A KR 1019960003062A KR 19960003062 A KR19960003062 A KR 19960003062A KR 100224656 B1 KR100224656 B1 KR 100224656B1
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- 239000003990 capacitor Substances 0.000 title claims abstract description 34
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 36
- 230000004888 barrier function Effects 0.000 claims abstract description 27
- 238000000137 annealing Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 7
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 7
- 239000001301 oxygen Substances 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 4
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 4
- 229910010413 TiO 2 Inorganic materials 0.000 claims description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 3
- 239000002131 composite material Substances 0.000 claims description 2
- GNTDGMZSJNCJKK-UHFFFAOYSA-N divanadium pentaoxide Chemical compound O=[V](=O)O[V](=O)=O GNTDGMZSJNCJKK-UHFFFAOYSA-N 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- URLJKFSTXLNXLG-UHFFFAOYSA-N niobium(5+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Nb+5].[Nb+5] URLJKFSTXLNXLG-UHFFFAOYSA-N 0.000 claims description 2
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 claims description 2
- 150000001875 compounds Chemical class 0.000 claims 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims 1
- 239000007789 gas Substances 0.000 claims 1
- 239000010936 titanium Substances 0.000 claims 1
- 229910052719 titanium Inorganic materials 0.000 claims 1
- 239000010410 layer Substances 0.000 description 24
- 239000011229 interlayer Substances 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 229910010282 TiON Inorganic materials 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 230000018109 developmental process Effects 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 230000002265 prevention Effects 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 2
- XHCLAFWTIXFWPH-UHFFFAOYSA-N [O-2].[O-2].[O-2].[O-2].[O-2].[V+5].[V+5] Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[V+5].[V+5] XHCLAFWTIXFWPH-UHFFFAOYSA-N 0.000 description 1
- OBOYOXRQUWVUFU-UHFFFAOYSA-N [O-2].[Ti+4].[Nb+5] Chemical compound [O-2].[Ti+4].[Nb+5] OBOYOXRQUWVUFU-UHFFFAOYSA-N 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000010955 niobium Substances 0.000 description 1
- 229910000484 niobium oxide Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910001935 vanadium oxide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
DRAM 소자의 커패시터의 제조방법에 대해 기재되어 있다. 이는 반도체기판 내에 형성된 트랜지스터의 소오스와 연결되는 하부전극을 형성하는 단계, 상기 하부전극 상에 유전체막을 형성하는 단계, 상기 유전체막 상에 베리어층을 형성하는 단계, 베리어층이 형성된 상기 결과물에 대한 어닐링(annealing) 공정을 실시하여 베리어 특성을 향상시키는 단계 및 어닐링공정이 진행된 결과물 전면에 상부전극을 형성하는 것을 특징으로 한다. 따라서, 누설전류 문제 및 유전율 감소문제를 개선할 수 있다.A method for manufacturing a capacitor of a DRAM device is described. This method includes forming a lower electrode connected to a source of a transistor formed in a semiconductor substrate, forming a dielectric film on the lower electrode, forming a barrier layer on the dielectric film, and annealing the resultant on which the barrier layer is formed. Implementing an annealing process to improve barrier characteristics and forming an upper electrode on the entire surface of the resultant annealing process. Therefore, the leakage current problem and the dielectric constant reduction problem can be improved.
Description
제1도는 종래 일 방법에 의해 제조된 커패시터의 일부를 개략적으로 도시한 단면도이다.1 is a cross-sectional view schematically showing a part of a capacitor manufactured by a conventional method.
제2도는 본 발명의 일 실시예에 의해 제조된 반도체 떼모리소자 제조방법을 설명하기 위해 도시한 단면도이다.2 is a cross-sectional view for explaining a method for manufacturing a semiconductor thermal element manufactured by an embodiment of the present invention.
본 발명은 반도체 메모리소자 및 그 제조방법에 관한 것으로, 특히 커패시터의 누설전류를 감소시키는 반도체 메모리소자의 커패시터 구조 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method for manufacturing the same, and more particularly, to a capacitor structure of a semiconductor memory device for reducing a leakage current of a capacitor and a method for manufacturing the same.
최근 반도체 제조기술의 발달과 메모리소자의 응용분야가 확장되어 감에 따라 대용량의 메모리소자 개발이 진척되고 있는데, 특히 단위 메모리셀을 한개의 커패시터와 한개의 트랜지스터로 구성한 DRAM(Dynamic Random Access Memory)은 고집적화에 유리하여 괄목할 만한 발전을 이루어 왔다.Recently, with the development of semiconductor manufacturing technology and the application field of memory devices, the development of large-capacity memory devices is progressing. In particular, DRAM (Dynamic Random Access Memory), which consists of one capacitor and one transistor, Significant developments have been made in favor of high integration.
이러한 반도체 메모리소자는 정보의 독출과 저장을 위해 큰 정전용량을 가져야 하는데, 기존의 커패시터 구조로서는 한정된 면적내에서 충분히 큰 셀 커패시턴스를 확보할 수 없다.Such a semiconductor memory device must have a large capacitance for reading and storing information, and a conventional capacitor structure cannot secure sufficiently large cell capacitance within a limited area.
따라서 작은 면적내에서 보다 큰 커패시턴스를 얻기 위한 방법의 연구가 요구되었는데, 이 방법은 보통 다음의 3가지로 나뉘어질 수 있다. 즉, 첫째는 유전체막의 두께 감소, 둘째는 커패시터의 유효면적 증가, 셋째는 유전상수가 큰 물질의 사용이 그것이다.Therefore, a study of a method for obtaining a larger capacitance in a small area was required. This method can be generally divided into three types. That is, the first is to decrease the thickness of the dielectric film, the second is to increase the effective area of the capacitor, and the third is to use a material having a large dielectric constant.
이중에서 세번째의 경우는, 반도체 메모리소자의 커패시터의 유전체막으로 사용하던 기존의 물질, 즉 산화막, ONO (Oxide/ Nitride/ Oxide) 또는 NO (Nitride/ Oxide)등은 물질자체의 유전율이 작으므로 (산화막의 경우 약 3.8이고, 질화막의 경우 약 7.8이다), 차세대 DRAM에 이를 적용할 때, 커패시터의 구조가 지나치게 복잡하게 되거나 두께가 얇게 되어 신뢰성에 문제가 생기게 된다. 따라서 이러한 문제점들을 해결하기 위하여, 현재 고유전물질이나 강유전물질을 사용하여 커패시터의 유전체막을 형성하는 방법이 연구되고 있다.In the third case, the existing material used as a dielectric film of a capacitor of a semiconductor memory device, that is, an oxide film, ONO (Oxide / Nitride / Oxide) or NO (Nitride / Oxide), has a low dielectric constant of the material itself ( The oxide film is about 3.8, and the nitride film is about 7.8). When applied to the next-generation DRAM, the capacitor structure becomes too complicated or too thin, resulting in reliability problems. Therefore, in order to solve these problems, a method of forming a dielectric film of a capacitor using a high dielectric material or a ferroelectric material is currently being studied.
고유전물질 중에서도 특히 Ta2O5(오산화탄탈륨)의 경우는 우수한 유전율(약 20∼25) 때문에 더 많은 연구가 이루어지고 있다. 그러나, 상기 Ta2O5는 에너지 밴드 갭(energy band gap)이 4eV 로서, 산화막(SiO2)의 11eV에 비해 훨씬 작은 단점이 있다. 에너진 밴드 갭이 작을수록 누설전류가 커지게 되므로 소자의 신뢰성이 저하되는 문제점이 있다.Among the high dielectric materials, especially in the case of Ta 2 O 5 (tantalum pentoxide), more research is being conducted because of the excellent dielectric constant (about 20-25). However, Ta 2 O 5 has an energy band gap of 4 eV, which is much smaller than that of 11 eV of the oxide film (SiO 2 ). The smaller the energized bandgap, the larger the leakage current, and thus, the reliability of the device is deteriorated.
또한, 상부전극으로 다결정실리콘만을 사용하게 되면, Ta2O5의 산소와 다결정실리콘이 반응하여 다결정실리콘이 산화되고, 이에따라 형성된 산화막은 전체 유전체막의 유전율을 감소시키는 요인이 된다.In addition, when only polycrystalline silicon is used as the upper electrode, oxygen of Ta 2 O 5 and polycrystalline silicon react to oxidize the polycrystalline silicon, and thus the oxide film formed is a factor for reducing the dielectric constant of the entire dielectric film.
상기와 같은 문제점들을 극복하기 위한 방법으로, 상부전극을 TiN (질화티타늄)과 다결정실리콘의 적층구조로 형성하는 방법이 제안되어 있다. Ta2O5의 산화에 대한 베리어층으로 TiN 막을 형성함으로써, 누설전류를 감소시키고, 산소와 다결정실리콘과의 반응을 방지한다.As a method for overcoming the above problems, a method of forming the upper electrode in a stacked structure of TiN (titanium nitride) and polycrystalline silicon has been proposed. By forming a TiN film as a barrier layer for oxidation of Ta 2 O 5 , leakage current is reduced, and the reaction between oxygen and polycrystalline silicon is prevented.
제1도는 종래 일 방법에 의해 제조된 커패시터의 일부를 개략적으로 도시한 단면도로서, 참조부호 10은 반도체 기판을, 12는 하부구조물을 절연시킬 목적으로 형성된 층간절연층을, 14는 커패시터의 하부전극을, 16은 커패시터의 유전체막을, 18은 베리어층으로 사용될 TiN 막을 각각 나타낸다.1 is a cross-sectional view schematically showing a part of a capacitor manufactured by a conventional method, reference numeral 10 denotes an interlayer insulating layer formed to insulate a semiconductor substrate, 12 denotes an underlying structure, and 14 denotes a lower electrode of the capacitor. 16 denotes a dielectric film of a capacitor and 18 denotes a TiN film to be used as a barrier layer.
상기한 구조를 갖는 커패시터는, 반도체 기판(10)에, 통상의 공정으로 트랜지스터와 비트라인까지 형성한 후, 실리콘산화물을 전면에 침적하여 층간절연층(12)을 형성한다. 이어서 트랜지스터의 소오스와 커패시터의 하부전극을 연결시키기 위한 접촉창을 형성하고, 결과물 전면에, 다결정실리콘을 증착한 다음 패터닝하여 커패시터의 하부전극(14)을 형성하고, 그 결과물 전면에 Ta2O5와 같은 고유전물질을 도포하여 유전체막(16)을 형성한다. 이 후, 결과물 전면에 TiN과 같은 베리어층(18)을 형성한 후, 다시 다결정실리콘을 증착하여 상부전극(도시되지 않음)을 형성한다.In the capacitor having the above structure, the transistor and the bit line are formed on the semiconductor substrate 10 in a conventional process, and then silicon oxide is deposited on the entire surface to form the interlayer insulating layer 12. Then, a contact window for connecting the source of the transistor and the lower electrode of the capacitor is formed, polysilicon is deposited on the entire surface of the resultant, and then patterned to form the lower electrode 14 of the capacitor, and then Ta 2 O 5 on the front of the resultant. A dielectric film 16 is formed by applying a high dielectric material, such as. Thereafter, a barrier layer 18 such as TiN is formed on the entire surface of the resultant, and then polycrystalline silicon is further deposited to form an upper electrode (not shown).
이때, 상기 TiN 막(18)은 통상의 스퍼터 방법을 이용하여 증착하여 베리어층으로 이용하여 왔다. 그러나, 이와같이 스퍼터 방법으로 증착된 TiN막(16)은 단차도포성 (step coverage)이 다결정실리콘에 비해 현저히 떨어진다. 따라서, 하부전극의 형태가 예컨대, 제1도에서와 같은 원통형 전극인 경우, 증착된 TiN 막의 두께가 불균일하게 되고, 국부적으로 막의 두께가 매우 얇은 부분(A 참조)이 존재하게 된다. 즉, A 부분에서는 Ta2O5유전체막과 다결정실리콘의 상부전극 사이에 베리어층이 거의 형성되어 있지 않다. 따라서, 이 부분은 누설전류 발생 지점이 되어 Ta2O5유전체막의 열화를 초래하고, Ta2O5막의 산소와 상부전극의 다결정실리콘의 반응을 방지하는 베리어층으로서의 역할을 하지 못하여 커패시터의 전체 유전율을 감소시키는 결과를 초래한다.At this time, the TiN film 18 was deposited using a conventional sputtering method and used as a barrier layer. However, the TiN film 16 deposited by the sputtering method is significantly inferior in step coverage to polysilicon. Thus, when the shape of the lower electrode is, for example, a cylindrical electrode as in FIG. 1, the thickness of the deposited TiN film becomes nonuniform, and there is a part where the film thickness is very thin (see A). That is, in the portion A, a barrier layer is hardly formed between the Ta 2 O 5 dielectric film and the upper electrode of the polysilicon. Therefore, this part becomes a leakage current generation point, which causes deterioration of the Ta 2 O 5 dielectric film and does not serve as a barrier layer that prevents the reaction of oxygen of the Ta 2 O 5 film and polycrystalline silicon of the upper electrode, thereby reducing the overall dielectric constant of the capacitor. Results in a reduction.
따라서, 본 발명의 목적은 고유전물질을 사용하여 유전체막을 형성하는 경우, 커패시터의 누설전류를 저하시키고 운전율의 감소를 억제할 수 있는 반도체 메모리소자의 커패시터 제조방법을 제공하는데 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a capacitor of a semiconductor memory device capable of reducing the leakage current of a capacitor and reducing the operation rate when forming a dielectric film using a high dielectric material.
상기 목적을 달성하기 위한, 본 발명에 의한 반도체 메모리소자의 컨패시터 제조방법은, 반도체기판 내에 형성된 트랜지스터의 소오스와 연결되는 하부전극을 형성하는 단계, 상기 하부전극 상에 유전체막을 형성하는 단계, 상기 유전체막 상에 베리어층을 형성하는 단계, 베리어층이 형성된 상기 결과물에 대한 어닐링(annealing) 공정을 실시하여 베리어 특성을 향상시키는 단계, 및 어닐링공정이 진행된 결과물 전면에 상부전극을 형성하는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor memory device, the method including: forming a lower electrode connected to a source of a transistor formed in a semiconductor substrate, forming a dielectric film on the lower electrode; Forming a barrier layer on the dielectric layer, performing an annealing process on the resultant material on which the barrier layer is formed, and improving barrier properties, and forming an upper electrode on the entire surface of the resultant annealing process. do.
본 발명에 의한 반도체 메모리소자의 커패시터 제조방법에 있어서 , 상기 베리어층은 질화티타늄막으로 형성하고, 상기 어닐링 공정은 질소, 산소 및 진공 중 어느 하나의 분위기, 300℃∼ 650℃의 온도에서 실시하는 것이 바람직하다.In the method of manufacturing a capacitor of a semiconductor memory device according to the present invention, the barrier layer is formed of a titanium nitride film, and the annealing process is performed at a temperature of 300 ° C. to 650 ° C. in one of nitrogen, oxygen, and vacuum. It is preferable.
본 발명에 의한 반도체 메모리소자의 커패시터 제조방법에 있어서, 상기 유전체막은 탄탈륨산화막(Ta2O5), 이트늄산화막(Y2O5), 바나듐산화막(V2O5), 니오브늄산화막(Nb2O5), 티타늄산화막(TiO2) 및 실리콘산화막(SiO2) 중 어느 하나를 이용하여 형성하거나, 상기 산화막들을 사용한 다중막 및 상기 산화막들을 사용한 복합조성막 중 어느 하나를 이용하여 형성하는 것이 바람직하며, 상기 하부 및 상부 전극은 다결정실리콘으로 형성한다.In the method of manufacturing a capacitor of a semiconductor memory device according to the present invention, the dielectric film may be a tantalum oxide film (Ta 2 O 5 ), an yttrium oxide film (Y 2 O 5 ), a vanadium oxide film (V 2 O 5 ), or a niobium oxide film (Nb). 2 O 5 ), a titanium oxide film (TiO 2 ) and a silicon oxide film (SiO 2 ) or any one of the multiple film using the oxide film and a composite composition film using the oxide film is formed by Preferably, the lower and upper electrodes are formed of polycrystalline silicon.
따라서, 본 발명에 의한 반도체 메모리소자의 커패시터 제조방법에 의하면, 베리어층, 예컨대 티타늄질화막에 대한 어닐링공정을 실시함으로써, 티타늄질화막의 베리어 특성을 향상시키고, 티타늄질화막 내에 TiON 상(相)을 형성하여 반응방지막으로서의 효율을 증가시키기 때문에, 국부적으로 얇게 형성된 부분에서 발생하던 누설전류 문제 및 유전율 감소문제를 개선할 수 있다.Therefore, according to the method of manufacturing a capacitor of a semiconductor memory device according to the present invention, by performing an annealing process on a barrier layer, such as a titanium nitride film, the barrier properties of the titanium nitride film are improved, and a TiON phase is formed in the titanium nitride film. Since the efficiency as the reaction prevention film is increased, it is possible to improve the leakage current problem and the dielectric constant reduction problem occurring in the locally thinly formed portion.
이하, 첨부한 도면들을 참조하여, 본 발명을 더욱 더 자세하게 설명하고자 한다.Hereinafter, with reference to the accompanying drawings, it will be described in more detail the present invention.
제2도는 본 발명의 일 실시예에 의해 제조된 반도체 메모리소자 제조방법을 설명하기 위해 도시한 단면도로서, 도면부호 50은 반도체기판을, 52는 하부구조물을 절연시킬 목적으로 형성된 층간절연층을, 54는 커패시터의 하부전극을, 56은 커패시터의 유전체막을, 58은 베리어층으로 사용될 TiN 막을 각각 나타낸다.2 is a cross-sectional view for explaining a method of manufacturing a semiconductor memory device manufactured by an embodiment of the present invention, a reference numeral 50 denotes an interlayer insulating layer formed for the purpose of insulating the semiconductor substrate, 54 denotes a lower electrode of the capacitor, 56 denotes a dielectric film of the capacitor, and 58 denotes a TiN film to be used as a barrier layer.
하부전극(54)은 층간절연층(52)에 형성되어 있는 접촉창을 통해 트랜지스터의 소오스(도시되지 않음)와 접속하고 있고, 베리어층(58)은 유전체막(56)과 상부전극(도시되지 않음) 사이에 형성되어 있다.The lower electrode 54 is connected to a source (not shown) of the transistor through a contact window formed in the interlayer insulating layer 52, and the barrier layer 58 is formed of the dielectric film 56 and the upper electrode (not shown). Not formed).
본 발명에 따른 커패시터 제조방법을 살펴보면 먼저, 반도체기판(50)에, 통상의 공정으로, 트랜지스터 및 비트라인등을 형성하고, 그 결과물 전면에, 예컨대 실리콘산화물과 같은 절연물질을 도포하여 층간절연층(52)을 형성한 다음, 상기 층간절연층(52)을 분분적으로 식각하여 트랜지스터의 소오스를 표면으로 노출시키는 접촉창을 형성한다. 이어서, 접촉창이 형성된 결과물 전면에, 예컨대 다결정실리콘과 같은 도전물질을 증착하여 하부전극 형성을 위한 도전층을 형성한 다음, 통상의 원통형 하부전극 형성방법을 이용하여 원통형 하부전극(54)을 형성한다. 이때, 본 발명의 일실시예에서는 원통형 하부전극(54)을 형성하였으나, 기존에 발표되어 있는 여러가지 다른 구조로 형성할 수 있음은 물론이다.Referring to the capacitor manufacturing method according to the present invention, first, in the conventional process, a transistor, a bit line, etc. are formed on the semiconductor substrate 50, and an insulating material such as, for example, silicon oxide is coated on the entire surface of the resultant to form an interlayer insulating layer. After forming 52, the interlayer insulating layer 52 is etched separately to form a contact window for exposing the source of the transistor to the surface. Subsequently, a conductive layer for forming a lower electrode is formed by depositing a conductive material such as polycrystalline silicon on the entire surface of the resultant window on which the contact window is formed, and then, the cylindrical lower electrode 54 is formed using a conventional cylindrical lower electrode forming method. . At this time, in one embodiment of the present invention, the cylindrical lower electrode 54 is formed, but of course, it can be formed in a variety of other structures that have been announced.
계속해서, 하부전극이 형성된 결과물 상에 절연물, 예컨대 오산화탄탈륨을 도포하여 유전체막(56)을 형성하고, 그 결과물 상에 예컨대 티타늄질화물을 스퍼터 방법으로 증착하여 베리어층(58)을 형성한다. 그 후, 베리어층(58)이 형성된 상기 결과물에 대한 어닐링 공정을 진행하고, 그 결과물 상에 다결정실리콘 등의 도전물을 증착하여 상부전극(도시되지 않음)을 형성하여 반도체 메모리소자의 커패시터를 완성한다.Subsequently, an insulating material, for example, tantalum pentoxide, is applied to the resultant on which the lower electrode is formed to form the dielectric film 56, and titanium nitride is deposited on the resultant, for example, by the sputtering method to form the barrier layer 58. Thereafter, an annealing process is performed on the resultant on which the barrier layer 58 is formed, and a conductive material such as polycrystalline silicon is deposited on the resultant to form an upper electrode (not shown) to complete the capacitor of the semiconductor memory device. do.
본 발명에 따르면, 상기 유전체막(56)은 탄탈륨산화막(Ta2O5) 이외에 이트늄산화막(Y2O5) , 바나듐산화막(V2O5) , 니오브늄산화막(Nb2O5), 티타늄산화막(TiO2) 및 실리콘산화막(SiO2) 중에서 선택된 어느하나로 형성할 수 있다.According to the invention, the dielectric film 56 is a tantalum oxide film (Ta 2 O 5) in addition to the teunyum oxide (Y 2 O 5), vanadium oxide (V 2 O 5), niobium titanium oxide (Nb 2 O 5), It may be formed of any one selected from a titanium oxide film (TiO 2 ) and a silicon oxide film (SiO 2 ).
또한, 상기 어닐링 공정은 질소, 산소 및 진공 중 어느 하나의 분위기, 300℃∼650℃의 온도에서 실시하는 것이 바람직하며 , 더욱 바람직하게는 질소분위기에서 실시한다.In addition, the annealing process is preferably carried out in the atmosphere of any one of nitrogen, oxygen and vacuum, the temperature of 300 ℃ to 650 ℃, more preferably in a nitrogen atmosphere.
상기한 본 발명의 일 실시예에서와 같이, 티타늄질화막(베리어층)이 형성된 결과물에 대해 질소분위기에서의 어닐링 공정을 수행하게 되면, 티타늄질화막의 베리어 특성이 향상되어 바이어스 인가시 누설전류가 작아지게 되며 , 어닐링시 극소량의 산소성분이 티타늄질화막에 침투되어 TiON 상(相)이 형성된다. 이는, 티타늄질화막 형성후 형성되는 다결정실리콘층(상부전극)의 실리콘이 탄탈륨산화막(유전체막)과 반응하는 것을 방지할 수 있는 반응방지막으로 작용할 가능성을 증가시키게 된다.As in the embodiment of the present invention described above, when the annealing process in a nitrogen atmosphere is performed on the resultant product on which the titanium nitride film (barrier layer) is formed, the barrier property of the titanium nitride film is improved, so that the leakage current is reduced when bias is applied. When annealing, a very small amount of oxygen penetrates into the titanium nitride film to form a TiON phase. This increases the likelihood that the silicon of the polysilicon layer (upper electrode) formed after the titanium nitride film is formed will act as a reaction prevention film that can prevent the silicon from reacting with the tantalum oxide film (dielectric film).
종래 방법에 의한 반도체 메모리소자의 커패시터의 경우, 단차도포성이 좋지않은 티타늄질화막으로 인해 국부적으로 매우 얇은 두께의 티타늄질화막(제1도의 A)이 형성되고, 이 부분에서 발생하는 누설전류 문제 및 유전율 감소의 문제가 심각하였다.In the case of the capacitor of a semiconductor memory device according to the conventional method, a titanium nitride film (A in FIG. 1) having a very thin thickness is formed locally due to a titanium nitride film having poor step coverage, and leakage current problems and dielectric constants occurring in this portion. The problem of reduction was serious.
그러나, 본 발명의 제조방법에 의한 반도체 메모리소자의 커패시터의 경우, 어닐링공정을 실시함으로써 티타늄질화막의 베리어 특성을 향상시키고, 티타늄질화막 내에 TiON 상(相)을 형성하여 반응방지막으로서의 효율을 증가시키기 때문에, 국부적으로 얇은 두께의 티타늄질화막이 형성되더라도, 이 부분에서 발생하던 누설전류 문제 및 유전율 감소문제를 개선할 수 있다.However, in the case of the capacitor of the semiconductor memory device according to the manufacturing method of the present invention, the annealing process is performed to improve the barrier property of the titanium nitride film, and to form a TiON phase in the titanium nitride film to increase the efficiency as a reaction prevention film. However, even if a locally thin titanium nitride film is formed, the leakage current problem and the dielectric constant reduction problem occurring in this part can be improved.
본 발명은 상기 실시예에 한정되지 않으며, 많은 변형이 본 발명의 기술적 사상내에서 당 분야에서 통상의 지식을 가진 자에 의하여 가능함은 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention.
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