JP5650185B2 - Integrated circuit device comprising discrete elements or semiconductor devices comprising dielectric material - Google Patents

Description

  The present invention relates to semiconductor devices and components, and more particularly to metal oxide dielectric materials for use in semiconductor devices and elements.

[Description of related application]
This application is a continuation of US patent application Ser. No. 08 / 871,024, filed Jun. 6, 1997, which is a US provisional application 60 filed Oct. 10, 1996. The advantages of / 027612 are as claimed. US patent application Ser. No. 08 / 871,024 is hereby incorporated by reference.

Dielectric materials are key to the characteristics of semiconductor devices. As devices become smaller and the need for higher performance increases, the thickness of dielectric layers in semiconductor devices is decreasing. At the same time, there is an increasing need for dielectric materials having a dielectric constant greater than that of the most common dielectric material, S _i O ₂ . Also, as the thickness of the dielectric layer in the semiconductor device decreases, the need for a material that does not leak charge increases even when the dielectric material layer is very thin (eg, 100 mm or less).

  However, not all dielectric materials form a thin dielectric layer that is acceptable for use in semiconductor devices and components. Semiconductor devices have several characteristic requirements such as efficiency and operating power. The properties of the dielectric material layer directly affect the device properties. For example, if a thin dielectric layer transmits too much current through it (this undesirable current is called leakage current), the resulting device or component will not meet the desired characteristic requirements. Since the leakage current through the gate dielectric of MOS (metal-oxide-semiconductor-field effect transistor) indicates the dielectric's insulating properties (resistance and reliability), the gate dielectric layer with too high leakage current through It indicates that the resistance and reliability of the dielectric layer is too low. In dielectric material (IPD) semiconductor devices where the dielectric material layer is between poly (ie, the dielectric material is sandwiched between two layers of polycrystalline silicon), the leakage current in the IPD is dependent on the retention time of the flash memory. is connected with. If the leakage current through the IPD is too high, the device retention time will be low.

  The interface state density between the dielectric layer and the underlying semiconductor interface also affects device characteristics. The interface state density degrades the reliability of current devices (current across the channel) and MOSFETs and MIS (metal-insulator-semiconductor) FETs. Thus, if the interface state density is too high, the resulting device or component will not meet the desired characteristic requirements.

  Accordingly, a dielectric material is sought that forms a thin dielectric layer with acceptable leakage and other properties.

[Summary of the Invention]
The present invention relates to integrated circuit devices having a dielectric material layer and electronic components such as integrated or discrete components such as linear capacitors. The dielectric material relates to a metal oxide of a group III metal or a group VB metal doped with a group IV element. Examples of group III metal oxides (groups as used herein means groups of the Mendeleev Periodic Table) include aluminum oxide (Al ₂ O ₃ ) and yttrium oxide (Y ₂ O ₃ ). It is. Examples of Group VB metal oxides are tantalum pentoxide (Ta ₂ O ₅ ) and vanadium pentoxide (V ₂ O ₅ ). Examples of suitable group IV dopants include zirconium (Zr), silicon (Si), titanium (Ti) and hafnium (Hf). The dopant is about 0.1 weight percent to about 30 weight percent of the metal oxide. It is advantageous if the dopant is about 0.1 weight percent to about 10 weight percent of the metal oxide.

  Using conventional deposition techniques such as sputtering, chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD), a dielectric material layer on the surface of the substrate suitable for the desired device or component. Is formed. During the formation of the layer on the substrate, a dopant is added to the metal oxide. Once the desired thickness of the doped metal oxide has been formed on the substrate, conventional process techniques are then used to complete the device.

In one embodiment of the invention, the semiconductor device is a MOS or MIS device. The structure of such devices is well known to those skilled in the art and will not be described in detail here. The gate dielectric layer in these devices is a doped metal oxide as described above. Due to the low leakage, low interface state density, and the high dielectric constant of these materials, the gate dielectric layer in these devices has a minimum allowable thickness that is limited by the onset of direct tunnel leakage current (eg, about 30 mm or Less than that). There are many tunnel currents, but here the tunnel current directly refers to the tunnel current. Thus, the gate dielectric layer in the device of the present invention is composed of S _i O ₂ (where the minimum thickness is limited by the onset of tunnel leakage current) or undoped metal oxidation such as Al ₂ O _3. There are advantages over conventional dielectric materials such as objects (in this case, the minimum thickness is limited by both high interface state density and onset of tunnel leakage current).

  The MOS device of the present invention is fabricated using conventional techniques well known to those skilled in the art. Conventional process steps before and after the deposition of the gate dielectric layer are considered appropriate.

  In a second embodiment of the invention, the device is a non-volatile memory device. Non-volatile memory is a type of memory that holds stored data when power is removed. Examples of non-volatile memory include erasable programmable read only memory (EPROM) and electrically erasable programmable read only memory (EEPROM). For convenience, flash EEPROM and EPROM are collectively referred to herein as EPROM.

  The non-volatile memory device of the present invention has a conventional structure, but the IPD layer of the device is the dielectric material of the present invention. The IPD layer is deposited using the deposition technique described above. The non-volatile memory device of the present invention is formed using conventional process techniques to form such a device both before and after forming the IPD layer.

  Another device in which the dielectric material of the present invention may be useful is a storage capacitor for dynamic random access memory (DRAM). The dielectric material of the present invention is also useful as a dielectric layer in linear capacitors and other integrated capacitors and capacitive devices.

[Detailed description]
The present invention relates to doped metal oxide materials. These doped metal oxides are used to form dielectric material layers in various device components such as MOS devices, flash EPROM devices, DRAM capacitors, linear capacitors and other capacitors. The doped metal oxide dielectric material of the present invention is a Group III or Group VB metal oxide doped with a Group IV element. For a given metal and dopant combination, it is advantageous if the energy of oxide formation for the dopant is less than the energy of oxide formation for the doped metal oxide. Examples of group III metal oxides (group here means the group of the Mendeleev Periodic Table) include aluminum oxide (Al ₂ O ₃ ) and yttrium oxide (Y ₂ O ₃ ). Examples of Group VB metal oxides are tantalum pentoxide (Ta ₂ O ₅ ) and vanadium pentoxide (V ₂ O ₅ ). Examples of suitable group IV dopants include zirconium (Zr), silicon (Si), titanium (Ti) and hafnium (Hf). The doped metal oxide includes about 0.1 weight percent to about 30 weight percent dopant. It is advantageous if the doped metal oxide comprises about 0.1 weight percent to about 10 weight percent dopant.

  Applicants do not wish to retain a particular theory, but the presence of dopants stabilizes defects in the bulk of the metal oxide and defects formed at the interface between the semiconductor or metal layer adjacent to the metal oxide. I am convinced that Such defects include dangling bonds or strain bonds or grain boundaries. An unbonded hand is an atom with an incomplete bond, as its name implies. Therefore, dangling bonds (also referred to as trap levels here) are not desirable. Strain bonds are bonds that have undergone some kind of strain due to the physical properties of the interface. These distorted bonds are more easily broken, resulting in unbonded hands. Thus, distorted bonds are also undesirable.

  It is advantageous to reduce the number of dangling bonds and strain bonds and to stabilize the grain boundaries in the bulk material and at the interface between the dielectric material and the adjacent layer. This is because such a reduction improves the electrical properties of the dielectric material. Applicants are convinced that the addition of the above-described dopants to the dielectric materials described herein actually reduces these undesirable defects. The amount of dopant introduced into the metal oxide will depend on the desired electrical properties of the dielectric material. Applicants believe that the doped dielectric material of the present invention is advantageous because the energy of oxide formation for the dopant is less than the enthalpy of oxide formation for the post-oxidation doped metal.

  For example, the enthalpy of formation for aluminum oxide is -390 kcal / mol. The enthalpy of formation for zirconium oxide is -266 kcal / mol. The enthalpy of formation for silicon oxide is -217 kcal / mol. A layer of aluminum oxide material includes a number of dangling bonds, strain bonds, and grain boundaries at the interface with the bulk and dielectric materials and adjacent layers. If the same layer of aluminum oxide is doped with zirconium or other Group IV metal, the number of dangling bonds, strain bonds and grain boundaries in the bulk material and at the interface between the dielectric material and adjacent layers is reduced. Applicants believe that it is a result of reaction thermodynamics that is more suitable for the formation of dopant oxides (eg, zirconium oxide) than the formation of metal oxides (eg, aluminum oxide). The dangling bonds, strain bonds, and grain boundaries at the bulk material and at the interface of the amount of dielectric stay are not formed to the same extent. This is because dopants (eg, zirconium) can react with oxygen at the location of these possible defects, thereby removing at least some of them. As a result, the properties of the dielectric material are improved over the undoped dielectric material.

  As previously mentioned, the dielectric materials of the present invention are used in a variety of electronic devices and electronic components.

  In one embodiment of the invention, the doped dielectric material is a gate dielectric material in a MOSFET device. Such a device is schematically depicted in FIG. The MOSFET (10) has a source (11), a drain (12) and a gate (13). The gate (13) is disposed between the side wall spacers (14) and (15). The source (11) and drain (12) extend from contact with the sidewall spacers (14) and (15) to each field oxide region (16) and (17). The gate dielectric layer (18) is the doped metal oxide material of the present invention.

In a second embodiment of the invention, the doped dielectric material is the IPD of a flash EPROM device. Such a device is shown in FIG. The device has a layer of silicon dioxide (S _i O ₂ ) formed on a substrate (110) having a source (112), a drain (114) and a channel region (116) formed therein. The oxides are formed by conventional techniques such as furnace oxidation and rapid thermal oxidation (RTO) in a normal atmosphere, such as O ₂ and N ₂ O, well known to those skilled in the art.

  A polysilicon floating gate (122) is formed on the gate oxide layer (120). The polysilicon layer (122) is formed using conventional techniques such as chemical vapor deposition (CVD). The thickness of the polysilicon layer (122) is a design choice. Typically, the thickness of the floating gate is about 50 nm to about 100 nm.

  The IPD (124) is formed on the floating gate using conventional techniques. Typically, techniques such as sputtering, chemical vapor deposition or oxidation are used to form the IPD layer. As mentioned earlier, it is advantageous if the IPD layer has a dielectric constant of at least about 8 but does not cause significant leakage current from the floating gate. In this example, the dopant concentration should not result in a material with unacceptably high leakage and unacceptably low yield strength.

In order for the device to retain that charge for at least about 10 years, the charge leakage through the IPD layer should be no more than about 10 ⁻¹⁴ A / cm ² . In this embodiment, a low leakage material is desirable so that charge is kept on the floating gate. The dielectric materials described above are examples of materials that meet this requirement.

  The control gate (126) is a layer of conductive material formed on the IPD layer (124). The control gate is doped polysilicon, metal silicide, titanium nitride or a double layer of polysilicon and metal silicide. The control gate layer is formed and patterned using conventional techniques for fabricating MOS devices.

In this embodiment, in the device of the present invention, the material and thickness of the IPD layer are selected to achieve a device that operates at a low voltage and holds the charge on the floating gate for an appropriate long period of time. In the device of the present invention, the material and thickness of the IPD layer and the thickness of the tunnel oxide (TO) layer are selected such that K _IPD E _IPD ≈K _TO E _TO . In this equation, the dielectric constant of the material is denoted by K and the electric field of the layer is denoted by E. In the context of the present invention, _ETO is advantageously large enough to create an atmosphere in which the device can be erased in a short time. In this regard, it is advantageous if the E _IPD is at least about 8 MV (megavolt) / cm. _Also, the smaller the _{E IPD,} since the reliability of the IPD is _high, it is advantageous and _{E IPD} is small. In this regard, it is advantageous if the E _IPD is less than about 5 MV / cm. Since K _TO is _fixed, the _{K IPD} increases, to bias on a given control gate, also with respect to the tunnel oxide and _{IPD, E TO} increases.

  In a third embodiment of the present invention, a dielectric material is used in the storage capacitor of a DRAM device. In a fourth embodiment of the invention, the dielectric material is used in a linear capacitor. It is also conceivable to use the dielectric material of the present invention for other integrations and discrete capacitors.

  In the above embodiments, the dielectric material has been described as a single layer containing one dopant. However, it is also conceivable that the dielectric layer includes one or more individual layers of material. In the multi-layer embodiment, at least one of the layers is doped as described above. Those skilled in the art will recognize that multilayer structures are useful when one layer is used to make the desired dielectric layer and one layer is used to improve the interface between the dielectric layer and the adjacent layer. I will. Similarly, a doped layer can include one or more dopants. For example, a first dopant is added in the metal oxide to improve the dielectric properties of the metal oxide, and a second dopant is to improve the interface between the dielectric material and the material adjacent to the dielectric layer. Can be added.

Example 1
Several thin films of doped and undoped aluminum oxide were formed. The dopants used are zirconium and silicon. The thin film was formed on a 6 inch silicon wafer. Prior to forming the metal oxide thin film on the substrate, the substrate was cleaned with an aqueous solution of hydrofluoric acid (15: 1 HF). After cleaning, the silicon substrate was placed in a load lock vacuum vessel so that no further native oxide grew.

  Doped and undoped aluminum oxide thin films were formed on the substrate using reactive sputtering in an argon / oxygen atmosphere. An aluminum target with a uniform distribution of 1 percent silicon by weight was used to form the silicon doped thin film. An aluminum target with a uniform distribution of 0.5 weight percent zirconium was used to form the zirconium doped thin film. A high purity (99.9 weight percent) aluminum target was used to form the undoped aluminum oxide thin film.

  The thin film was formed by placing a desired target in the sputtering chamber. Next, argon and oxygen were introduced into the container. A plasma glow was grown by applying alternating current (AC) power between the cathode and anode in the range of about 1 kW to about 2 kW. (The specific current used depends on the system used.) In order to oxidize the target surface, the target was quenched prior to deposition. Current and voltage were monitored to ensure that quenching was complete.

  The substrate was kept at 380 ° C. while the metal oxide thin film was sputter deposited onto it. The deposition rate was 1.1 kg / sec. The resulting thin film thickness varied within 2 percent on the surface of the wafer. Oxygen and argon flow rates were controlled during thin film deposition using a mass flow controller.

  The thickness of each thin film was about 10 nm. One of each type of thin film was then annealed at 550 ° C. for 30 minutes in a nitrogen atmosphere. The second of each type of thin film was subsequently annealed at 550 ° C. in an oxygen atmosphere for 30 minutes.

The leakage current through the various films was measured using standard current-voltage (IV) tests well known to those skilled in the art. The applied voltage was 1.5 MV (megavolt) / cm. The surface area of the thin film was 1000 μm ² . The results for thin films annealed at 550 ° C. are reported in FIG. FIG. 2 shows that the leakage current through the undoped thin film is more than an order of magnitude greater than the leakage current in the silicon oxide or zirconium doped aluminum oxide thin film. The leakage current characteristics of the thin film annealed in the oxygen atmosphere were substantially the same as the leakage characteristics of the thin film annealed in the nitrogen atmosphere. The thin film annealed at 800 ° C. and the thin film not annealed showed the same tendency.

The interface and lap density of the various thin films were measured using standard capacitance-voltage (CV) quasi-static methods well known to those skilled in the art. The surface area of the thin film was 100 μm ² . The result is shown in FIG. In FIG. 3, the interface state density of the undoped thin film was one order of magnitude higher than the interface state density in the aluminum oxide thin film doped with silicon or zirconium.

It is a schematic side view of MOSFET of this invention. 1 is a schematic side view of a flash EPROM device of the present invention. FIG. FIG. 3 compares the leakage characteristics of the doped metal oxide dielectric material of the present invention with the leakage characteristics of an undoped metal oxide layer. FIG. 4 is a diagram comparing the interface and wrap density of a doped metal oxide dielectric material of the present invention with the interface and wrap density of an undoped metal oxide layer.

10 MOSFET
11 Source 12 Drain 13 Gate 14, 15 Side wall spacer 16, 17 Field oxide region 110 Substrate 112 Source 114 Drain 116 Channel region 120 Gate oxide layer 122 Floating gate, polysilicon layer 124 IPD, IPD layer 126 Control gate

Claims (8)

A method of manufacturing an integrated circuit device comprising discrete elements comprising a dielectric material or a semiconductor device comprising:
The dielectric material is a metal oxide selected from the group consisting of aluminum oxide, yttrium oxide, tantalum pentoxide, vanadium oxide,
Zirconium doped with at least one Group IV element selected from the group consisting of titanium and hafnium, the Group IV element after said doping is oxidized in this state, the dielectric material in the presence of oxygen, sputtering, Produced by a deposition method selected from the group consisting of chemical vapor deposition and atomic layer deposition;
The metal oxide has a first oxide formation energy, the group IV element oxide has a second oxide formation energy, and the first oxide formation energy is the second oxide. Greater than the formation energy,
The amount of dopant is from 0.1 weight percent to 30 weight percent;
The presence of the dopant stabilizes defects in the bulk of the metal oxide and defects formed at the interface of the semiconductor or metal layer adjacent to the metal oxide;
A method of manufacturing an integrated circuit device.   The method of manufacturing an integrated circuit device according to claim 1, wherein the amount of the dopant is 0.1 weight percent to 10 weight percent of the dielectric material.   2. The method of manufacturing an integrated circuit device according to claim 1, wherein the component is a MOS device and the dielectric material is a gate dielectric of the MOS device.   2. The method of manufacturing an integrated circuit device according to claim 1, wherein the component is a MIS device and the dielectric material is a gate dielectric of the MIS device.   2. The method of manufacturing an integrated circuit device according to claim 1, wherein the component is a nonvolatile memory device, and the dielectric material is an interpoly dielectric layer of the nonvolatile memory device.   2. The method of manufacturing an integrated circuit device according to claim 1, wherein the component is a capacity for a dynamic random access memory device.   2. The method of manufacturing an integrated circuit device according to claim 1, wherein the component is a linear capacitor and the dielectric material is a capacitive dielectric material.   The method of manufacturing an integrated circuit device according to claim 1, wherein the dielectric material is a multilayer structure, and at least one of the layers is a doped metal oxide layer.

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