JPS62118524A - Manufacture of semiconductor element - Google Patents

Manufacture of semiconductor element

Info

Publication number
JPS62118524A
JPS62118524A JP25765385A JP25765385A JPS62118524A JP S62118524 A JPS62118524 A JP S62118524A JP 25765385 A JP25765385 A JP 25765385A JP 25765385 A JP25765385 A JP 25765385A JP S62118524 A JPS62118524 A JP S62118524A
Authority
JP
Japan
Prior art keywords
substrate
resist mask
metal layer
deposited metal
metallic layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25765385A
Other languages
Japanese (ja)
Inventor
Mutsuzou Takada
高田 睦三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP25765385A priority Critical patent/JPS62118524A/en
Publication of JPS62118524A publication Critical patent/JPS62118524A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To enable the lift-off processing with excellent workability and reliability to be performed while forming thick deposit metallic layer together with thin resist film by a method wherein deposit metallic layer comprising metallic material for interconnection is formed on a resist mask formed on a substrate and then the unnecessary part of deposit metallic layer is removed by lifting off an adhesive film. CONSTITUTION:A resist mask 2 1mum thick with overhang ends is formed on a substrate 1 and then a deposit metallic layer 3 comprising metallic material for wiring around 0.6mum thick is deposited. Next a bonding film 5 is pressure- fixed on the substrate 1. Then the substrate 1 is fixed by vacuumizing or using a fixture and then the bonding film 5 is lifted off in the arrow direction. Through these procedures, the connecting part 4 between the first and the second deposit metallic films 3a, 3b is completely cut of and the second deposit metallic layer 3b is lifted off together with the bonding film 5. Later the residual resist mask 2 is removed by melted cleaning or plasma processing to form a wiring pattern by the first deposit metallic layer 3a.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体素子の製造方法に関し、特にGaAa等
の化合物半導体を用いた素子の製造プロセスにおいて、
基板上への金属膜のパターン形成方法に係る。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly in a process for manufacturing a device using a compound semiconductor such as GaAa.
The present invention relates to a method for forming a pattern of a metal film on a substrate.

〔従来の技術〕[Conventional technology]

従来、基板上への金属膜のパターン形成方法としては、
レジストコートと共に配線部以外の金属膜を同時に除去
する所謂リフトオフ法があった。
Conventionally, the method of patterning a metal film on a substrate is as follows:
There is a so-called lift-off method in which the resist coat and the metal film other than the wiring portion are removed at the same time.

このリフトオフ法は、周知のように微細パターン、ある
いは化学エツチングが困難な金属パターンの形成に多用
されている。
As is well known, this lift-off method is often used to form fine patterns or metal patterns that are difficult to chemically etch.

以下、第2図を基にこの従来例を説明する。まず同図(
a)に示すように、基板1上にレジスト膜2を所定膜厚
に形成する。次に同図(b)の如く、レジスト膜2にパ
ターニングを施しレジストマスク2aを形成すjる。次
いで、この試料上に金属を所定膜厚積層させると、同図
(c>のように、基板1上には第1の堆積金属層3が、
またレジストマスク2a上には第2の堆積金属層3aが
夫々形成される。
This conventional example will be explained below based on FIG. 2. First, the same figure (
As shown in a), a resist film 2 is formed on a substrate 1 to a predetermined thickness. Next, as shown in FIG. 2B, the resist film 2 is patterned to form a resist mask 2a. Next, when metal is laminated to a predetermined thickness on this sample, the first deposited metal layer 3 is formed on the substrate 1, as shown in the same figure (c>).
Further, second deposited metal layers 3a are respectively formed on the resist masks 2a.

その後、リフトオフの溶剤中に試料を浸漬すると、レジ
ストマスク2aの溶解と共に第2の堆積金属層3aが剥
離され、同図(d)に示す如き所定の配線パターンが得
られる。
Thereafter, when the sample is immersed in a lift-off solvent, the resist mask 2a is dissolved and the second deposited metal layer 3a is peeled off, resulting in a predetermined wiring pattern as shown in FIG. 3(d).

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、上記従来例においては、リフトオフ処理
を容易且つ確実にする為に、堆積金属層必要であり、ま
たレジストを均一にコーティングする事ができるのは約
1μmが限度であった。
However, in the above-mentioned conventional example, a deposited metal layer is required to facilitate and ensure the lift-off process, and the thickness of the resist that can be uniformly coated is limited to approximately 1 μm.

この為、堆積金属層の膜厚が5ooouを超えてくると
、第3図に示すように、基板1上の第1の堆積金属層3
と、レジストマスク2a上の第2の堆積金属層3aとに
接続部4が生ずる。従ってリフトオンする際、レジスト
マスク2aへの溶剤の浸潤が悪くなり、超音波洗浄等の
処理を加えてもバターニングに長時間を要し、作業性が
低下するという問題があつi。
For this reason, when the thickness of the deposited metal layer exceeds 5000, the first deposited metal layer 3 on the substrate 1 will be removed as shown in FIG.
A connection portion 4 is formed between the resist mask 2a and the second deposited metal layer 3a on the resist mask 2a. Therefore, during lift-on, there is a problem in that the infiltration of the solvent into the resist mask 2a becomes poor, and even if a process such as ultrasonic cleaning is applied, a long time is required for patterning, resulting in a decrease in workability.

また超音波等の機械的衝撃を加える場合、基板が耐衝撃
性に難のあるQaAsであれば破損する確率が高くなシ
、信頼性の点からプロセス上好ましくないという問題が
あった。
Further, when applying mechanical shock such as ultrasonic waves, if the substrate is made of QaAs, which has poor impact resistance, there is a high probability of breakage, which is unfavorable from the viewpoint of reliability in the process.

従って、本発明は以上述べた諸問題を解消し、レジスト
膜厚を均一形成が可能な1μm範囲内にすると共に堆積
金属層を従来よシも厚く形成でき、しかも作業性、信頼
性に優れたリフトオフ処理を1−する半導体素子の製造
方法を提供する事を目的とする。
Therefore, the present invention solves the above-mentioned problems, makes it possible to make the resist film thickness within the range of 1 μm that can be formed uniformly, and makes it possible to form a deposited metal layer thicker than before, with excellent workability and reliability. It is an object of the present invention to provide a method for manufacturing a semiconductor device that undergoes a lift-off process.

〔問題点を解決するための手段〕[Means for solving problems]

本発明に係る半導体素子の製造方法は、(a)基板上に
所定形状のノeターンをMするレジストマスクを形成し
、その後配線用の金属層から成る堆積金属層を形成する
工程、 (b)その後、この試料」二に粘着フィルムを押圧密着
する工程、 (c)上記粘着フィルムを剥離する工程とを含むもので
ある。
The method for manufacturing a semiconductor device according to the present invention includes the steps of (a) forming a resist mask having a predetermined shape of a no-e turn on a substrate, and then forming a deposited metal layer consisting of a metal layer for wiring; ) Thereafter, the process includes the steps of: (c) peeling off the adhesive film; and (c) peeling off the adhesive film.

〔作 用〕[For production]

以上のように、本発明によれば基板上に所望のレジスト
マスクを形成し、その後配線用の金属材から成る堆積金
属層を形成する為、基板上には直接配線パターン用の第
1の堆積金属層が、!、た上記レジストマスク上にはリ
フトオフ法により除去される第2の堆積金属層が夫々形
成される。
As described above, according to the present invention, a desired resist mask is formed on a substrate, and then a deposited metal layer made of a metal material for wiring is formed. The metal layer! , and a second deposited metal layer is formed on the resist mask, respectively, and is removed by a lift-off method.

また、粘着フィルムを基板上に押圧密着する為、この粘
着フィルムは上記第2の堆積金属層とのみ密着され、一
方この際、レジストマスクは基板に対する機械的ストレ
スを緩和するよう作用する。
Further, since the adhesive film is pressed and adhered to the substrate, the adhesive film is brought into close contact only with the second deposited metal layer, and at this time, the resist mask acts to relieve mechanical stress on the substrate.

更に、上記粘着フィルムを剥離する場合、上記第2の堆
積金属層のみが同時に密着剥離される。
Further, when the adhesive film is peeled off, only the second deposited metal layer is peeled off at the same time.

〔実施例〕〔Example〕

以下、第1図に基き本発明の一実施例を詳細に説明する
。′−!ず同図(a)に示す如く、基板l上にパターニ
ングによシ1μm厚のレジストマスク2を端部がオーバ
ーハング状となるように形成した後、配線用の金属材か
ら成る堆積金属層3を0.611m程度積層する。この
場合、基板1上には配線パターン用の第1の堆積金属層
(パターン幅は1μm程度〕3aが、またレジストマス
ク2上には後工程で除去される第2の堆積金属層3bが
夫々積層形成される。なお、4は第1及び第2の堆積金
属層3a。
Hereinafter, one embodiment of the present invention will be described in detail based on FIG. ′-! First, as shown in FIG. 5A, a resist mask 2 with a thickness of 1 μm is formed on a substrate 1 by patterning so that the end portion has an overhang shape, and then a deposited metal layer 3 made of a metal material for wiring is formed. 0.611m thick. In this case, on the substrate 1 is a first deposited metal layer 3a for a wiring pattern (pattern width is about 1 μm), and on the resist mask 2 is a second deposited metal layer 3b to be removed in a later process. The numeral 4 indicates the first and second deposited metal layers 3a.

3bの接続部である。This is the connection part of 3b.

次に同図(b)に示すように、粘着フィルム(日東製ダ
ンプロンチーi 、 [)iaco 製エレクトロンテ
、−プ等)5を用い、粘着層6を基板1側にしてゴム等
のローラ7を矢印Bの垂直方向に加圧しながら矢印Aの
方向に移動させ、上記粘着フィルム5を基板1上に押圧
密着する。この際、基板1に垂if方向から加わる機械
的ストレスは、レジストマスク2の介在により緩和され
る。そして同図(c)のように、基板1を真空引き、あ
るいは固定治具(図示せず)を用いる事により固定し、
粘着フィルム5を矢印の方向へ向けて引き剥す。この処
理によシ、第1及び第2の堆積金属層3a 、3b間の
接続部4は完全に切断され、第2の堆積金属層3bは粘
着フィルム5と共に剥離される。図中、破断線上方の点
線、及びこれに続く実線は剥離後の粘着フィルム5を模
式的に表したものである。
Next, as shown in the same figure (b), using an adhesive film (Nitto's Danpronchi I, [)iaco's Electronte, -pu, etc.) 5, a roller 7 made of rubber or the like is placed with the adhesive layer 6 on the substrate 1 side. is moved in the direction of arrow A while applying pressure in the direction perpendicular to arrow B, and the adhesive film 5 is pressed tightly onto the substrate 1. At this time, the mechanical stress applied to the substrate 1 from the vertical if direction is alleviated by the interposition of the resist mask 2. Then, as shown in FIG. 3(c), the substrate 1 is fixed by vacuuming or using a fixing jig (not shown),
Peel off the adhesive film 5 in the direction of the arrow. Through this treatment, the connection 4 between the first and second deposited metal layers 3a and 3b is completely severed, and the second deposited metal layer 3b is peeled off together with the adhesive film 5. In the figure, the dotted line above the break line and the solid line following it schematically represent the adhesive film 5 after peeling.

々お、レジストマスク2と第2の堆積金属層3bとは、
図示の0部のようにその界ih+から剥がれるか、また
は0部のよりにレジストマスク2が第2の堆積金属層3
bと密着して層間がちぎれるようにして剥がれる。また
、粘着層6と第1の堆積金属層3aとは、レジストマス
ク2の厚み(1融相度)の為に密着する事t1ないので
、剥離処理においては、第2の堆積金)A/f13bの
みが剥離される事どなる。
Furthermore, the resist mask 2 and the second deposited metal layer 3b are
The resist mask 2 is peeled off from the boundary ih+ as shown in the 0 part, or the resist mask 2 is removed from the second deposited metal layer 3 as shown in the 0 part.
It adheres closely to b and peels off as if the layer is torn apart. Further, since the adhesive layer 6 and the first deposited metal layer 3a do not come into close contact with each other due to the thickness of the resist mask 2 (1 melting phase degree), in the peeling process, the second deposited metal layer 3a) What happens is that only f13b is peeled off.

ここで、粘着フィルム5の押圧密着処理と剥離処理とは
、同図(d)に示すようなローラー型の粘着フィルムを
用いれば連続して行う事ができる。即チ、巻きフィルム
5aから粘着フィルム5を、矢印の方向にローラ7を介
して堆積金属層3を形成後の基板部1aに押圧密着させ
る一方、これらと同方向に連動して回転する巻き取りロ
ーラ5bにより、押圧密着後の粘着フィルム5を巻き上
げる事により粘着フィルム5と基板1間に気泡が生ずる
事なく、シかも剥離処理が連続的に行われる。
Here, the pressure adhesion treatment and the peeling treatment of the adhesive film 5 can be performed continuously by using a roller-type adhesive film as shown in FIG. 4(d). In other words, the adhesive film 5 is pressed and brought into close contact with the substrate portion 1a on which the deposited metal layer 3 has been formed in the direction of the arrow via the roller 7 in the direction of the arrow, while the winding film 5 rotates in conjunction with these in the same direction. By rolling up the adhesive film 5 after being pressed into close contact with the roller 5b, the peeling process is continuously performed without generating air bubbles between the adhesive film 5 and the substrate 1.

その後、残ったレジストマスク2を溶解洗浄、またはプ
ラズマ処理により除去し、第1の堆積金属層3aによる
配ffMパターンが得られる。
Thereafter, the remaining resist mask 2 is removed by dissolving and cleaning or plasma processing, and an ffM pattern formed by the first deposited metal layer 3a is obtained.

このように本発明によれば、リフトオフされる第2の堆
積金F4層3bが粘着フィルム5に密着して剥離される
為、金属の再付着が回避され、しかもこれを簡単に回収
する事ができる。
As described above, according to the present invention, the second deposited gold F4 layer 3b to be lifted off is peeled off in close contact with the adhesive film 5, so that re-adhesion of metal is avoided and it can be easily recovered. can.

なお上記基板1には、QaAs等の化合物半導体の単結
晶基板の他、これにSi0g膜、 Sl、N4膜等の絶
縁膜を積層形成させた基板でも良く、81単結晶基板は
勿論、各種基板を幅広く適用する事ができる。
In addition to a single crystal substrate of a compound semiconductor such as QaAs, the substrate 1 may also be a substrate on which an insulating film such as a Si0g film, Sl, N4 film, etc. is laminated. can be widely applied.

〔発明の効果〕〔Effect of the invention〕

以上詳#Ij1に説明り、 1jように、本発明によれ
ば堆積金属層の形成体、不要な個所(第2の堆積金属層
)を粘着フィルムの押FIE密着、及び剥離により除去
する為、この堆積金属層を(堆積金属層の膜厚)り(し
・ノストマスクの膜厚)の範囲内で、換言すれば最大1
μ?n程度と厚く形成する事ができる。
As explained above in detail in #Ij1, and as shown in 1j, according to the present invention, in order to remove the deposited metal layer formation and unnecessary portions (second deposited metal layer) by pressing the adhesive film into close contact with each other and peeling it off, This deposited metal layer is within the range of (film thickness of deposited metal layer) (film thickness of nost mask), in other words, maximum 1
μ? It can be formed as thick as approximately n.

従って、ンート抵hi:が50inΩΔ1以下の低抵抗
の配線層が得られるという効果がある。
Therefore, there is an effect that a low-resistance wiring layer having a root resistance hi: of 50 inΩΔ1 or less can be obtained.

また堆積金属層を厚く形成i−ても、従来のようにリフ
ト」フの浴剤のN潤性ケ良くする為の長時間の浸漬さら
に超音波処理が不要となるので、基板への機械的ストレ
スが抑制され、L2かも作業(11が向上するという効
果がある。
In addition, even if the deposited metal layer is formed thickly, there is no need for long-time immersion or ultrasonic treatment to improve the N-moisture properties of the lift bath agent, which is required in the conventional method. It has the effect of suppressing stress and improving L2 and work (11).

更に、リフトオフ法を有効に利JIJする為、十M雑な
微細パターンも容易に形成する事ができるという効果も
あり、高い工業的利用価値を七−するものである1、
Furthermore, in order to effectively utilize the lift-off method, it is possible to easily form even a coarse fine pattern of 10M, making it highly valuable for industrial use1.

【図面の簡単な説明】 第1図は本発明の一実施例を説明する工程断面図、第2
図は従来例を説明する工程断面図、第3図は従来例の欠
点を説明する要部断面図である。 1・・・基板、2・・・レジストマスク、3・・・堆積
金属層、3a・・・第1の堆積金属層、3b・・・第2
の堆積金属層、5・・・粘着フィルム、6・・・粘着層
、7・・・ローラ。 手続補正書
[BRIEF DESCRIPTION OF THE DRAWINGS] Fig. 1 is a cross-sectional view of a process for explaining one embodiment of the present invention;
The figure is a process cross-sectional view explaining the conventional example, and FIG. 3 is a main part cross-sectional view explaining the drawbacks of the conventional example. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Resist mask, 3... Deposited metal layer, 3a... First deposited metal layer, 3b... Second
Deposited metal layer, 5...adhesive film, 6...adhesive layer, 7...roller. Procedural amendment

Claims (1)

【特許請求の範囲】[Claims] (1)基板上へ金属膜の配線パターンを形成する半導体
素子の製造方法において、 (a)上記基板上に所定形状のパターンを有するレジス
トマスクを形成し、その後配線用の金属材から成る堆積
金属層を形成する工程、 (b)その後、この試料上に粘着フィルムを押圧密着す
る工程、 (c)上記粘着フィルムを剥離する工程 とを含む事を特徴とする半導体素子の製造方法。
(1) In a method of manufacturing a semiconductor device in which a wiring pattern of a metal film is formed on a substrate, (a) a resist mask having a pattern of a predetermined shape is formed on the substrate, and then a deposited metal made of a metal material for wiring is formed. A method for manufacturing a semiconductor device, comprising the steps of: forming a layer; (b) then press-fitting an adhesive film onto the sample; and (c) peeling off the adhesive film.
JP25765385A 1985-11-19 1985-11-19 Manufacture of semiconductor element Pending JPS62118524A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25765385A JPS62118524A (en) 1985-11-19 1985-11-19 Manufacture of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25765385A JPS62118524A (en) 1985-11-19 1985-11-19 Manufacture of semiconductor element

Publications (1)

Publication Number Publication Date
JPS62118524A true JPS62118524A (en) 1987-05-29

Family

ID=17309235

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25765385A Pending JPS62118524A (en) 1985-11-19 1985-11-19 Manufacture of semiconductor element

Country Status (1)

Country Link
JP (1) JPS62118524A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1353362A3 (en) * 2002-04-09 2006-03-08 Northrop Grumman Corporation Process for fabricating a semiconductor
JP2006175343A (en) * 2004-12-22 2006-07-06 Matsushita Electric Ind Co Ltd Rice polishing device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1353362A3 (en) * 2002-04-09 2006-03-08 Northrop Grumman Corporation Process for fabricating a semiconductor
JP2006175343A (en) * 2004-12-22 2006-07-06 Matsushita Electric Ind Co Ltd Rice polishing device

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