JPS61280660A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS61280660A
JPS61280660A JP12301085A JP12301085A JPS61280660A JP S61280660 A JPS61280660 A JP S61280660A JP 12301085 A JP12301085 A JP 12301085A JP 12301085 A JP12301085 A JP 12301085A JP S61280660 A JPS61280660 A JP S61280660A
Authority
JP
Japan
Prior art keywords
wafer
reinforcing plate
semiconductor device
transparent member
stuck
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12301085A
Other languages
Japanese (ja)
Inventor
Koji Suzukawa
鈴川 光二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP12301085A priority Critical patent/JPS61280660A/en
Publication of JPS61280660A publication Critical patent/JPS61280660A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To reduce the electric resistance and thermal resistance of a wafer by a method wherein the wafer is once stuck on a reinforcing plate of a transparent member and thinned and then the reinforcing plate is removed to make the wafer thin sufficiently. CONSTITUTION:An element is formed in a very shallow region under the main surface of a wafer 10. Next, this wafer 10 being set on the main surface side, it is stuck on a reinforcing plate 12 formed on a transparent member, with an adhesive layer 11 interposed therebetween. It is because positioning be accurate in a subsequent scribing process that the reinforcing plate 12 is formed of the transparent member. The exposed back side of the wafer 10 is subjected to lapping or the like, and the wafer 10 is cut into a thin wafer 13. After the back surface is subjected to a prescribed back-surface processing, a back-side electrode 14 is stuck thereon. Then, the scribing process is applied to the back- side electrode 14 and the wafer 13 to form scribed grooves 15. Thereafter the adhesive layer 11 is melted away by a prescribed solvent, and thereby semiconductor devices 20 comprising respective elements are obtained.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、半導体装置の製造方法に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to a method for manufacturing a semiconductor device.

〔発明の技術的背景〕[Technical background of the invention]

従来、高周波高出力トランジスタからなる半導体装置は
、例えば第3図(A)乃至同図体)に示す工程によりa
造されている。すなわち、まず、同図(〜に示す如く、
所定の素子(図示せず)を主面側に形成した厚さDs3
00〜600μmのウェハ1を用意する。次いで、この
ウェハ1の裏面側を150〜350−程度除去し、同図
(B)に示す如く、厚さDz150〜250μmの薄肉
の9エバ2にする。このように薄肉化するのは、熱抵抗
及び電気抵抗を下げるためである。次いで、同図(Qに
示す如く、薄肉にしたウェハ2の裏面側に裏面電極3を
貼着する。次に、同図(Oに示す如く、裏面電極3及び
ウェハ2を所定の素子ごとのパターンに分割するための
スクライブ#4を形成する。然る後、このスクライブ溝
4に従ってウェハ2を分割することによシ、同図(E)
 K示す如く、各々の素子からなる半導体装置5′j&
:得る。
Conventionally, a semiconductor device consisting of a high-frequency, high-output transistor has been manufactured by a process shown in FIG.
It is built. That is, first, as shown in the same figure (~
Thickness Ds3 when a predetermined element (not shown) is formed on the main surface side
A wafer 1 having a diameter of 00 to 600 μm is prepared. Next, about 150 to 350 mm of the back side of this wafer 1 is removed to form a thin 9-layer wafer 2 with a thickness Dz of 150 to 250 μm, as shown in FIG. The purpose of reducing the thickness in this way is to lower thermal resistance and electrical resistance. Next, as shown in the same figure (Q), the back electrode 3 is attached to the back side of the thinned wafer 2.Next, as shown in the same figure (O), the back electrode 3 and the wafer 2 are attached to each predetermined element. A scribe #4 is formed to divide the wafer into patterns.Then, by dividing the wafer 2 according to the scribe groove 4, the wafer 2 is divided into patterns (E)
As shown in K, a semiconductor device 5'j&
:obtain.

〔背景技術の問題点〕[Problems with background technology]

このようにして半導体装置を得る従来の方法では、ウェ
ハ1を薄肉にできる限界が後のスクライプ処理等にて制
限されるため、通常150〜250μm程度であった。
In the conventional method of obtaining a semiconductor device in this way, the limit to which the wafer 1 can be made thin is usually about 150 to 250 μm because it is limited by the subsequent scribing process and the like.

このため、電気抵抗、熱抵抗を十分に低減させることが
できず信頼性の高い半導体装置5を得ることができなか
った。
For this reason, the electrical resistance and thermal resistance could not be sufficiently reduced, and a highly reliable semiconductor device 5 could not be obtained.

そこで、所謂(レットサイ、+L′を大きくして相対的
に肉厚を薄くシ、熱抵抗の低減を図る手段か採られでる
が、この手段では装置が大型化する欠点がある。
Therefore, a measure has been taken to reduce the thermal resistance by increasing +L' and making the wall thickness relatively thin, but this measure has the disadvantage of increasing the size of the device.

〔発明の目的〕[Purpose of the invention]

本発明は、ウェハを十分に薄肉にして電気抵抗及び熱抵
抗の低減を達成した半導体装置を容易に得ることができ
る半導体装置の製造方法を提供することをその目的とす
るものである。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can easily produce a semiconductor device that achieves reductions in electrical resistance and thermal resistance by making the wafer sufficiently thin.

〔発明の概略〕[Summary of the invention]

本発明は、ウエハを−坦透明部材からなる補強板に貼着
して薄肉にした後、補強板を除去する工程を設けたこと
によシ、電気抵抗及び熱抵抗の低減を達成した半導体装
置を容易に得ることができる半導体装置の製造方法であ
る。
The present invention provides a semiconductor device that achieves reductions in electrical resistance and thermal resistance by attaching a wafer to a reinforcing plate made of a flat transparent material to make it thinner and then removing the reinforcing plate. This is a method of manufacturing a semiconductor device that can easily obtain the following.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の実施例について図面を参照して説明する
。第1図(〜乃至同図(杓は、本発明方法を工程順に示
す説明図である。先ず、同図(A)に示す如く、所定の
素子(図示せず)を主面側に形成した厚さL1300〜
600μmのウェハJ0を用意する。素子は通常ウェハ
10の主面から10μmに達しない極めて浅い領域に形
成されている。次いで、このウェハ1oを同図(B)に
示す如く、主面側忙接着剤層1ノを介して透明部材から
なる補強板12上に貼着する。補強板12としては、例
えばガラス板を使用する。補強板12を透明部材で形成
したのは、後のスクライプ工程(ウェハの分割工程)で
位置合せをウェハ10の薄肉化の際及びその後にウェハ
JOが破壊しないよりに補強する作用を発揮できるもの
であれば良い。なお、図示を省略しているがウェハ10
の主面上には、所定の電極及び絶縁膜が形成されている
。欠に、露出したウェハ10の裏面に同図(Qに示す如
く、ラッピング等を行ない、ウェハ10を厚さり、10
〜50μmの薄肉のウェハ13tlC切削する。次に、
ウェハ13の裏面忙所定の裏面処理を施した後、同図(
lに示す如く、裏面電極14を貼着する。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an explanatory diagram showing the method of the present invention in the order of steps. First, as shown in FIG. Thickness L1300~
A 600 μm wafer J0 is prepared. The elements are usually formed in an extremely shallow region of less than 10 μm from the main surface of the wafer 10. Next, this wafer 1o is adhered onto a reinforcing plate 12 made of a transparent member via the adhesive layer 1 on the main surface side, as shown in FIG. As the reinforcing plate 12, for example, a glass plate is used. The reason why the reinforcing plate 12 is made of a transparent material is that it can strengthen the wafer JO rather than destroying it during the thinning of the wafer 10 during alignment in the subsequent scribing process (wafer dividing process) and after that. That's fine. Although not shown, the wafer 10
Predetermined electrodes and an insulating film are formed on the main surface of. As shown in the same figure (Q), wrapping or the like is performed on the exposed back side of the wafer 10 to increase the thickness of the wafer 10.
A thin wafer 13tlC of ~50 μm is cut. next,
After performing a predetermined backside treatment on the backside of the wafer 13, the same figure (
As shown in FIG. 1, the back electrode 14 is attached.

次に、同図(Qに示す如く、裏面電極14及びウェハ1
3にスクライプ処理を施し、これらを所定の素子ごとに
分割するためのスクライブ溝15を形成する。然る後、
接着剤層11t−所定の溶剤で溶かし、同図(ffiK
示す如く、各々の素子からなる半導体装置20を得る。
Next, as shown in the same figure (Q), the back electrode 14 and the wafer 1
3 are subjected to a scribing process to form scribe grooves 15 for dividing them into predetermined elements. After that,
Adhesive layer 11t - Dissolved with a specified solvent and
As shown, a semiconductor device 20 consisting of each element is obtained.

このようにこの半導体装置の製造方法によれば、ウェー
10を補強板12Vc貼着した状態で薄肉にすると共に
、スクライブ溝15を形成するので、十分に薄肉化した
ウニノリ3を容易に得ることができる。しかも、スクラ
イブ溝15の形成は、補強板12が透明部材で形成され
ているので、位置合せを正確にして容易に行うことがで
きる。この結果、ウェハJ3が十分に薄肉になっている
ので、熱抵抗及び電気抵抗を低減して信頼性の向上を図
った半導体装置2θを容易に得ることができる。
According to this semiconductor device manufacturing method, the wafer 10 is thinned with the reinforcing plate 12Vc attached and the scribe grooves 15 are formed, so it is possible to easily obtain the sea urchin laver 3 with a sufficiently thin wall. can. Furthermore, since the reinforcing plate 12 is made of a transparent material, the scribe grooves 15 can be easily formed with accurate alignment. As a result, since the wafer J3 is sufficiently thin, it is possible to easily obtain a semiconductor device 2θ with reduced thermal resistance and electrical resistance and improved reliability.

因みに、本発明方法で得られた半導体装置20は、第3
図(菊に示す如く、ウエハ13の肉厚L!が10〜50
μmで十分に薄肉になっているが、従来方法で得られた
半導体装置5は、同図(B)に示す如く、ウェハ2の肉
厚D2が150〜250μmの大きなものになっている
ことが確認されている。なお、第3図(A)、CB)中
21は絶縁膜、22は長面電極である。
Incidentally, the semiconductor device 20 obtained by the method of the present invention is
(As shown in the chrysanthemum figure, the thickness L! of the wafer 13 is 10 to 50.
Although the semiconductor device 5 obtained by the conventional method has a large wall thickness D2 of 150 to 250 μm, as shown in FIG. Confirmed. Note that in FIGS. 3(A) and CB), 21 is an insulating film, and 22 is a long electrode.

〔発明の効果〕〔Effect of the invention〕

以上説明した如く、本発明に係る半導体装置の製造方法
によれば、ウェハを十分に薄肉にして電気抵抗及び熱抵
抗の低減を達成した半導体装置を容易に得ることができ
るものである。
As explained above, according to the method of manufacturing a semiconductor device according to the present invention, it is possible to easily obtain a semiconductor device that achieves reductions in electrical resistance and thermal resistance by making the wafer sufficiently thin.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(A)乃至同図(的は、本発明方法を工程順に示
す説明図、第2図(尋#(四は、本発明の効果を示す説
明図、第3図(A)乃至同図(E)は、従来の半導体装
置の製造方法を工程順に示す説明図である。 1θ、13・・・ウェハ、11・・・接着剤層、12・
・・補強板、14・・・裏面電極、15・・・スフライ
20・・・半導体装置、21・・・絶縁膜、22・・・
電極。 出願人代理人  弁理士 鈴 江 武 彦@ 1 図
Figure 1 (A) to the same figure (Figure 2 is an explanatory diagram showing the method of the present invention in the order of steps, Figure 2 is an explanatory diagram showing the effects of the present invention, Figure 3 (A) to Figure (E) is an explanatory diagram showing a conventional method for manufacturing a semiconductor device in the order of steps. 1θ, 13... Wafer, 11... Adhesive layer, 12...
... Reinforcement plate, 14... Back electrode, 15... Spray 20... Semiconductor device, 21... Insulating film, 22...
electrode. Applicant's agent Patent attorney Takehiko Suzue @ 1 Figure

Claims (1)

【特許請求の範囲】[Claims] 所定の素子が形成されたウェハを主面側に接着剤を介し
て透明部材からなる補強板に貼着する工程と、前記ウエ
ハの露出した裏面側を所定の肉厚分だけ除去する工程と
、除去後の前記ウエハの裏面に電極を形成する工程と、
該電極及び前記ウエハを所定形状となるように一体に分
割する工程と、分割された該ウエハから前記補強板を剥
離する工程とを具備することを特徴とする半導体装置の
製造方法。
a step of attaching a wafer on which a predetermined element is formed to a reinforcing plate made of a transparent member via an adhesive on the main surface side; a step of removing the exposed back side of the wafer by a predetermined thickness; forming an electrode on the back surface of the wafer after removal;
A method for manufacturing a semiconductor device, comprising the steps of: dividing the electrode and the wafer into a predetermined shape; and peeling off the reinforcing plate from the divided wafer.
JP12301085A 1985-06-06 1985-06-06 Manufacture of semiconductor device Pending JPS61280660A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12301085A JPS61280660A (en) 1985-06-06 1985-06-06 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12301085A JPS61280660A (en) 1985-06-06 1985-06-06 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS61280660A true JPS61280660A (en) 1986-12-11

Family

ID=14850010

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12301085A Pending JPS61280660A (en) 1985-06-06 1985-06-06 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61280660A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5256562A (en) * 1990-12-31 1993-10-26 Kopin Corporation Method for manufacturing a semiconductor device using a circuit transfer film
US5258325A (en) * 1990-12-31 1993-11-02 Kopin Corporation Method for manufacturing a semiconductor device using a circuit transfer film
US5757445A (en) * 1990-12-31 1998-05-26 Kopin Corporation Single crystal silicon tiles for display panels
JP2000077518A (en) * 1998-08-25 2000-03-14 Commiss Energ Atom Physical insulating process of substrate base-board region
JP2002544669A (en) * 1999-05-07 2002-12-24 ギーゼッケ ウント デフリエント ゲーエムベーハー How to handle thin chips for incorporation into smart cards
US6593978B2 (en) 1990-12-31 2003-07-15 Kopin Corporation Method for manufacturing active matrix liquid crystal displays
JP2016063092A (en) * 2014-09-18 2016-04-25 芝浦メカトロニクス株式会社 Laminate manufacturing device, laminate, separation device and laminate manufacturing method

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5256562A (en) * 1990-12-31 1993-10-26 Kopin Corporation Method for manufacturing a semiconductor device using a circuit transfer film
US5258325A (en) * 1990-12-31 1993-11-02 Kopin Corporation Method for manufacturing a semiconductor device using a circuit transfer film
US5757445A (en) * 1990-12-31 1998-05-26 Kopin Corporation Single crystal silicon tiles for display panels
US6486929B1 (en) 1990-12-31 2002-11-26 Kopin Corporation Bonded layer semiconductor device
US6593978B2 (en) 1990-12-31 2003-07-15 Kopin Corporation Method for manufacturing active matrix liquid crystal displays
US6919935B2 (en) 1990-12-31 2005-07-19 Kopin Corporation Method of forming an active matrix display
JP2000077518A (en) * 1998-08-25 2000-03-14 Commiss Energ Atom Physical insulating process of substrate base-board region
JP2002544669A (en) * 1999-05-07 2002-12-24 ギーゼッケ ウント デフリエント ゲーエムベーハー How to handle thin chips for incorporation into smart cards
JP2016063092A (en) * 2014-09-18 2016-04-25 芝浦メカトロニクス株式会社 Laminate manufacturing device, laminate, separation device and laminate manufacturing method

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