JPS6211752B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a storage control device, particularly a data processing system comprising a plurality of data processing devices and a plurality of storage units connected to them.
The present invention relates to a storage control device that controls bank interleaving between each data processing device and a storage unit.

Generally, a storage control device that performs interleave control generates a memory address for driving a storage device in response to an access address supplied from an access device such as a central processing unit or a channel.

FIG. 1 is a system configuration diagram including the present invention and a conventional storage control device, in which central processing units CPUA,
The storage controller MC receives the access address AA from the access device ACD such as CPUB, channels CHA, CHB, etc., and generates the memory address MA to drive the storage device MEMD consisting of the storage units MEMA and MEMB. .

Here, the storage device MEMD is arranged as shown in FIG. 2 between the storage space and the memory address MA.

In other words, memory address MA is unit address MEM indicating storage units MEMA and MEMB.
It consists of a module address MD, a module address MDAD, and a bank address BK, and each memory location is a unit address.
MEM0, MEM1, module address MD0~
MD3, module address MDAD0 to MDAD
3. Indicate individually with bank addresses BK0 to BK3〓〓〓〓〓
It can be done.

That is, the storage device MEMD shown in FIG. 2 is divided into a plurality of storage modules, and the storage modules are also divided into a plurality of banks.

The banks are configured so that each bank can be accessed independently of the other banks, and the central processing units CPUA, CPUB, channels CHA, CHB, etc. can access each bank in parallel at the same time.

Conventional storage control devices are equipped with a means for checking whether the physical storage module to be accessed is valid in response to memory access from a data processing device. A channel or the like accesses several banks simultaneously in parallel, and memory failures are handled by switching the memory in which the failure occurs to spare memory either programmatically or by hardware.

However, in a system configured as described above, there is no particular problem with normal memory access, but when hardware (formware) uses memory, accesses may concentrate on a specific storage unit. However, there were drawbacks that degraded the performance of the system. In other words, in the normal memory access mentioned above, there is no continuity in the physical module space due to the basing and segmentation methods, so accesses are not concentrated on a specific storage module, but the hardware (firmware)
Areas used by hardware and software such as page tables and segment tables (logical address to real address conversion tables) are accessed using absolute addresses.

Further, the above areas are usually addressed lower in the absolute address space.

Addressing (absolute addresses) in conventional storage devices was continuous addressing within a module, so addresses corresponding to the module capacity were assigned to a specific module starting from address 0.

In cases such as the above, when software or hardware uses the above memory area, absolute address access is performed, so accesses may concentrate on a specific module. Accesses were concentrated on the memory modules, and the frequency of accesses among storage modules became uneven, resulting in a decrease in memory access efficiency and a deterioration in system performance.

On the other hand, in the case of a storage module, even if a failure occurs, it is necessary to continue processing operations without stopping system processing for a long time. Memory is a particularly important device in a data processing system, and in the event of a failure, it is essential for the data processing system to switch the affected memory to spare memory either by software or hardware. . Conventionally, as such a memory switching method, memory switching was performed by assigning a variable device number to each module and rewriting this number.
For this reason, conventional devices have included means for converting the logical storage module number from the access device into an actual memory storage module number and checking means for checking whether the accessed storage module is valid.

In a system configured in this way, memory accesses from software are usually performed using paging and segmentation methods, and there is no continuity in the physical module space, so accesses are not concentrated on a specific storage module, but memory accesses from the hardware (farm When software such as software uses memory, accesses are made using absolute addresses, so accesses may concentrate on a specific physical storage module.

In this case, in a system configured with a plurality of memory units, accesses are concentrated on a specific memory unit, which has the disadvantage of degrading system performance.

A conventional storage control device will be described below with reference to the drawings. Figure 3 is a block diagram showing an example of the conventional technology, in which the access address register AAR
The upper bits _b5 to _b2 of the access address AA stored in the memory address register MAR are exchanged in the selection circuit SEL by the selection signal S generated in response to the ON/OFF operation of the switch circuit SW, and the memory address MA is stored in the memory address register MAR. The upper bits are stored as a group of upper bits _B5 to _B2 . The lower bit group _b1 to _b0 of the access address AA is stored as the lower bit group _B1 to _B0 of the memory address MA in the memory address register.
Stored in MAR.

〓〓〓〓〓
Here, upper bit _B5 is the unit address
The upper bit B ₄ becomes the module address MD, the upper bits B ₃ and B ₂ become the intra-module address MDAD, and the lower bits B ₁ and B ₀ become the bank address BK.

The selection signal S from the switch circuit SW is fixedly set to "0" and "1" by software or manually to select the selection circuit SEL.

When the selection signal S is set to "0", the flow of addresses and the address map in the storage device become as shown in FIGS. 4a and 4b.

Also, when the selection signal S is set to “1”, the fifth
It will look like Figures a and b.

Assuming that access is performed continuously from 00 to 0F in both, time charts of the operations are shown in FIGS. 6 and 7.

When the selection signal S is set to "0" and the settings are as shown in Figure 4 a and b, accesses 04 and 0 are made as shown in Figure 6.
Since 8.0C is in use, the bank will be kept waiting. Therefore, read data READ DATA 0
Time for F to return to the access device (access time)
The disadvantage is that it is slow.

Next, the selection signal S is set to "1", and FIGS.
By doing this, as shown in FIG. 1, there is no need to wait for the bank, so the read data READ DATA returns quickly.

As mentioned above, in order to use the storage device efficiently, it is necessary to equalize access to banks.

However, considering the address map, if the selection signal S is "0" in the storage module.
When , tasks A, B, C, and D, including programs or data, are mapped as shown in Figure 5.
When the selection signal S is "1", task A is assigned to A ₀ and A ₁ , task B is assigned to tasks B ₀ and B _{1, task C is assigned to tasks C 0 and C 1} , and task D is assigned to tasks C ₀ and C ₁ , as shown in FIG.
It is distributed and mapped to D ₀ and D ₁ .

That is, in FIG. 8, each task is separated for each module, but in FIG. 9, these tasks are mapped in a distributed manner.

At this time, memory address MEM0,
If the module indicated by the module address MD0 fails, task A in FIG. 8 becomes unusable and the corresponding program or task can be taken down, but in FIG. One program or task must be brought down.

Therefore, even if only the module indicated by memory address MEM0 and module address MD0 fails, the contents of the module at memory address MEM1 will also become meaningless, and essentially two modules will go down.

As described above, in the conventional configuration, whether or not to decentralize the addresses is fixedly selected for all modules, and either method has the above-mentioned drawbacks.

An object of the present invention is to provide a storage control device that solves both of the above-mentioned drawbacks, namely, the centralization of access and the increase in the number of down units.

In other words, an object of the present invention is to prevent the concentration of access frequency on a specific storage module of a specific storage unit, and to equalize the access frequency among storage units, thereby increasing the efficiency of memory access and improving system performance. In addition, even if a failure occurs in a memory module, simply disconnecting the affected memory module will not unnecessarily reduce the memory capacity easily and with a small amount of hardware, and will not affect other memory modules. Another object of the present invention is to provide a storage control device which is simple and realized with a small amount of metal material so that interleaving between storage units can be arbitrarily set for each storage module, so that the ratio of reliability and performance can be arbitrarily selected.

The storage control device of the present invention includes an access address register that stores an access address supplied from an access device, and a validity bit and an interleave control bit provided for each storage module, which are specified by the upper bits of the access address. a table stored in a memory location; an AND circuit that generates a selection signal in accordance with the read validity bit and the interleave control bit; and a bit exchange of a group of upper bits of the access address in accordance with the selection signal. a selection circuit that generates a group of upper bits of a memory address by performing a selection circuit, and a memory that stores a memory address of a storage device that is interleaved and controlled by a group of upper bits of the memory address and a group of lower bits of the access address. 〓〓
It consists of an address register.

In other words, the storage control device of the present invention is a storage control device that controls access from a data processing device to a storage device that includes a plurality of storage units each consisting of a plurality of storage modules, and which uses a validity bit to indicate whether or not a storage module is valid. means for holding an interleave control bit for controlling interleaving for each storage module; a first address register for receiving an address from the data processing device; and a second address register for sending an address to the storage device. a register, an AND circuit that ANDs the validity indicating bit and the interleave control bit for any storage module based on the access address from the data processing device; It is configured to include a selector circuit that exchanges a part of the address storage module number and a part of the address in the module.

That is, the storage control device of the present invention is a storage control device that controls access from a data processing device to a storage unit consisting of a plurality of storage modules that are divided into a plurality of banks and interleaved. A circuit that holds a validity bit indicating whether or not the data is stored, a circuit that holds an interleave control bit that controls interleaving for each storage module, and a circuit that holds a validity indication bit that controls interleaving for each storage module, and and an interleave control bit for a plurality of storage modules; and an AND circuit that performs an AND operation on a plurality of storage modules, and uses the output of the AND circuit to exchange a part of the storage module number and a part of the address in the module of the access address from the data processing device. The configuration includes a selector circuit that performs the following operations.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 10 is a block diagram showing one embodiment of the present invention. Tables TABL0 and TABL1 are tables in which module validity bits and interleave control bits are stored, and these tables are set in advance by software or hardware. Assume that the setting values are validity bits V ₀ -V ₃ =1 and interleave control bits I ₀ -I ₃ =0. At this time, no matter which access address AA is accessed, the output of the AND circuit AND is "0", so the selection circuit SEL selects the 0 side, and the flow of address bits and the addresses in the memory module are the same as before. It will look like Figure 4 a and b.

In this case, the frequently accessed access address
If AA is 00-0F, access is
It will be concentrated on MEM0 and cannot be accessed effectively.

Next, the contents of the table are V ₀ ~ V ₃ = 1, I ₀ ~ _{I 3} = 1
Assuming that it is set to , no matter which access address AA is accessed, the AND circuit
Since the output of AND is "1", the selection circuit SEL selects the 1 side, and the flow of address bits and the address in the storage module are the same as in the conventional case, as shown in Figures 5a and b.
become that way.

In this case, the frequently accessed access addresses AA, 00 to 0F, correspond to the memory unit MEM0.
It is distributed in MEM1. Therefore, access to both storage units will be equalized.

Furthermore, as another example, V ₀ ~V ₃ = 1, I ₃ =
A case where the table is set to 0, I ₀ to I ₂ =1 will be explained. When the access address AA from the access device is 00 to 1F, V ₀ , V ₂ , I ₀ , I ₂
=1, the output of the AND circuit AND becomes "1", the selection circuit SEL selects the "1" side, and the flow of address bits becomes as shown by the solid line in FIG. 11a. Also, when the access address AA is between 20 and 3F,
Since I ₃ =0, the output of the AND circuit AND becomes 0, and the selection circuit SEL selects the "0" side, and the flow of address bits becomes as shown by the dotted line in FIG. 11a.

As can be seen from this example, the address map is as shown in FIG. 11b, and addressing works differently depending on the module. That is,
For modules that are frequently accessed, the address map is distributed between modules, and for other modules, the address map is made continuous within the module.
The access frequency was made uniform and the number of down units was also reduced. However, the above I ₃ =0
In the case of FIG. 11a and b above, the access address AA is 04~07, 0C~0F, 14~
17 and 1C to 1F and access address AA is 2
For 0 to 2F, module MD0 of MEM1
As shown in Figure 12, 20th to 2F of access address AA cannot be used due to duplication.
Become.

Also, when I ₁ =0, addresses overlap in MD0 of MEM1 as described above, and even when I ₀ =0 or I ₂ =0, addresses overlap in MD1 of MEM0. This also applies when V ₀ to V ₃ are 0.

In other words, it has a drawback in terms of effective use of main memory. However, it goes without saying that this is not a decisive drawback of the present invention. In other words, when there are a large number of modules as shown in FIG. 13, it is possible to use the main memory effectively by setting the interleave control bits so that addresses do not overlap on the modules.

FIG. 14 is a block diagram showing another improved embodiment of the present invention.

In FIG. 14, a module conversion table is provided.

Tables TABL0' and TABL1' store module conversion information, validity bits, and interleave control bits.

First, an example will be explained in which the interleave control bits are all "0" as shown in FIGS. 15a and 15b.

For example, when the access address AA accesses the address 00 ₍₁₆₎ , the address b5 is 0, so the 0 side of the table TABL is selected and its contents "1110" and "0010" are output.

Next, selection circuits SEL0 and SEL1 select address b4.
Since the address b2 is "0", both select the 0 side, and the outputs of the selection circuits SEL0 and SEL1 both output "11". Also, 0 is 1 in the output of table TABL.
Since there are more than one, the output of the logical product circuit AND is “0”
Therefore, the selection circuit SEL2 selects the 0 side. Therefore, the output of the selection circuit SEL2 is the output "11" of the selection circuit SEL1, which becomes the address to the storage device as a module address. For the intra-module address and bank address, "0000" is the address to the storage device. Therefore, address 00 ₍₁₆₎ from the access device is accessed to module MD=3, address within module=0, and bank address=0. The address from the access device is thus converted into a module number and sent to the storage device.

Next, when the validity bit and the interleave control bit are all "1", the results are as shown in FIGS. 16a and 16b.

When access is made to address 00 ₍₁₆₎ of access address AA, address b5 is 0, so the 0 side of table TABL1 is selected and its contents "0111" and "1011" are output.

Next, selection circuits SEL0 and SEL1 select address b2
Since and b4 are 0, both select the 0 side, and the outputs of the selection circuits SEL0 and SEL1 both output "01". Also, since all the inputs of the logical product circuit AND are "1", the output is "1", and the selection circuit
For SEL2, the 1 side is selected. Therefore, the selection circuit
The output of SEL2 is the output "01" of the selection circuit SEL0 as it is, and becomes the module address. Also,
b4 and b3 become addresses within the module and become addresses to the storage device.

Next, if the address 04 ₍₁₆₎ is accessed, the output of the table TABL', the output of the selection circuit SEL1, and the output of the AND circuit AND are the same as above, but b2 becomes "1", so it is selected. The “1” side is selected for circuit SEL0 and the table
The output "10" of TABL' is sent to the selection circuit SEL2. The selection circuit SEL2 directly uses "10" as a module address to address the storage device.
As described above, when the address b2 bit is 0, the contents of the table TABL0' are sent to the storage device, and when the b2 bit is ``1'', the contents of the table TABL1' are sent to the storage device.

Next, the case where the interleave control bit of an arbitrary module is "0" will be explained with reference to FIGS. 17a and 17b.

In this case, when b5 of access address AA is 0, the effect is similar to that in FIGS. 16a and b, and when access address b5 is 1, the effect is similar to that in FIGS. 15a and b.

By providing the module conversion table in this way, it is possible to make address mapping more variable, and the usability of the software can be made easier.

Figures 18 to 20 are figures 15a, b to 1.
This figure shows a task map corresponding to Figures 7a and 7b, in which addresses are not distributed for modules that are down, and addresses are not distributed between modules in order to improve the efficiency of interleaving such as absolute addresses. At this time,
18 to 20 or some other task map.

Since the storage control device of the present invention can freely change the address map by adding a table, it has the advantage of preventing concentration of access frequencies and reducing the effects of module downtime.

[Brief explanation of the drawing]

FIG. 1 is a system configuration diagram including the present invention and a conventional storage control device, FIG. 2 is an address allocation diagram showing the relationship between memory addresses and storage spaces in the storage device shown in FIG. A block diagram showing an example, FIGS. 4a and 4b, is an address relationship diagram and an address map in the first address relationship between the access address and the memory address when the selection signal is in the first state in the conventional example shown in FIG. , FIGS. 5a and 5b are an address relationship diagram and an address map in the second address relationship between the access address and the memory address when the selection signal is in the second state in the conventional example shown in FIG. 3, and FIG. Time chart 7 for explaining the first access state between the access device and the storage device in the first address relationship shown in FIGS. 4a and 4b.
The figure is a time chart for explaining the first access state between the access device and the storage device in the case of the second address relationship shown in FIGS. 5a and b, and FIG. 8 is shown in FIGS. 4a and b. FIG. 9 is a task map for explaining the first task allocation state in the storage device when the first address relationship exists, and FIG. A task map for explaining the task allocation state, FIG. 10 is a block diagram showing an embodiment of the present invention, and FIGS. 11a and 11b show the relationship between access addresses and memory addresses in the embodiment shown in FIG. 10. Address relationship diagram and address map, FIG. 12 is a task map for explaining the first task allocation state in the storage device when the address relationships shown in FIGS.
The figure shows a task map for explaining the second task allocation state when the present invention is applied by increasing the number of modules of the storage device, FIG. 14 is a block diagram showing another embodiment of the present invention, and FIG. 15 a and b are the 14th
The table storage state and address map when the table state in the embodiment shown in the figure is the first table state, FIGS. 16a and b are the table state when the table state in the embodiment shown in FIG. Table storage status and address map, No. 17
Figures a and b show the table storage state and address map when the table state is the third table state in the embodiment shown in Fig. 14, and Fig. 18 shows the first table storage state shown in Figs. 15 a and b. 19 is a task map for explaining the first task allocation state when the second table is stored in the state shown in FIGS. 16a and 16b, FIG. 20 is a task map for explaining the first task allocation state in the third table storage state shown in FIGS. 17a and 17b. ACD...Access device, CPUA, CPUB...Central processing unit, CHA, CHB...Channel, MC...
...Storage control device, MEMD...Storage device,
MEMA, MEMB...memory unit, SW...switch circuit, SEL, SEL0, SEL1, SEL2...selection circuit, AAR...access address register,
MAR...Memory address register, TABL,
TABL0, TABL1, TABL0', TABL1'...
Table, AND, AND′...AND circuit, AA...
...Access address, MA...Memory address,
MEM, MEM0, MEM1...Unit address, MD, MD0, MD1...Module address, MDAD, MDAD0-MDAD3...Address within module, BK, BK0-BK3...Bank address, S, S', S''... …Selection signal, READ
DATA...Read data, _V1 , _V2 , _V3 , _V4 ...Validity display bit, _I1 , _I2 , _I3 , _I4 ...Interleave control bit, A, B, C, D, E ,F,G,
H, _A0 , _B0 , C0, _D0 , A1, _B1 , _C1 , _D1 ...Task, MN0 to _MN3 ...Module number _. 〓〓〓〓〓

Claims (1)

[Claims] 1. An access address register for storing an access address supplied from an access device for a storage device having a plurality of storage units each consisting of a plurality of interleaved storage modules, and a validity bit and interleave control provided for each storage module. a table for storing bits in a storage location indicated by the storage module designation of the upper bits of the access address; and one storage module for each storage unit from the storage table based on the storage module designation of the upper bits of the access address. an AND circuit that generates a selection signal in response to the validity bits and the interleave control bits selected and read out; A selection circuit that performs bit exchange with a part of the lower bit group to generate the upper bit group and lower bit group of the memory address, and the upper bit group of the memory address and the lower bit group of the access address are interleaved and controlled. 1. A storage control device comprising: a memory address register for storing a memory address of a storage device.