JP2001034534A - Disk system and its cache system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability of data in a cache memory without any deterioration in system performance. SOLUTION: For a disk part 1 which stores data, this disk system is equipped with an MPU 22 which controls data access to the disk part 1 and cache memory parts (23-1) and (23-2) having cache memories wherein data are temporarily held and handles access made by a host computer. A data transfer path (27) is provided which interconnects the cache memory parts (23-1) and (23-2) and data are transferred between the cache memory parts (23-1) and (23-2) through the data transfer path (27).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk system, and more particularly to a disk system suitable for accessing a disk employing a disk array device and its cache system.

[0002]

2. Description of the Related Art Conventionally, a disk system usually has a cache memory. In order to maintain the data in the cache memory, it is conceivable to duplicate the cache memory.

However, when the cache memories are duplicated, there arises a problem that the performance is deteriorated, for example, it is not possible to promptly respond to a request from the host side for the process of equalizing the data of the two cache memories.

[0004]

When a controller is duplicated and a disk and a duplicated cache memory are managed, two controllers perform predetermined processing for the same data in the two cache memories. It is necessary to provide a procedure, which causes a problem that processing becomes complicated.

The present invention has been made to solve the problems of the conventional disk system, and has as its object to improve the reliability of data written in a cache memory without deteriorating the performance of the system. To provide a disk system and a cache system for the disk system, which can improve the performance.

[0006]

According to the present invention, there is provided a disk system comprising: a disk unit for storing data; a control unit for controlling data access to the disk unit; and a cache having a cache memory for temporarily storing data. In a disk system corresponding to access by a host computer, a plurality of sets with a memory unit are provided, and a data transfer path connecting only the cache memory units of each set to each other is provided in each of the cache memory units of the set. And control means for performing data transfer between the cache memory units via the data transfer path. As a result, data transfer is performed between the cache memory units of each set via the dedicated data transfer path, and the data path used for accessing the disk unit is not used for data matching. Further, the control unit does not intervene in data matching.

In the disk system according to the present invention,
The control means transfers data to another cache memory unit via the data transfer path when writing data to the cache memory of the cache memory unit. As a result, when writing data to the cache memory of the cache memory unit, data consistency between the cache memory units is achieved.

In the disk system according to the present invention,
A sub-cache memory unit provided corresponding to each of the sets of cache memory units, the cache memory temporarily storing data, and the data stored in the set of cache memory units and the sub-cache memory unit. A sub-cache memory unit having sub-cache memory unit control means for matching data is provided. This makes it possible to duplicate data in the sub-cache memory unit for each set.

Further, in the disk system according to the present invention,
A dedicated path for connecting only between the cache memory unit and the sub cache memory unit is provided, and the sub cache memory unit control means controls the data held in the cache memory unit of the set and the sub path via the dedicated path. It is characterized by matching the data with the cache memory unit. As a result, data is transferred between the cache memory unit and the sub-cache memory unit of each set via the dedicated path, and the data path used for accessing the disk unit is not used for data matching.

[0010] In the disk system according to the present invention,
Each set of control units performs control by dividing a different data area of the disk unit, and when a failure occurs in any of the control units, the control unit is replaced by any of the other control units. Thereby, load distribution of the control unit is achieved.

Further, in the disk system according to the present invention,
A cache table provided in the cache memory unit, a memory table for managing information of write permission / prohibition based on an access state and a memory table for managing the information based on an access situation, and the control means manages the information of the memory table and controls the information via a data transfer path. Permission / non-permission information is transmitted based on information in the memory table in response to incoming data transfer request information. Thereby, the timing of data matching between the cache memory units is controlled according to the access status to the cache memory units.

Further, a cache system of a disk system according to the present invention is provided with a first unit having a control unit for controlling data access to the disk unit and a cache memory for temporarily storing data for a disk unit for storing data. A second cache memory unit having a cache memory for temporarily storing data, a first cache memory unit, and a second cache in a cache system of a disk system corresponding to an access of a host computer; A data transfer path interconnecting only the memory units, control means provided in the first cache memory unit, for transferring data to the second cache memory unit via the data transfer path, Provided in the cache memory unit, via the data transfer path. Characterized by comprising a first control means for performing data transfer to the cache memory unit.
As a result, in the first and second cache memory units, data transfer is performed via the dedicated data transfer path, and the data path used for accessing the disk unit is not used for data matching. Further, the control unit does not intervene in data matching.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A disk system according to the present invention will be described below with reference to the accompanying drawings. In each drawing, the same components are denoted by the same reference numerals, and redundant description will be omitted. FIG. 1 shows a first embodiment of the disk system of the present invention. In this embodiment, a disk array composed of a plurality of disk devices is employed for the disk unit 1, and here, arrays # 0 to # 5 are used.
Is arranged.

A controller 2 for accessing the disk unit 1 in response to a request from the host computer is provided. The controller 2 has a host interface (HOST) for transmitting and receiving data to and from a host computer.
I / F) 21, microprocessor unit (MPU) 2
2. Cache memory unit 23, disk controllers 24-1 to 24 that are squeegee protocol controllers (SPCs) connected to a predetermined disk in disk unit 1.
-3 is provided. The host interface 21, the microprocessor unit 22, the cache memory unit 23, and the disk controllers 24-1 to 24-3 are a bus (for example, a PCI bus) that is a common data transfer path.
25.

Another way of expressing the above embodiment is as shown in FIG. That is, the host interface 21, the microprocessor unit 22, the cache memory unit 23, and the disk input / output units 24a-1 to 24a-2.
4a-6 are connected to the common bus 25. Here, in FIG. 1, the Scourge Protocol Controller (SPC) is replaced with the disk controllers 24-1 to 24-3.
However, since each of the disk devices 1a-1 to 1a-6 is individually connected, the disk input / output units 24a-1 to 24a-
6 and the disk controller 24-
1 to 24-3 and the disk input / output units 24a-1 to 24a-
No. 6 has the same function of accessing the disk device.

FIG. 2 shows the internal configuration of the microprocessor section 22. The microprocessor unit 22 has a configuration in which the ROM 12 and the RAM 13 are connected to the microprocessor 11, and the microprocessor 11 uses a program in the ROM 12 to use the RAM 13 as a working memory.
Based on instructions from the host computer received via the host interface 21, the disk input / output units 24a-1 to 24a-1
24a-6, and controls the cache memory unit 23. As described above, the microprocessor unit 22
The control unit controls data access to the disk unit.

FIG. 3 shows the configuration of the cache memory unit 23. The cache memory unit 23 includes a DRAM 31 for holding cache data, a DRAM control unit 32, a data path switching control unit 33, a mirroring copy interface 34, and a PCI bus interface 35.

The above-mentioned DRAM control unit 32 includes a DRAM 3
1 has a function of writing or reading data to / from
The data path switching control unit 33 includes the microprocessor unit 2
2 to control the DRAM control unit 32 to store or read data, transfer the data via the mirroring copy interface 34 when necessary, and give an interrupt signal to the microprocessor unit 22 to notify the microprocessor unit 22 of the end of the data transfer. I do. Mirroring copy interface 3
4 is connected to another cache memory unit. The other cache memory units have the same configuration as the cache memory unit 23. The PCI bus interface 35 transmits and receives data via the bus 25 shown in FIGS.

The operation of the cache memory unit 23 configured as described above will be described. When the host computer issues an instruction to write data to the disk unit 1, the instruction is sent to the microprocessor unit 2 via the host interface 21.
2, the disk controllers 24-1 to 24-
The data is given to a predetermined disk controller in 3 and writing to the disk unit 1 is performed. Further, this data is given to the cache memory unit 23 and held.

At this time, the data path switching control unit 33 of the cache memory unit 23
And writes the data into the DRAM 31 by controlling the DRAM control unit 32 (FIG. 3). Then, the data path switching control unit 33 sends a data transfer instruction via the mirroring copy interface 34 to a storage address (write cache address).
And a timer, for example. When the timer expires, the data path switching control unit 33 executes data transfer via the mirroring copy interface 34 based on the set instruction (FIG. 3). It is provided to the processor unit 22 to notify the end of the data transfer.

Since the other cache memory units have the same configuration as the cache memory unit 23 of FIG. 3, this operation will be described using the same numbers as those of FIG. The mirroring copy interface 34 of the other cache memory unit receives the incoming data together with the storage address and sends it to the data path switching control unit 33. The data path switching control section 33
It controls the RAM control unit 32 to write data to the DRAM 31.

FIG. 4 shows the data path switching control unit 33 shown in FIG.
14 shows a cache memory unit including a data path switching control unit 33A that performs an operation different from that of FIG. This cache memory unit is provided with a data path switching control unit 33A except that
It has the same configuration as the cache memory unit of FIG.
This cache memory unit operates as follows.

When a host computer issues an instruction to write data to the disk unit 1, the microprocessor unit 22 fetches the instruction via the host interface 21 and sends the data to a predetermined disk controller among the disk controllers 24-1 to 24-3. Give disk part 1
Is written. This data is shown in FIG.
To the cache memory unit 23 shown in FIG.

At this time, the data path switching control unit 33A of the cache memory unit 23
5 receives the data and the write command through the DRAM
The data is written to the DRAM 31 by controlling the control unit 32. In parallel with this, the data path switching control unit 33 performs data transfer via the mirroring copy interface 34 (FIG. 4). A signal is given to the microprocessor section 22 to notify the end of the data transfer. With such a configuration, it is possible to quickly duplicate cache data.

Next, a controller 2A according to a second embodiment of the controller 2 is shown in FIG. In this embodiment, two cache memory units 23 and 23A are provided, these are connected to a bus 25, and are connected to each other by a dedicated data transfer path 26. The cache memory unit 23 is assumed to be the cache memory unit of FIG. 3 or FIG. 4, and the cache memory unit 23A is assumed to be another cache memory unit described in FIG. 3 or FIG. The cache memory unit 23A functions as a sub-cache memory unit that assists the cache memory unit 23.

When data is written to the cache memory unit 23, the data is written to the same address of the cache memory unit 23A as described with reference to FIG. 3 or FIG. Then, the microprocessor unit 22 operates using the cache memory unit 23 in normal times, and operates using the cache memory unit 23A when a failure occurs in the cache memory unit 23. That is, the cache memory unit 23A is used for backup.

The following other methods of use can also be adopted. As a method for the cache memory unit 23 to transfer data to the cache memory unit 23A, the method shown in FIG. 4 is used. Then, the microprocessor unit 22 writes the data in the cache memory unit 23 and reads the data by accessing the cache memory unit 23A. By performing the operation as described above, the data in the cache memory unit 23 and the data in the cache memory unit 23A can be made the same, the data can be maintained, and the data writing and the data reading can be performed in parallel. Processing capacity can be improved.

FIG. 6 shows a second embodiment of the disk system according to the present invention. In this embodiment, the disk unit 1 is controlled by the controllers 2-1 and 2-2 having the same configuration.
To respond to requests from the host computer. Then, each controller 2-1 and 2-
2 is connected by the data transfer path 27 between the cache memory units 23-1 and 23-2.
1 and 23-2 are made the same. The configuration shown in FIG. 3 or FIG. 4 is employed as the cache memory units 23-1 and 23-2.

Then, the controllers 2-1 and 2-2
Each can be configured to operate independently based on a request from the host computer. Therefore, between the cache memory units 23-1 and 23-2, data is transferred to each other, and data is made identical. According to this embodiment, the processing capability of the system can be improved. As another operation mode, the controller 2
It is assumed that -1 is the current use and the controller 2-2 is the spare. When a failure occurs in the controller 2-1, the controller 2-2 responds to a request from the host computer. The host computer gives an instruction to the microprocessor unit 22-2 via the host interface 21-2 to switch between the working mode and the standby mode.

FIG. 7 shows a third embodiment of the disk system according to the present invention. In this embodiment, in the embodiment shown in FIG. 6, the controller 2-1 is provided with a sub-cache memory unit 23B-1, and the controller 2-2 is provided with a sub-cache memory unit 23B-2. The cache memory units 23-1 and 23-2 and the sub-cache memory units 23B-1 and 23B-2 have the same configuration, and pass a data transfer path between the sub-cache memory unit 23B-1 and the sub-cache memory unit 23B-2. 2
7B, the sub-cache memory unit 23B-
1, the data held in 23B-2 are made the same. The configuration shown in FIG. 3 or FIG. 4 is adopted as the above sub-cache memory units 23B-1 and 23B-2.

The cache memory unit 23-1 and the sub cache memory unit 23B-1 divide the area of the disk unit 1 and hold data. For example, the cache memory unit 23-1 holds the data of the arrays # 0 to # 2, and stores the data of the arrays # 3 and # 4 in the sub-cache memory unit 23B-
1 holds. Similarly, the cache memory unit 23-2 holds the data of the arrays # 0 to # 2, and stores the data of the arrays # 3 and # 4.
Is stored in the sub-cache memory unit 23B-2.

The operation mode in this embodiment is shown in FIG.
One of the two types can be adopted as in the system shown in FIG. That is, in the first embodiment, the controller 2-
1 and 2-2 operate independently on the basis of a request from a host computer. In the second embodiment, the controller 2-1 is used as an active device and the controller 2-2 is used as a standby device. It is.

FIG. 8 shows a disk system according to a fourth embodiment of the present invention. In this embodiment, the cache memory unit 23-1 and the sub-cache memory unit 23B-1 are further connected to each other by a dedicated data transfer path 26-1 in the embodiment shown in FIG. -2 and sub cache memory unit 23B-
The two are connected by a dedicated data transfer path 26-2.

This embodiment corresponds to a configuration in which two controllers 2A according to the second embodiment shown in FIG. 5 are provided. Further, the cache memory unit 23-1 and the cache memory unit 23-2 are connected by the data transfer path 27, and the data held in the cache memory units 23-1 and 23-2 are made identical. Therefore, controller 2
A-1 and 2A-2 have backup cache memory units 23B-1 and 23B-2, respectively. The operation mode of each of the controllers 2A-1 and 2A-2 is the same as that of the embodiment of FIG. The operation mode between the controllers 2A-1 and 2A-2 is the same as the operation mode in FIG.

Another embodiment of the cache memory unit will be described. When two cache memory units are used in parallel, the following configuration can be used to preserve the stored data. That is, the DRAM 31
In addition, a memory table as shown in FIG. 9 is provided, and in response to a data transfer request from the other cache memory,
The data path switching control unit 33 (33A) gives permission / non-permission by referring to the memory table. The memory table shown in FIG. 9 is for managing the data area of the DRAM 31 by dividing the data area into a plurality of blocks having a predetermined capacity.
A flag (prohibition = 1, permission = 0) which is information of permission of writing is provided corresponding to each block. This flag has an initial value of “0” and is set to “1” when data is read, for example, when data is partially read and further reading may occur, and It is reset to "0" when the possibility disappears. Then, the data path switching control unit 33 (33A)
11 operates according to the procedure shown in FIG.

First, a data transfer request and a cache write address arrive from the other cache memory unit via the data transfer path (FIG. 11), and this is transferred to the data path switching control unit 33 (33A) via the mirroring copy interface 34. Is received (S1). Therefore, the data path switching control unit 33 (33A) refers to the corresponding flag in the memory table shown in FIG. 9 (FIG. 11 and S2) and detects whether the flag is “1” or “0” (S3). here,
If the flag is "0", the data transfer permission is returned (FIG. 11 and S4), and if the flag is "1", the data transfer non-permission is returned (FIG. 11 and S5). As a result, two cache memory units are used in parallel,
Rewriting can be prevented when there is a possibility of reading, and it is not necessary to access the disk unit again, so that the performance of the system can be improved.

[0037]

As described above, according to the disk system of the present invention, a control unit for controlling data access to the disk unit and a cache memory for temporarily storing data are provided for the disk unit for storing data. In the disk system corresponding to the access of the host computer, a plurality of sets with the provided cache memory unit are provided, and a data transfer path for interconnecting only the respective set of cache memory units, And control means for performing data transfer between the cache memory units via the data transfer path, so that data transfer is performed between the respective sets of cache memory units via the dedicated data transfer path. The data path used to access the disk unit is used for data matching. Since there is no possible to realize an efficient system. In addition, since the control unit does not intervene in data matching, load distribution is achieved.

Further, according to the cache system of the disk system of the present invention, a control unit for controlling data access to the disk unit and a cache memory for temporarily storing data are provided for the disk unit for storing data. A first cache memory unit, a second cache memory unit having a cache memory for temporarily storing data, and a second cache memory unit having a cache memory for temporarily storing data; A data transfer path for interconnecting only two cache memory units, a control unit provided in the first cache memory unit, and performing data transfer to the second cache memory unit via the data transfer path; Provided in the second cache memory unit,
Control means for transferring data to the first cache memory unit via the data transfer path, so that data transfer is performed via a dedicated data transfer path between each set of cache memory units, Since the data path used for accessing the section is not used for data matching, an efficient system can be realized.
In addition, since the control unit does not intervene in data matching, load distribution is achieved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a first embodiment of a disk system according to the present invention.

FIG. 2 is a configuration diagram showing an embodiment of a controller in the disk system according to the present invention.

FIG. 3 is a configuration diagram showing a first embodiment of a cache memory unit in the disk system according to the present invention.

FIG. 4 is a configuration diagram showing a second embodiment of the cache memory unit in the disk system according to the present invention.

FIG. 5 is a configuration diagram showing a second embodiment of the controller in the disk system according to the present invention.

FIG. 6 is a configuration diagram showing a second embodiment of the disk system according to the present invention.

FIG. 7 is a configuration diagram showing a third embodiment of the disk system according to the present invention.

FIG. 8 is a configuration diagram showing a fourth embodiment of the disk system according to the present invention.

FIG. 9 is a diagram showing a memory table used for a cache memory unit in the disk system according to the present invention.

FIG. 10 is a diagram showing an operation of a cache memory unit employed in the disk system according to the present invention.

FIG. 11 is a configuration diagram showing a third embodiment of the cache memory unit in the disk system according to the present invention.

[Explanation of symbols]

1 Disk section 2, 2-1, 2
-2 Controller 21 Host interface 22 Microprocessor unit 23, 23-1, 23-2, 23B-1, 23B-2
Cache memory unit 31 DRAM 32 DRAM
Control unit 33, 33A Data path switching control unit 34 Mirroring copy interface 35 PCI bus interface

Claims (7)

[Claims] 1. A disk unit for storing data,
In a disk system corresponding to an access of a host computer, a plurality of pairs of a control unit for controlling data access to the disk unit and a cache memory unit having a cache memory for temporarily storing data are provided. A data transfer path that connects only the sections to each other, and control means that is provided in each of the sets of cache memory sections and performs data transfer between the cache memory sections via the data transfer path. Disk system. 2. The control unit according to claim 1, wherein when writing data to the cache memory of the cache memory unit, the control unit transfers the data to another cache memory unit via the data transfer path. Disk system. 3. A sub-cache memory unit provided corresponding to each of the sets of cache memory units, the sub-cache memory unit temporarily storing data, and the data stored in the set of cache memory units. 2. The disk system according to claim 1, further comprising a sub-cache memory unit having a sub-cache memory unit control unit that matches data in the sub-cache memory unit. 4. A dedicated path for connecting only between the cache memory unit and the sub-cache memory unit is provided, and the sub-cache memory unit control means is held in the set of cache memory units via the dedicated path. 4. The disk system according to claim 3, wherein the data stored in the sub-cache memory unit is matched with the data stored in the sub-cache memory unit. 5. The control unit of each set separately controls different data areas of a disk unit, and when a failure occurs in any one of the control units, the control unit is replaced by one of the other control units. The disk system according to claim 1, wherein 6. A cache table provided in a cache memory unit, comprising: a memory table for managing write permission / prohibition information based on an access situation and a memory table for managing the information in the memory table. The disk system according to claim 1, wherein permission / non-permission information is transmitted based on information in the memory table in response to data transfer request information arriving via a transfer path. 7. A disk unit for storing data,
A control unit for controlling data access to the disk unit and a first cache memory unit having a cache memory for temporarily storing data, wherein the data is temporarily stored in the cache system of the disk system corresponding to the access of the host computer A second cache memory unit having a cache memory to be connected, a data transfer path interconnecting only the first cache memory unit and the second cache memory unit, and a data transfer path provided in the first cache memory unit; A control unit for transferring data to the second cache memory unit via the data transfer path; and a control unit provided in the second cache memory unit for transferring data to the first cache memory unit via the data transfer path. And a control means for the disk system. Gerhard system.