JPS5781659A - Storage controller - Google Patents

Storage controller

Info

Publication number
JPS5781659A
JPS5781659A JP15800280A JP15800280A JPS5781659A JP S5781659 A JPS5781659 A JP S5781659A JP 15800280 A JP15800280 A JP 15800280A JP 15800280 A JP15800280 A JP 15800280A JP S5781659 A JPS5781659 A JP S5781659A
Authority
JP
Japan
Prior art keywords
access
becomes
address
module
equal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15800280A
Other languages
Japanese (ja)
Other versions
JPS6211752B2 (en
Inventor
Shukichi Moriyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15800280A priority Critical patent/JPS5781659A/en
Publication of JPS5781659A publication Critical patent/JPS5781659A/en
Publication of JPS6211752B2 publication Critical patent/JPS6211752B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Abstract

PURPOSE:To improve the efficiency of a memory access, by equalizing the access frequency between storage units. CONSTITUTION:Tables TABL0, TABL1 constitute a table which stores effective bits V0-V3 and interleave control bits I0-I3 of a module, and this table is set in advance by software or hardware. For instance, in case when the table has been set as V0-V3=1, I3=0, and I0-I2=1, V0, V2, I0 and I2 are equal to ''1'' when an access address AA from an access device is 00-1F, therefore, an output of an AND circuit AND becomes ''1'', a selecting circuit SEL selects the side of ''1'', and flow of its address bit becomes like a solid line. Also, in case when the access address AA is 20-3F, I3 is equal to ''0'', therefore, an output of the AND becomes ''0'', the selecting circuit SEL selects the side of ''0'', and the flow of the address bit becomes like a dotted line. In this way, the addressing is operated so as to be varied, depending on a module.
JP15800280A 1980-11-10 1980-11-10 Storage controller Granted JPS5781659A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15800280A JPS5781659A (en) 1980-11-10 1980-11-10 Storage controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15800280A JPS5781659A (en) 1980-11-10 1980-11-10 Storage controller

Publications (2)

Publication Number Publication Date
JPS5781659A true JPS5781659A (en) 1982-05-21
JPS6211752B2 JPS6211752B2 (en) 1987-03-14

Family

ID=15662097

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15800280A Granted JPS5781659A (en) 1980-11-10 1980-11-10 Storage controller

Country Status (1)

Country Link
JP (1) JPS5781659A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009199135A (en) * 2008-02-19 2009-09-03 Nec Computertechno Ltd Main storage device and address control method of main storage device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0544312Y2 (en) * 1986-12-12 1993-11-10
JPH0231862U (en) * 1988-08-19 1990-02-28

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009199135A (en) * 2008-02-19 2009-09-03 Nec Computertechno Ltd Main storage device and address control method of main storage device

Also Published As

Publication number Publication date
JPS6211752B2 (en) 1987-03-14

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