JP4992114B2 - Main storage device and address control method for main storage device - Google Patents

Description

  The present invention relates to a main storage device of a computer system, and more particularly to an address control technique for improving the throughput of the main storage device.

  In a main storage device including a plurality of RAMs and each RAM being divided into a plurality of banks, generally, successive logical addresses are repeatedly accessed from the first bank to the last bank of the RAM, and the last bank When the last position in the RAM is accessed, the logical address issued from the arithmetic processing unit is converted into a physical address by physical address generation logic that repeatedly converts the physical bank from the first bank to the last bank in another RAM. ing. Therefore, for example, in the main storage device including the RAMs # 1 and # 2, when consecutive logical addresses are issued from the arithmetic processing unit, the BANK00 to BANK07 of the RAM # 1 are changed as shown in FIG. After being repeatedly accessed and the last address in BANK07 is accessed, BANK08 to BANK15 of RAM # 2 are repeatedly accessed.

  On the other hand, Patent Document 1 describes a technology for switching address generation logic for each RAM having different RAM interfaces (electrical and logical interfaces between the memory controller and the RAM are different) regarding the memory of the computer system.

JP 2004-213337 A

  When RAM # 1 and # 2 are high-speed RAMs with a short cycle time, when consecutive logical addresses are issued from the arithmetic processing unit, BANK00 to BANK07 of RAM # 1 are repeatedly accessed as shown in FIG. Thereafter, there is no problem even if the BANK08 to BANK15 of the RAM # 2 are repeatedly accessed. However, when the RAM # 1 and # 2 are low-speed RAMs, there is a problem that the throughput of the main storage device is lowered. . That is, when RAM # 1 and # 2 are low-speed RAMs, the last banks BANK07 and 15 are accessed and then the first banks BANK00 and 08 are tried to be accessed. At that time, the outputs of BANK00 and 08 are determined. Therefore, it is necessary to wait for the output of BANK00 and 08 to be finalized (bank conflict), and the throughput of the main storage device is reduced accordingly.

  Patent Document 1 describes a technique for switching address generation logic for each RAM having a different RAM interface with respect to the memory of the computer system, but does not describe the above-described problem and its solution.

(Object of invention)
Accordingly, an object of the present invention is to increase the throughput even when the main storage device is constituted by a low-speed RAM.

The first main storage device according to the present invention is:
In a main storage device having a plurality of RAMs and a memory controller,
The plurality of RAMs are each divided into a plurality of banks; and
The memory controller is
Operation is performed by first physical address generation logic in which consecutive logical addresses are sequentially accessed from the first bank of the RAM to the last bank, and after the last bank is accessed, the first bank is converted to a physical address for accessing the first bank of another RAM. An address generation circuit for converting a logical address issued from a processing device into a physical address is provided.

An address control method for a first main storage device according to the present invention includes:
An address control method for a main storage device comprising a plurality of RAMs, wherein each of the plurality of RAMs is divided into a plurality of banks,
A first physical address in which the address generation circuit sequentially accesses the last bank from the first bank of the RAM and converts the continuous logical address into a physical address that accesses the first bank of another RAM after accessing the last bank. According to the generation logic, a logical address issued from the arithmetic processing unit is converted into a physical address.

  According to the present invention, even if the RAM constituting the main storage device is a low-speed RAM, the throughput of the main storage device is increased.

  Next, the best mode for carrying out the present invention will be described in detail with reference to the drawings.

Embodiment of the present invention
Referring to FIG. 1, a computer system according to the present embodiment includes a central processing unit (CPU) 1, a main storage unit (MMU) 2, and a memory storage disk unit 5 realized by a magnetic disk unit or the like. It is configured.

  The main storage device 2 includes a memory controller 3 and a storage unit 4.

  The storage unit 4 is composed of a plurality of RAMs 4-1 to 4-4, and each RAM 4-1 to 4-4 has an 8-bank configuration. The RAMs 4-1 and 4-2 are connected to the memory controller 3 by a bus of memory channel (memory CH) number # 0, and the RAMs 4-3 and 4-4 are connected to the memory controller 3 by a bus of memory CH number # 1. Has been.

  The memory controller 3 includes an address mode register 3-1, a memory access control circuit 3-2, a throughput counter 3-3, a busy counter 3-4, and an address generation circuit 3-5.

  The address mode register 3-1 is a register used for switching the physical address generation logic of the address generation circuit 3-5, and is used as selection information for selecting the first or second physical address generation logic A or B. , “0” or “1” is stored. The setting of the address mode register 3-1 is performed by the operating system (OS) and the memory access control unit 3-2.

  The memory access control unit 3-2 is a chip enable signal or a write / read enable signal for controlling the RAM constituting the storage unit 4 in accordance with an access request (write / read command) to the main storage device issued by the arithmetic processing unit 1. In addition, the control signal transmission timing interval control (busy control) to the RAM is performed according to the RAM specifications. Further, the memory access control unit 3-2 starts the count operation of the throughput counter 3-3 and the busy counter 3-4 when the counter measurement start instruction is issued from the OS, and when the counter read instruction is issued from the OS, The count values of the throughput counter 3-3 and the busy counter 3-4 are transferred to the OS. Further, when there is an address assignment switching instruction from the OS, a process of setting an address switching flag provided therein, a process of copying (saving) the contents of the storage unit 4 to the memory storage disk device 5, Processing for changing the value of the selection information set in the address mode register 3-1 to a value corresponding to the physical address allocation type instructed by the physical address switching instruction, and the data saved in the memory storage disk device 5 as OS The processing of writing back to the storage unit 4 and the processing of resetting the address switching flag are sequentially performed by the physical address allocation type allocation method instructed by

  The address generation circuit 3-5 converts the address (logical address) issued from the arithmetic processing device 1 into a physical address for controlling the RAM constituting the storage unit 4. At this time, if the value of the address mode register 3-1 is “0”, the logical address is converted into a physical address using the first physical address generation logic A, and if it is “1”, the second physical address is converted. A logical address is converted into a physical address using the generated logic B. The first and second physical address generation logics A and B will be described in detail later.

  The throughput counter 3-3 is a counter for counting the number of memory access requests processed by the main storage device 2 in an arbitrary period. The busy counter 3-4 is a counter for counting a request issuance waiting time due to busy occurring in an arbitrary period, and includes counters 3-4a to 3-4c for each busy type as shown in FIG. ing. The counter 3-4a counts the waiting time (busy time) at the time of continuous access to the same bank as shown in FIG. 3A, and the counter 3-4b is different from that in the same RAM as shown in FIG. The waiting time at the time of continuous access to the bank is counted, and the counter 3-4c counts the waiting time at the time of continuous access between different RAMs connected to the data bus in the memory CH as shown in FIG. Note that the waiting time (bus conflict time) shown in FIG. 3C is generally independent of the speed rank (cycle time) of the RAM alone, and the physical configuration of the bus (wiring length, device connected to the bus) Number).

[Description of Operation of Embodiment]
Next, the operation of the present embodiment will be described in detail. Note that the computer system according to the present embodiment can operate in three modes: a normal mode, a dynamic allocation mode, and an automatic optimization mode.

[Operation in normal mode]
First, the operation in the normal mode will be described. When operating in the normal mode, first, a value corresponding to the speed (cycle time) of the RAMs 4-1 to 4-4 constituting the storage unit 4 is set in the address mode register 3-1. When the RAMs 4-1 to 4-4 are low-speed RAMs, “0” is set, and when the RAMs are high-speed RAMs, “1” is set. In this setting, for example, the administrator instructs the OS to set a value to be set in the address mode register 3-1, and the OS that has received this instruction sets the specified value in the address mode register 3-1. Thereafter, the OS instructs the execution of the program.

  The memory access control unit 3-2 is a chip enable for controlling the RAM constituting the storage unit 4 in accordance with an access request (write / read command) to the main storage device 2 issued by the arithmetic processing unit 1 as the program is executed. Signals and write / read enable signals are generated. The address generation circuit 3-5 converts the address (logical address) issued from the arithmetic processing device 1 into a physical address for controlling the RAM that constitutes the storage unit 4. At that time, as shown in the flowchart of FIG. 4, if the value of the address mode register 3-1 is “0” (YES in Step S401), the address generation circuit 3-5 performs the first physical address generation logic A. Is used to generate a physical address (step S402), and if “1” (NO in step S401), a physical address is generated using the second physical address generation logic B (step S403).

  FIGS. 5A and 5B are diagrams showing address allocation when the physical addresses are generated using the first and second physical address generation logics A and B, respectively. In the first physical address generation logic A, as shown in FIG. 5A, the least significant bit [0th bit] of the logical address is arranged at the bit position indicating the memory CH number of the physical address, 3 bits [1st to 3rd bits] of the physical address are arranged in the bit position indicating the bank number in the RAM of the physical address, and the next 1 bit [4th bit] of the logical address is the group in the memory CH (GRP) of the physical address. ) The physical address is generated by placing the bit in the bit position indicating the number and placing the remaining bits of the logical address [5th bit to (n-1) bit] in the bit position indicating the bank address of the physical address. To do. Such an address assignment is referred to as a first address assignment A. Further, in the second physical address generation logic B, as shown in FIG. 5B, the least significant bit [0th bit] of the logical address is arranged at the bit position indicating the memory CH number of the physical address, and the logical address The next 3 bits [1st to 3rd bits] are arranged at the bit position indicating the bank number in the RAM of the physical address, and the most significant bit [(n-1) bit] of the logical address is a group of physical addresses A physical address is generated by arranging the remaining bits [fourth to (n-2) th bits] of the logical address in the bit position indicating the bank address of the physical address by arranging the bit address indicating the number. . Such address assignment is referred to as second address assignment B.

  Therefore, when the first physical address generation logic A is used, for example, when the logical address all addresses “0” are continuously accessed, the access is made in the order of BANK00 → BANK01 → BANK02 →... → BANK31 → BANK00 → BANK01 → Will be. When this is limited to one memory CH, in the memory CH # 0, the order of BANK00 → BANK02 →. It can happen.

  On the other hand, when the second physical address generation logic B is used, if the logical addresses are all continuously accessed from the address “0”, the access in the order of BANK00 → BANK01 →... → BANK14 → BANK15 is made multiple times (group number # 0 Until all the addresses of the RAM are accessed), and then BANK16 → BANK17 →... → BANK30 → BANK31 are accessed a plurality of times. If this is limited to the memory CH, in the memory CH # 0, the access in the order of BANK00 → BANK02 →... → BANK14 is performed a plurality of times, and then the access in the order of BANK16 → BANK18 →. . Also in this case, there is a possibility that a bus conflict occurs when BANK14 → BANK16. However, since the frequency over which the RAM is accessed is reduced as compared with the case where the first physical address generation logic A is used. The risk of bus conflicts is reduced.

  FIG. 6 shows an example of the busy time. A general DDR-SDRAM memory device has a data bus speed of several ns, but has a continuous access time of several tens of ns. Concealing time. Therefore, the breakdown of the busy cycle is approximately as shown in FIG. In FIG. 6, for each of the low-speed and high-speed RAMs, the busy time for write access to the same bank in the same RAM, the busy time for read access to the same bank in the same RAM, and different banks in the same RAM are consecutive. Busy time for read or write access, busy time for sequential read access and write access to different banks in the same RAM, and sequential write access and read access to different banks in the same RAM Busy time, busy time for consecutive read or write access to different RAMs, busy time for sequential read access and write access to different RAMs, write access and read access to different RAMs Indicates busy time for sequential To have.

  As can be seen from FIG. 6, in the case of a low-speed RAM, the bottleneck of memory throughput is largely due to the same bank access during random access (small access of several bytes to several hundred bytes). Therefore, in the case of a low-speed RAM, the larger the interleave number (bank number) in the continuous address, the better the memory throughput. For example, when the data width per memory address is 4 bytes, the number of interleaves in 256 consecutive bytes is 32 in the case of the address assignment A shown in FIG. 5A, and is shown in FIG. In the case of the address allocation B, the address allocation A is 16. Therefore, the address allocation A is preferable.

  On the other hand, the same bank access busy time of a high-speed RAM (for example, FCRAM) is significantly shorter than that of the low-speed RAM, and the influence of the bus conflict time cannot be ignored. Depending on the memory access characteristics of the program to be executed, There are cases in which the effect of a decrease in memory throughput appears significantly.

  FIG. 7 shows the result of simple calculation of the influence of bank conflict and bus conflict. FIGS. 7A and 7B show the results of simple calculations of the effects of bank conflict and bus conflict for address assignments A and B, respectively.

  In the case of address allocation A, as shown in FIG. 5A, the number of banks per memory CH is 16, and since consecutive addresses are allocated to these 16 banks, the main memory access instruction issue rate is Assuming 100%, the probability of continuously accessing the same bank is 1/16, the probability of accessing different banks in the same RAM is 7/16, and the probability of accessing another RAM in the memory CH is 8/16. The value obtained by multiplying the probability (a) in each case described above by the low speed and high speed RAM busy times (b) and (b ′) in each case described above is the low speed and high speed RAM busy time in each case described above. Index value (expected value). Here, for each of the high-speed RAM and the low-speed RAM, the total value of the index values is “14.25” and “17.25”, respectively. The smaller this value is, the less the memory throughput is reduced due to bank conflicts and bus conflicts.

  On the other hand, in the case of address assignment B, as shown in FIG. 5B, the number of banks per memory CH is 16, but 8 addresses are assigned consecutive addresses. Therefore, a bus conflict occurs only at the time of continuous access across an m / 2 byte boundary when the storage capacity of the main storage device is m bytes. For example, if the capacity of one RAM shown in FIG. 5B is 1 Gbyte, the memory capacity per memory CH is 2 Gbyte. Focusing on the locality of main memory access during program execution, assuming a program with a local address range of several kilobytes to several megabytes, the effect of bus conflict due to memory access across the m / 2 byte boundary is as follows: It can be easily guessed that it is almost negligible. If the influence of the bus conflict is ignored and the busy time index value of the low-speed and high-speed RAM is obtained in the same manner as in the case of the address assignment A, the result is as shown in FIG. As shown in FIG. 7B, the total index values of the high-speed RAM and the low-speed RAM in the case of address allocation B are “13.5” and “19.5”, respectively.

  As can be seen from FIGS. 7A and 7B, in the case of the high-speed RAM, the total value of the index values is smaller in the address allocation B, and conversely in the case of the low-speed RAM, the address allocation A is the index value. The total value of becomes smaller.

  Accordingly, when the RAMs 4-1 to 4-4 constituting the storage unit 4 are low-speed RAMs, "0" is set in the address mode register 3-1 so that address allocation A is performed. In this case, by setting “1” in the address mode register 3-1 so that the address allocation B is performed, a decrease in the main memory throughput can be minimized.

[Operation in dynamic allocation mode]
Next, the operation in the dynamic allocation mode will be described with reference to FIGS. This mode is used when the address assignment type (indicating address assignment A or address assignment B) of each program to be executed is determined in advance. The address allocation type is specified by, for example, a program compile option, and the OS switches the address allocation type as necessary based on this specification. Note that the address allocation type of each program is selected based on the characteristics of each program (regularity of addresses to be accessed) so that the decrease in main memory throughput is reduced.

  When there are programs A and B whose address allocation types are determined in advance and program B is executed after program A, as shown in the flowchart of FIG. Next, the address allocation type of the program B to be executed is checked (step S801), and the current address allocation type is checked with reference to the address mode register 3-1 (step S802). Thereafter, the OS compares the address allocation types checked in steps S801 and S802 (step S803).

  If the two match (step S803 is YES), the next program B is immediately instructed to be executed (step S806). On the other hand, if the two do not match (NO in step S803), an address assignment switching instruction including the address assignment type of program B is output to the memory access control unit 3-2 (step S804). It waits for the address switching flag to be reset (step S805). If the address switching flag is reset (YES in step S805), execution of the program B is instructed (step S806).

  Next, an operation of the memory access control unit 3-2 when an address assignment switching instruction is input will be described with reference to FIG. However, FIG. 9 shows a case where the current address assignment type is address assignment A, and the address assignment type of the program B to be executed next is address assignment B.

  When the execution of the program A is completed, the OS outputs an address allocation switching instruction including the address allocation type (address allocation B) of the program B to the memory access control unit 3-2.

  Thereby, the memory access control unit 3-2 first sets an address switching flag (step S901 in FIG. 9), and notifies the arithmetic processing unit 1 of prohibition of main memory access. Next, the memory access control unit 3-2 copies the data in the storage unit 4 to the memory storage disk device 5 (step S902), and sets the value of the address mode register 3-1 to the address allocation B when the copy is completed. The corresponding value is updated to “1” (step S903). Thereafter, the memory access control unit 3-2 writes the contents of the memory storage disk device 5 back to the storage unit 4 with the address assignment B (step S904). At this time, the data in the storage unit 4 corresponds to the address assignment B. Since the address conversion is closed in the main storage device 2, it is not necessary to read the address between the arithmetic processing unit 1 and the main storage device 2. Thereafter, the memory access control unit 3-2 resets the address switching flag (step S905). As a result, the OS instructs execution of the program B.

[Operation in automatic optimization mode]
Next, the operation in the automatic optimization mode will be described with reference to FIGS.

  When instructing the execution of a new program, the OS first checks the current address allocation type with reference to the address mode register 3-1 (step S1001 in FIG. 10). For example, assume that the address assignment type is address assignment A. Thereafter, the OS outputs a counter measurement start instruction and a program execution instruction to the memory access control unit 3-2 (steps S1002 and S1003). In step S1003, instead of the execution target program, execution of a test program (for example, a program in which the data array of the execution program is reduced) for the execution target program prepared by the user may be instructed.

  When a counter measurement start instruction is input, the memory access control unit 3-2 outputs a counter reset signal to the throughput counter 3-3 and the busy counter 3-4 as shown in FIG. Output. As a result, the throughput counter 3-3 starts counting the number of memory access requests processed by the main storage device 2, and the throughput counter 3-4 starts counting the request issuance waiting time.

  On the other hand, when a predetermined time T has elapsed after outputting the program execution instruction, the OS instructs the program to stop and outputs a counter read instruction to the memory access control unit 3-2 (step S1004). When the test program is executed, the counter read instruction is output after the test program is completed.

  As a result, the memory access control unit 3-2 sets the counter enable signal to “0” and transmits the count values of the throughput counter 3-3 and the busy counter 3-4 to the OS. The OS holds the count values of both counters at the time of address allocation A (step S1005). The busy counter 3-4 holds the total value of the count values of the counters 3-4a to 3-4c. Hereinafter, this total value is referred to as the total value of the busy counter 3-4.

  Thereafter, since the OS measures the throughput and the request issuance waiting time only in address allocation A among address allocations A and B (NO in step S1006), in order to change the address allocation type to address allocation B, An address assignment switching instruction is output to the memory access control unit 3-2 (step S1007). As a result, the memory access control unit 3-2 performs the same processing as steps S901 to S905 described above (steps S1101 to 1105 in FIG. 11).

  When the address switching flag is reset, the OS again performs the above-described processing of steps S1002 to S1005 and holds the count values of both counters at the time of address allocation B.

  Thereafter, the OS determines the count values of the throughput counter 3-3 and the busy counter 3-4 when the address allocation is A, and the count values of the throughput counter 3-3 and the busy counter 3-4 when the address allocation is B. Based on a predetermined criterion, it is determined which one of the address assignments A and B is used (step S1009). Here, the following can be used as a criterion. The count value of the throughput counter 3-3 increases as the throughput increases, and the count value of the busy counter 3-4 decreases as the throughput increases. Therefore, for example, it is possible to adopt a criterion of using the address allocation A, B, whichever has a larger count value of the throughput counter 3-3. In addition, it is possible to adopt a determination criterion in which one of the address assignments A and B in which the count value of the busy counter 3-4 becomes smaller is used. Of the address assignments A and B, the ratio between the count value of the throughput counter 3-3 and the count value of the busy counter 3-4 (the count value of the throughput counter 3-3 / the count value of the busy counter 3-4) is The criterion of using the larger one can also be adopted.

  If the address allocation type determined in step S1009 is the same as the current address allocation type (S1010 is YES), a program execution instruction is immediately output (S1013). On the other hand, when the determined address allocation type is different from the current address allocation type (NO in step S1010), the address allocation switching is performed for the memory access control unit 3-2 in order to change the address allocation type. An instruction is output (step S1011), and after waiting for the address switching flag to be reset (YES in S1012), a program start instruction is output (step S1013).

[Effect of the embodiment]
According to this embodiment, even if the RAMs 4-1 to 4-4 constituting the main storage device 2 are low-speed RAMs, the throughput of the main storage device 2 can be increased. The reason is that the first physical address generation is such that consecutive logical addresses are sequentially accessed from the first bank of the RAM to the last bank, and after the last bank is accessed, the physical address is accessed to access the first bank of another RAM. This is because it includes an address generation circuit 3-5 that converts a logical address issued from the arithmetic processing unit 1 into a physical address by logic.

  Further, according to the present embodiment, the throughput of the main storage device 1 is increased regardless of whether the RAMs 4-1 to 4-4 constituting the main storage device 2 are low speed RAMs or high speed RAMs. Can do. This is because an address generation circuit is provided that converts a logical address into a physical address by the first or second physical address generation logic based on the value set in the address mode register 3-1.

  Furthermore, according to the present embodiment, the first or second physical address generation logic is used according to the characteristics of the program to be executed (main memory access address characteristics), so that the throughput is increased for each program to be executed. There is also an effect that can be optimized.

  The present invention is preferably applied to address control of the main storage device.

It is a block diagram of an embodiment of the invention. It is a block diagram which shows the structural example of the busy counter 3-4. It is a figure for demonstrating busy classification. It is a flowchart which shows the process example of the address generation circuit 3-5. It is the figure which showed the difference in the address allocation by the difference in a physical address generation logic. It is a figure which shows an example of busy time. It is a figure which shows the simple calculation result of busy time. It is a flowchart which shows the process example of OS in the dynamic allocation mode. It is a figure for demonstrating the operation | movement at the time of dynamic allocation mode. It is a flowchart which shows the process example of OS in the automatic optimization mode. It is a figure for demonstrating the operation | movement at the time of automatic optimization mode. It is a figure for demonstrating a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Processing unit 2 ... Main memory 3 ... Memory controller 3-1 ... Address mode register 3-2 ... Memory access control part 3-3 ... Throughput counter 3-4 ... Busy counter 3-5 ... Address generation circuit 4- 1-4-4 ... RAM
5 ... Disk storage device for memory storage

Claims (4)

In a main storage device having a plurality of RAMs and a memory controller,
The plurality of RAMs are each divided into a plurality of banks; and
The memory controller is
An address mode register in which selection information for selecting the first physical address generation logic or the second physical address generation logic is set ;
When the first physical address generation logic is selected by the selection information, successive logical addresses are sequentially accessed from the first bank of the RAM to the last bank, and after accessing the last bank, the first bank of another RAM is accessed. Is converted into a physical address by converting the logical address issued from the arithmetic processing unit into a physical address, and the second physical address generation logic is selected by the selection information. In this case, a continuous logical address is repeatedly accessed from the first bank to the last bank in the RAM, accessed to the last position in the last bank, and then converted to a physical address for accessing the first bank in another RAM. Logical address issued from the arithmetic processing unit by the physical address generation logic of An address generating circuit for converting a physical address,
A throughput counter that counts the number of memory access requests processed by the main storage device in an arbitrary period;
A busy counter that counts the request issuance waiting time due to busy that occurred during an arbitrary period,
The ratio between the count value of the throughput counter and the count value of the busy counter when the program is executed with the physical address generation logic of the address generation circuit set to the first physical address generation logic, and the physical value of the address generation circuit based address generation logic and the ratio between the count value and the count value of the busy counter of said throughput counter when executing the program by the second physical address generation logic, the physical address selected by the selection information a main storage device characterized by comprising a control means for determining a generation logic. The main storage device according to claim 1 ,
It has a disk device for memory storage,
The control means saves the data stored in each RAM before setting the selection information in the address mode register to the memory storage disk device, sets the selection information, and then sets the selected selection information. A main storage device, wherein the data saved in the memory storage disk device is written back to each RAM using the physical address generation logic indicated by. An address control method for a main storage device comprising a plurality of RAMs, wherein each of the plurality of RAMs is divided into a plurality of banks,
An address mode register in which selection information for selecting the first physical address generation logic or the second physical address generation logic is set ;
A throughput counter that counts the number of memory access requests processed by the main storage device in an arbitrary period;
A busy counter that counts the request issuance waiting time due to busy that occurred during an arbitrary period,
When the first physical address generation logic is selected by the selection information, the address generation circuit sequentially accesses the last bank from the first bank of the RAM, and accesses the last bank. The first physical address generation logic for converting the first bank of another RAM into a physical address to be accessed is used to convert the logical address issued from the arithmetic processing unit into a physical address, and the second physical address generation logic is determined by the selection information. Is selected, the successive logical addresses are repeatedly accessed from the first bank to the last bank of the RAM, accessed to the last position in the last bank, and then accessed to the physical address for accessing the first bank of another RAM. By the second physical address generation logic of conversion, the arithmetic processing unit Converting the logical address into a physical address,
A ratio between a count value of the throughput counter and a count value of the busy counter when the control unit executes a program with the physical address generation logic of the address generation circuit set to the first physical address generation logic; based on physical address generation logic generating circuit and the ratio between the count value and the count value of the busy counter of said throughput counter when executing the program by the second physical address generation logic, by the selection information An address control method for a main storage device, comprising determining a physical address generation logic to be selected . The main memory address control method according to claim 3 ,
A disk device for memory storage is provided,
The control means saves the data stored in each RAM before setting the selection information in the address mode register to the memory storage disk device, sets the selection information, and then sets the selected selection information. An address control method for a main storage device, wherein the data saved in the memory storage disk device is written back to each RAM using the physical address generation logic indicated by

Images