JPS62115381A - Lsi tester - Google Patents

Lsi tester

Info

Publication number
JPS62115381A
JPS62115381A JP60255885A JP25588585A JPS62115381A JP S62115381 A JPS62115381 A JP S62115381A JP 60255885 A JP60255885 A JP 60255885A JP 25588585 A JP25588585 A JP 25588585A JP S62115381 A JPS62115381 A JP S62115381A
Authority
JP
Japan
Prior art keywords
lsi
tester
signal lines
input
output signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60255885A
Other languages
Japanese (ja)
Inventor
Masato Kawai
正人 河合
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60255885A priority Critical patent/JPS62115381A/en
Publication of JPS62115381A publication Critical patent/JPS62115381A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE:To facilitate generation of a test pattern, make an LSI aggregate perform self inspection and make testing at high speed and high accuracy in real time possible by mounting plural LSI at the same time, connecting signal lines properly to test LSI as an aggregate. CONSTITUTION:LSI 11, 12 to be tested are mounted on a tester by adapters 21, 22 respectively. A part of input/output signal lines 111-113, 121-123 of the LSI 11, 12 to be tested are connected between LSI by connecting units 3, and the rest is connected to the pin electronics 4 of the LSI tester. The LSI tester tests LSI 11, 12 to be tested as an aggregate of LSI applying signals only to the input/output signal lines 111, 123 of the pin electronics 4 of the LSI tester or observing the signals.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ＬＳＩテスタ、特に、複数個のＬＳＩを同時
にひとつの機能を有するＬＳＩ集合体とみなして検査す
ることができるＬＳＩテスタに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an LSI tester, and particularly to an LSI tester that can simultaneously test a plurality of LSIs while treating them as an LSI assembly having one function.

〔従来の技術〕[Conventional technology]

従来のＬＳＩテスタは、同時には准ひとつのＬＳＩが搭
載できるだけのアダプタと、このアダプタ経由ですべて
のＬ８Ｉの入出力信号線がテスタのピンエレクトロニク
スに接続される構成となっていた。Conventional LSI testers were configured with an adapter that could accommodate only one LSI at a time, and through which all L8I input/output signal lines were connected to the tester's pin electronics.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

このため、上述した従来のＬＳＩテスタは同時にはひと
つのＬＳＩ１．か検査できないため、いくつかのＬＳＩ
をまとめた場合には、機能的に簡単な試験が可能になる
場合や、さらにもっと進んで、ＬＳＩをまとめて、自己
検査ができるような構成になっている場合でも、個別の
ＬＳＩ単位で試験を実行しなければならず、試験バタン
の発生が困難だったり、高速な試験ができなかったりと
いった欠点がある。For this reason, the conventional LSI tester described above can only test one LSI1. Some LSI
In cases where functionally simple tests are possible, or even if the configuration is such that self-testing can be performed by grouping LSIs together, it is not possible to test each individual LSI. This method has drawbacks such as difficulty in generating test slams and inability to perform high-speed tests.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のＬＳＩテスタは、複数個の被試験ＬＳＩを搭載
できるアダプタと、ＬＳＩの入出力信号線をピンエレク
トロニクスもしくは、他のＬＳＩの入出力信号線と結び
つける接続ユニットとを含んで構成される。The LSI tester of the present invention includes an adapter that can mount a plurality of LSIs under test, and a connection unit that connects the input/output signal lines of the LSI to the input/output signal lines of pin electronics or other LSIs.

〔実施例〕〔Example〕

次に、本発明の実施例について、図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.

第１図は本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing one embodiment of the present invention.

被試験Ｌ８１１１，１２は、各々アダプタ２１．２２に
よシテスタに搭載される。The L8111 and L812 under test are mounted on the tester using adapters 21 and 22, respectively.

被試験ＬＳ１１１．１２の入出力信号ｌｌＡ１１１〜１
１３゜１２１〜１２３は接続ユニット３により一部はＬ
ＳＩ間で接続され、残りはＬＳＩテスタのピンエレクト
ロニクス４に接続される。Input/output signal llA111-1 of LS111.12 under test
13° 121 to 123 are partially L due to connection unit 3
The SIs are connected to each other, and the rest are connected to the pin electronics 4 of the LSI tester.

ＬＳＩテスタはピンエレクトロニクス４に接続された入
出力信号線１１１，１２３にのみ信号を印加したり、信
号を観測したりしてＬＳＩ集合体として被試験ＬＳＩＩ
Ｉ、１２の試験を行う。The LSI tester applies signals only to the input/output signal lines 111 and 123 connected to the pin electronics 4, and observes the signals to test the LSI under test as an LSI assembly.
I. Perform 12 tests.

第２図は第１図に示す接続ユニット３の一例を示すブロ
ック図である。FIG. 2 is a block diagram showing an example of the connection unit 3 shown in FIG. 1.

接続ユニット３はスイッチボックス５の集合から構成さ
れ Ｌ８１１１側の入出力信号線１１２，１１３とＬ８１１
２側の入出力信号線１２１，１２２を接続したり ＬＳＩＩＩ側の入出力信号＆１１１１およびＬｆ！３１
１２側の入出力信号線１２３をテスタのピンエレクトロ
ニクス４に接続している。The connection unit 3 is composed of a set of switch boxes 5, and input/output signal lines 112, 113 on the L8111 side and L811
Connect the input/output signal lines 121 and 122 on the 2 side, and input/output signals &1111 and Lf! on the LSIII side. 31
The input/output signal line 123 on the 12 side is connected to the pin electronics 4 of the tester.

なお、上述の実施例では、スイッチで接続ユニットを構
成したがこれ以外の方法で接続ユニットを構成したＬＳ
Ｉテスタも本特許請求の囲に含まれることは轟然である
。In the above embodiment, the connection unit was configured with a switch, but an LS with a connection unit configured using a method other than this may also be used.
It is surprising that the I tester is also included in the claims of this patent.

〔発明の効果〕〔Effect of the invention〕

本発明のＬＳＩテスタは、複数個のＬＳＩを同時に搭載
し、これらＬＳＩ間で適宜信号線を接続することによＦ
）ＬＳ　Ｉを集合体としてテストでビるため、ＬＳＩ＋
７＞集合体として機能的にまとまっている構成をとらせ
ることによシ試験バタンの発生が容易になったり、ＬＳ
Ｉ集合体に自己検査をさせることができたり、あるいは
、実時間で高速・高精度な試験をさせることができると
いう効果がある。The LSI tester of the present invention mounts multiple LSIs at the same time and connects appropriate signal lines between these LSIs.
) LSI+
7> By having a functionally organized structure as a collection, it becomes easier to generate test bangs, and LS
This has the effect of allowing the I-assembly to perform self-inspection, or to perform high-speed, high-precision testing in real time.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例を示すブロック図、第２図は
第１図に示す接続ユニットの一例を示すブロック図であ
る。 １１・・・・・・被試験Ｌ８Ｉ、１１１〜１１３・・・
・・・入出力信号線、１２・・・・・・被試験ＬＳＩ、
１２１〜１２３・・・・・・入出力信号線、２１・・・
・・・アダプタ、２２・・・・・・アダプタ、３・・・
・・・接続エニット、４・・・・・・ピンエレクトロニ
クス、５・・・・・・スイッチボックス。 桝２　面FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a block diagram showing an example of the connection unit shown in FIG. 1. 11...Test L8I, 111-113...
...Input/output signal line, 12... LSI under test,
121-123... Input/output signal line, 21...
...Adapter, 22...Adapter, 3...
... connection enit, 4 ... pin electronics, 5 ... switch box. 2nd square

Claims (1)

【特許請求の範囲】[Claims] 複数個の被試験ＬＳＩを搭載できるアダプタと、前記被
試験ＬＳＩの入出力信号線をピンエレクトロニクスもし
くは他の、ＬＳＩの入出力信号線を結びつける接続ユニ
ットとを含むことを特徴とするＬＳＩテスタ。An LSI tester comprising an adapter capable of mounting a plurality of LSIs under test, and a connection unit for connecting input/output signal lines of the LSIs under test to pin electronics or other LSI input/output signal lines.
JP60255885A 1985-11-14 1985-11-14 Lsi tester Pending JPS62115381A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60255885A JPS62115381A (en) 1985-11-14 1985-11-14 Lsi tester

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60255885A JPS62115381A (en) 1985-11-14 1985-11-14 Lsi tester

Publications (1)

Publication Number Publication Date
JPS62115381A true JPS62115381A (en) 1987-05-27

Family

ID=17284918

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60255885A Pending JPS62115381A (en) 1985-11-14 1985-11-14 Lsi tester

Country Status (1)

Country Link
JP (1) JPS62115381A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6704897B1 (en) 2000-03-30 2004-03-09 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and the test system for the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6704897B1 (en) 2000-03-30 2004-03-09 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and the test system for the same

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