JPS62114240A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a fine semiconductor device having preferable characteristics by using a CVD oxide film formed on the sidewall of a capacitor electrode and a thermal oxide film formed on the upper surface as interlayer insulating films. CONSTITUTION:After a capacitor oxide film 23 is formed on an element region surrounded by a field oxide film 22 formed on a substrate 21, a first polycrystalline silicon film 24 is deposited, an impurity is doped, patterned to form a capacitor electrode 25 having a sidewall substantially perpendicular, and an unnecessary capacitor oxide film 23 is etched. Then, a CVD oxide film 26 to become an interlayer insulating film remains only on the sidewall of the electrode 25 by etching. Thereafter, a thermal oxide film 27 is formed, a gate oxide film 28 is formed by thermal oxidation for removing only a tin oxide film formed on the substrate 21, a second polycrystalline silicon film 29 is deposited, an impurity is doped, patterned to form a transfer gate electrode 30. With the electrodes 30, 25 and the film 22 as masks arsenic is ion implanted to form n<+> type source and drain regions 31, 32.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in a method for forming an interlayer insulating film between conductor layers formed in a stacked manner.

[Technical background of the invention]

8 on the semiconductor substrate! A method of manufacturing a semiconductor device having an i-layer conductor layer will be described using a dynamic RAM as an example with reference to FIGS. 2(a) to 2(l). Note that the cross sections of FIGS. 2(a) to (C) and the cross section of FIG. 2(d) are orthogonal to each other.

First, a field oxide film 2 is formed on the surface of a p-type silicon substrate 1 by selective oxidation, for example. Next, after forming a capacitor oxide film 3 on the surface of the element region surrounded by the field oxide film 2, a first polycrystalline silicon film 4 is deposited on the entire surface and doped with impurities (as shown in FIG. 2(a)). ). Then,
First polycrystalline silicon 1114 is patterned by anisotropic etching to form capacitor electrode 5, and unnecessary capacitor oxide film 3 is etched. This capacitor electrode 5 has substantially vertical side walls. Subsequently, thermal oxidation is carried out to form a thermal oxide film 6, which is an interlayer insulating film, on the surface of the capacitor electrode tj5, and only the thin oxide film formed on the surface of the substrate 1 is removed (as shown in FIG. 2('b)). Next, thermal oxidation is performed to form a gate oxide film 7 on the exposed surface of the substrate 1.
After forming a second polycrystalline silicon film 8, a second polycrystalline silicon film 8 is deposited on the entire surface and doped with an impurity (as shown in FIG. 3C). Then,
Transfer gate electrode 9 is formed by patterning second polycrystalline silicon film 8 by anisotropic etching. Next, using the transfer gate electrode 9, the capacitor electrode 5, and the field oxide film 2 as masks, ions of, for example, arsenic are implanted to form n+ type source and drain regions 10 and 11 (as shown in FIG. 3D). After depositing, for example, a CVD oxide film over the entire surface, a contact hole is formed by selectively etching a portion above the drain region. Subsequently, a wiring metal is deposited on the entire surface and then patterned to form a wiring 11 (bit I) to manufacture a dynamic RAM.

According to the method described above, it is possible to form the thermally oxidized layer 116, which becomes the interlayer insulating film on the capacitor electrode 5, in a self-lined manner without using a single lithography process.

[Problems with background technology]

However, in the conventional method, the thickness of the thermally oxidized layer 16 forming the interlayer insulating film formed in the step shown in FIG. 2(b) is influenced by the shape of the capacitor electrode 5 and is not uniform. That is, as shown in FIG. 3, the thickness of the thermal oxide film 6 becomes extremely thin, especially near the boundary with the field oxide film 2 on the side wall of the capacitor electrode 5 (the area surrounded by Q in the figure). In this way, an interlayer insulating film having a very thin part is formed on the capacitor electrode 5, and the transfer gate electrode 9 is further formed on it.
If this happens, problems such as a decrease in the dielectric strength of the interlayer insulating film and a short circuit between the capacitor electrode 5 and the transfer gate electrode 9 will occur.

These problems occur not only in the case of dynamic RAMs as described above, but also in interlayer insulating films of various semiconductor devices, such as interlayer insulating films between floating gates and control gates of EPROMs and EEPROMs.

[Purpose of the invention]

The present invention has been made in order to eliminate the above-mentioned drawbacks, and aims to provide a method for manufacturing a semiconductor device in which an interlayer insulating film can be formed using self-line, and in which defects such as a decrease in dielectric strength voltage and short circuits do not occur. It is.

[Summary of the invention]

In the method for manufacturing a semiconductor device of the present invention, a first
After depositing a conductor layer, patterning is performed to form a first conductor layer pattern having substantially vertical sidewalls; and after depositing an insulating film over the entire surface, etching is performed by anisotropic etching to form a first conductor layer pattern having substantially vertical sidewalls. A step of leaving an insulating film on the side wall of the conductor layer pattern, a step of forming an oxide film on the surface of the first conductor layer pattern, and a step of depositing a second conductor layer on the entire surface and then patterning it to form a second conductor layer. The method is characterized by comprising a step of forming a conductor layer pattern.

According to such a method, it is possible to form a sufficiently thick interlayer insulating film on any part of the side wall of the first conductor layer pattern using Selfa Line, which prevents a decrease in the withstand voltage of the interlayer insulating film and prevents No short circuit will occur.

(Embodiments of the Invention) Hereinafter, embodiments in which the method of the present invention is applied to the manufacture of a dynamic RAM will be described with reference to FIGS. 1(a) to (e).

Note that the cross sections of FIGS. 1(a) to (d) and the cross section of FIG. 1(e) are orthogonal to each other.

First, a field oxide film 22 is formed, for example, on the surface of a p-type silicon substrate 21 by selective oxidation.

Next, field oxidation 1! ! After forming a capacitor oxidation layer 123 on the surface of the element region surrounded by 22, a first polycrystalline silicon film 24 having a thickness of, for example, 4,000 wafers is deposited on the entire surface and doped with impurities (as shown in Fig. ψ (a)). ). Next, the first polycrystalline silicon film 24 is patterned by reactive ion etching (RIE) to form a capacitor electrode 25 having substantially vertical sidewalls, and unnecessary capacitor oxide film 23 is etched. Next, LPGVD
After depositing a CVD oxide film with a thickness of, for example, 1,500 yen on the entire surface using the CVDI method, etching is performed using RIE to form an interlayer insulating film only on the side walls of the capacitor electrode 25. I conversion 1
26 (as shown in FIG. 3(b)). Next, thermal oxidation is performed to form a thermal oxide film 27 serving as an interlayer insulating film on the side wall of the capacitor electrode 25, and only the thin oxide film formed on the surface of the substrate 21 is removed (as shown in FIG. 2C). Next, thermal oxidation is performed to form a gate oxide film 28 on the exposed surface of the substrate 21, and then a second polycrystalline silicon It!, for example, with a thickness of 4000 is applied to the entire surface. 29 and doped with impurities (as shown in FIG. 1). Next, the second polycrystalline silicon film 29 is patterned by RIE to form a transfer gate electrode 30. Next, transfer gate electrode 30, capacitor electrode 25, and field oxidation! By ion-implanting, for example, arsenic using 1122 as a mask, n+ type source and drain regions 31 and 32 are formed (as shown in FIG. 3(e)). Below, for example, CVD is applied to the entire surface.
After depositing the oxide film, a contact hole is formed by selectively etching the portion above the train region. Next, wiring metal is deposited on the entire surface and then patterned to form wiring (bit lines).

Manufactures dynamic RAM.

In the above method, the CVD oxidation 8!26 formed on the side wall of the capacitor electrode 25 in the step of FIG. 1(b) and the heat generated on the upper surface of the capacitor electrode 25 in the step of FIG. The oxide film 27 becomes a temporary insulating film. In other words, unlike the case of a conventional interlayer insulation film made of a thermal oxide film,
Sufficiently thick CVD oxide 18126 is formed at any position including the vicinity of field oxide film 22 on the sidewall of capacitor electrode 25.

Therefore, the dielectric strength of the interlayer insulating film can be improved, and the capacitor electrode 25 - transfer gate electrode 2
No short circuit occurs between the two. Further, since the interlayer insulating film can be formed by self-line without using lithography technology, there is no need to consider mask misalignment, etc., and it can be applied to even finer patterns.

In the above embodiment, after forming a CVD oxide film 1126 on the side wall of the capacitor electrode M in the process shown in FIG. , but this order may be reversed.

Further, in the above embodiment, the CVD oxide film 26 was used as the insulating film left on the side wall of the capacitor electrode 25, but the present invention is not limited to this, and other insulating films such as a silicon nitride film may be used.

Furthermore, in the above explanation, the interlayer insulating film between the capacitor electrode and the transfer 1 gate electrode of a dynamic RAM was described, but the method of the present invention can be applied to, for example, an EPROM or an EEPRO.
It goes without saying that the present invention can be similarly applied to the formation of interlayer insulating films of other semiconductor devices, such as interlayer insulating films between M(7)70-T'/gates and control gates.

〔Effect of the invention〕

As detailed above, according to the method of the present invention, it is possible to form an interlayer insulating film in a self-aligned manner without causing defects such as a decrease in dielectric strength voltage or short circuits, so that it is possible to manufacture fine semiconductor devices with good characteristics. It has a remarkable effect on Qin.

[Brief explanation of drawings]

1(a) to 1(e) are cross-sectional views showing a method of manufacturing a dynamic RAM according to an embodiment of the present invention, and FIG. 2(a)
-(d) are cross-sectional views showing a conventional method of manufacturing a dynamic RAM, and FIG. 3 is an explanatory diagram showing the drawbacks of the conventional method. 21... P-type silicon substrate, 22... Field oxide film, 23... Capacitor oxide film, 24... First polycrystalline silicon film, 25... Capacitor electrode, 26...
...CVD oxide film, 27...thermal oxide film, 28...gate oxide film, 29...second polycrystalline silicon film, 30
...Transfer gate electrode, 31.32...n"
type source, drain region.

Claims (1)

[Claims] After depositing a first conductor layer on a semiconductor substrate, patterning is performed to form a first conductor layer pattern having substantially vertical sidewalls; and after depositing an insulating film on the entire surface, etching is performed by anisotropic etching. and leaving an insulating film on the sidewalls of the first conductor layer pattern, forming an oxide film on the surface of the first conductor layer pattern, and depositing a second conductor layer on the entire surface, A method for manufacturing a semiconductor device, comprising the step of patterning to form a second conductor layer pattern.