JPS62111524A - Digital/analog converter - Google Patents
Digital/analog converterInfo
- Publication number
- JPS62111524A JPS62111524A JP25150785A JP25150785A JPS62111524A JP S62111524 A JPS62111524 A JP S62111524A JP 25150785 A JP25150785 A JP 25150785A JP 25150785 A JP25150785 A JP 25150785A JP S62111524 A JPS62111524 A JP S62111524A
- Authority
- JP
- Japan
- Prior art keywords
- output
- amplifier
- reference voltage
- voltage
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
Ｄ−Ａ変換器であって、公知の梯子形抵抗回路網と、オ
ペレーショナルアンプ（以下ＯＰアンプという）の非反
転端子に、同相の基準電圧を入力し、両方の出力を加算
して、反転入力のｏｐアンプに入力することにより、正
負何れかの基準電圧だけシフトしたユニポーラ出力が得
られる回路構成のＤ−Ａ変換器について開示されている
。[Detailed Description of the Invention] [Summary] This is a D-A converter, in which an in-phase reference voltage is input to the non-inverting terminals of a well-known ladder resistor network and an operational amplifier (hereinafter referred to as OP amplifier). A D-A converter having a circuit configuration is disclosed in which a unipolar output shifted by either a positive or negative reference voltage is obtained by adding both outputs and inputting the result to an inverting input op-amp.
本発明は、公知の荷重電流形の梯子形抵抗回路網を用い
たＤ−Ａ変換回路の改良に関するものであり、さらに詳
しくいえば、バイポーラ技術を使ったＩＣのＤ−Ａ変換
回路では、梯子形抵抗回路網から反転形ＯＰアンプ回路
を経て出力を得る方式が一般に用いられている。The present invention relates to an improvement in a D-A converter circuit using a known load current type ladder-shaped resistor network.More specifically, in an IC D-A converter circuit using bipolar technology, a ladder-type resistor network is used. A commonly used method is to obtain an output from a resistor network through an inverting OP amplifier circuit.
従って、出力電圧の極性は基準電圧の極性に対し反転す
るため、所要とする出力の極性に対応して、正負の二種
類の基準電圧が必要となるが、これを単一電源で可能と
したＤ−Ａ変換器に関するものである。Therefore, since the polarity of the output voltage is inverted with respect to the polarity of the reference voltage, two types of reference voltages, positive and negative, are required to correspond to the required output polarity, but this is possible with a single power supply. This relates to a DA converter.
第３図は公知の梯子形抵抗回路網を用いたＤ−Ａ変換回
路の原理的構成を示した図である。FIG. 3 is a diagram showing the basic configuration of a D-A conversion circuit using a known ladder-type resistor network.
梯子形抵抗回路網２と、反転入力のＯＰアンプ３の回路
で構成される従来形Ｄ−Ａ変換器の出力電圧は、その極
性が入力電圧と反転して現れＯＰアンプの一般式により
次の通りとなる。The output voltage of a conventional D-A converter consisting of a ladder resistor network 2 and an inverting input OP amplifier 3 has a polarity that is inverted with respect to the input voltage, and is expressed by the following general formula for an OP amplifier: It becomes a street.
Ｖｏ −−１ｏ Ｒ。Vo --1o R.
上式において、Ｖｏは出力電圧、ＩＯは梯子形抵抗回路
網２の内部抵抗と、ｏｐアンプ回路の抵抗ＲＯの回路に
、基準電圧を印加したときの電流である。In the above equation, Vo is the output voltage, and IO is the current when a reference voltage is applied to the internal resistance of the ladder resistor network 2 and the resistor RO of the op-amp circuit.
このように出力電圧の極性は、基準電圧が正のときは負
となり、また反対に基準電圧が負の時は正となる。なお
、ＲＯは○Ｐアンプのフィードパンク抵抗である。In this way, the polarity of the output voltage becomes negative when the reference voltage is positive, and, conversely, becomes positive when the reference voltage is negative. Note that RO is the feed puncture resistance of the ○P amplifier.
この従来方式では、正負いずれの極性を有する出力電圧
を必要とするかによって、正負の二種類の極性を有する
基準電源の準備が必要となり、正電源あるいは、負電源
だけては回路が構成ができないという問題点を有してい
る。In this conventional method, it is necessary to prepare a reference power supply with two types of polarity, positive and negative, depending on which output voltage is required, and the circuit cannot be configured with only a positive power supply or a negative power supply. There is a problem with this.
本発明は、かかる問題点を解消して、正電源または負電
源の何れかの単一電源で回路を構成しようとするもので
ある。The present invention aims to solve these problems and configure a circuit using a single power source, either a positive power source or a negative power source.
第１図は本発明のＤ−Ａ変換器の原理構成図を示す。 FIG. 1 shows a basic configuration diagram of a D-A converter according to the present invention.
第１図において１は、非反転入力の○Ｐアンプであり、
２は梯子形抵抗回路網であって基準電圧の入力端子２１
、ディジタル端子２２を有しており、また、出力端子２
３からは梯子形抵抗回路網２の出力が得られる。In FIG. 1, 1 is a non-inverting input ○P amplifier,
2 is a ladder-type resistor network with a reference voltage input terminal 21;
, has a digital terminal 22, and also has an output terminal 2
3 provides the output of the resistor ladder network 2.
３は反転入力のＯＰアンプであって、反転入力端子に梯
子形抵抗回路網２の出力が入力されており、非反転入力
端子側には、ＯＰアンプ１の出力が入力加算回路４で加
算される接続である。3 is an OP amplifier with an inverting input, the output of the ladder resistor network 2 is input to the inverting input terminal, and the output of the OP amplifier 1 is added to the non-inverting input terminal by an input adding circuit 4. This is a connection.
なお５は回路に印加する基準電圧であり、該梯子形抵抗
回路網２と、ＯＰアンプ１に基準電圧が供給される。Note that 5 is a reference voltage applied to the circuit, and the reference voltage is supplied to the ladder-shaped resistance network 2 and the OP amplifier 1.
このような回路構成により、前記の問題点を解決したＤ
−Ａ変換器が得られる。With such a circuit configuration, the D
-A converter is obtained.
ディジタル信号が、ディジタル端子２２６ご入力され、
梯子形抵抗回路網２が作動し、端子２１に印加された基
準電圧５が制御され１．出力端子２３に電）流出力が得
られる。A digital signal is input to the digital terminal 226,
The resistor ladder network 2 is activated and the reference voltage 5 applied to the terminal 21 is controlled such that 1. A current output is obtained at the output terminal 23.
一方、同相の基準電圧が印加された、ＯＰアンプ１の出
力は、該抵抗回路網２の出力と人力加算回路４で加算さ
れ、ＯＰアンプ３に入力される。On the other hand, the output of the OP amplifier 1 to which the in-phase reference voltage is applied is added to the output of the resistor network 2 by a manual adding circuit 4, and is input to the OP amplifier 3.
これにより基準電圧５を最大とした、出力電圧Ｖ ｏｕ
ｔがＯＰアンプ３の出力として得られる。This makes the reference voltage 5 the maximum, and the output voltage V ou
t is obtained as the output of the OP amplifier 3.
第２図は本発明の実施例の回路図であって、第３図に示
した従来の梯子形抵抗回路網を用いたＤ−Ａ変換器に、
非反転入力のＯＰアンプ１の回路と、入力加算回路４が
追加されて構成された本発明の回路である。FIG. 2 is a circuit diagram of an embodiment of the present invention, in which the D-A converter using the conventional ladder resistor network shown in FIG.
This is a circuit of the present invention which is configured by adding an OP amplifier 1 circuit with a non-inverting input and an input adder circuit 4.
Ｖｒ基準電圧５が梯子形抵抗回路網２に印加され、ディ
ジタル信号により制御され、該梯子形抵抗回路網２の出
力となり、○Ｐアンプ３に入力される。A Vr reference voltage 5 is applied to the ladder resistor network 2, controlled by a digital signal, becomes the output of the ladder resistor network 2, and is input to the OP amplifier 3.
ＯＰアンプ３の出力電圧はＯＰアンプの原理により次式
で示される。The output voltage of the OP amplifier 3 is expressed by the following equation based on the principle of an OP amplifier.
Ｖｏ −ｍ−１ｏ Ｒｏ ＝ −（ｘ／Ｘ−Ｒｏ ／Ｒ
） Ｖ ｒ上式のＶＯはＯＰア；／ブ３の出力電圧、Ｉ
ｏは回路の電流であり、梯子形抵抗回路網２の内部抵抗
（Ｘ／ｘ）Ｒと、基準電圧（Ｖｒ）５により求められる
回路の電流である。Vo −m−1o Ro = −(x/X−Ro /R
) V rIn the above equation, VO is the output voltage of OP A;/B3, I
o is a circuit current, which is determined by the internal resistance (X/x)R of the ladder-shaped resistance network 2 and the reference voltage (Vr) 5.
また、Ｘは２’、ｘはＯ〜２″刊であり、ここにｎはビ
ット数である。ＲｏはＯＰアンプのフィードバンク抵抗
である。Further, X is 2', x is O~2'', where n is the number of bits. Ro is the feed bank resistance of the OP amplifier.
また、第２図（ａ）点の○Ｐアンプ１の出力電圧は上記
と同様の理論から得られるが、該ＯＰアンプ１の人力抵
抗Ｒ２の端子間電圧が加算されるので次式に示す値とな
る。In addition, the output voltage of the ○P amplifier 1 at point (a) in Figure 2 can be obtained from the same theory as above, but since the voltage between the terminals of the human resistor R2 of the OP amplifier 1 is added, the value shown in the following equation is obtained. becomes.
Ｖａ ＝（１＋ Ｒｒ ／ Ｒｚ ） Ｖｒ上
式において、Ｖａは第２図（８１点の電圧、Ｖｒは基準
電圧５、Ｒ，はＯＰアンプｌのフィードバック抵抗、Ｒ
２はＯＰアンプｌの入力抵抗である。Va = (1+ Rr / Rz) Vr In the above equation, Va is the voltage at 81 points in Figure 2 (the voltage at 81 points, Vr is the reference voltage 5, R is the feedback resistance of the OP amplifier I, R
2 is the input resistance of the OP amplifier l.
従って、ＯＰアンプ３の総合出力電圧Ｖ。ｕＬは、前記
の式の総和となり、次式が成立する。Therefore, the total output voltage V of the OP amplifier 3. uL is the sum of the above equations, and the following equation holds true.
Ｖｏｕｔ ＝ （１＋Ｒ＋／Ｒｚ（２＋ｘ／Ｘ）Ｒ
ｏ／Ｒ） ＶｒＸ ＝２’ 、 ｘ＝Ｑ〜２ｆｉ−
１、ｎはビット数、Ｘはディジタル入力により変化する
値である。Vout = (1+R+/Rz(2+x/X)R
o/R) VrX =2', x=Q~2fi-
1 and n are the number of bits, and X is a value that changes depending on the digital input.
いま、仮にフィードバック抵抗Ｒｏと、梯子形抵抗回路
網２の内部抵抗Ｒを同一値とし、基準電圧（Ｖｒ） ５
を５ボルトとすると総合出力電圧Ｖ。ａｔは上記の式よ
り、Ｏ〜４．９８ボルトが得られ、約基準電圧５ボルト
だけシフトした出力が得られる。Now, suppose that the feedback resistor Ro and the internal resistance R of the ladder resistor network 2 are the same value, and the reference voltage (Vr) 5
If is 5 volts, the total output voltage is V. From the above equation, at is obtained as O~4.98 volts, and an output shifted by approximately 5 volts from the reference voltage is obtained.
以上のように、本発明のＤ−Ａ変換器の回路構成では基
準電圧５だけシフトしたユニポーラ出力が得られ、かつ
正電源または、負電源だけの単一電源により動作が可能
となる梯子形抵抗回路網を用いたＤ−Ａ変換器が製作で
きる。As described above, in the circuit configuration of the D-A converter of the present invention, a unipolar output shifted by the reference voltage 5 can be obtained, and the ladder-shaped resistor can be operated with a single power supply of only a positive power supply or a negative power supply. A D-A converter using a circuit network can be manufactured.
以上述べてきたように、本発明によれば、極めて簡易な
回路構成で、極性が正負いずれかの単一電源を用いるこ
とにより、基準電圧だけシフトしたユニポーラ出力のＤ
−Ａ変換器を製作することができ、実用的には掻めて有
用である。As described above, according to the present invention, by using a single power supply with either positive or negative polarity with an extremely simple circuit configuration, a unipolar output D shifted by the reference voltage can be generated.
-A converter can be manufactured and is extremely useful in practical terms.
第１図は本発明のＤ−Ａ変換器の原理構成図、第２図は
本発明の実施例を示す回路図、第３図は従来のＤ−Ａ変
換器の原理構成図である。
第１図、第２図、において、
１は非反転入力のＯＰアンプ、
２は梯子形抵抗回路網、
３は反転入力のＯＰアンプ、
４は入力加算回路である。
第 ２ 図
２８柑ネ抗団路Ｊ
ｆ／ｌ０−Ａ９４１１−＋）ｊＢｒ＃ｓ：ｍ第３囚FIG. 1 is a diagram showing the principle configuration of a D-A converter according to the present invention, FIG. 2 is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is a diagram showing the principle configuration of a conventional DA converter. In FIGS. 1 and 2, 1 is an OP amplifier with a non-inverting input, 2 is a ladder resistor network, 3 is an OP amplifier with an inverting input, and 4 is an input addition circuit. 2nd Figure 28 Kannehandanro J f/l0-A9411-+)jBr#s:m3rd Prisoner
Claims (1)
抗回路網（２）の出力を、オペレーショナルアンプ（３
）に反転入力するＤ−Ａ変換回路において、該基準電圧
（５）と同相の電圧を、オペレーショナルアンプ（１）
に非反転入力し、その出力を該オペレーショナルアンプ
（３）の非反転入力端子に、入力加算回路（４）で加算
し、 当該オペレーショナルアンプ（３）の出力が加算された
電圧との和となる回路構成により、 正負いずれかの基準電圧（５）だけシフトした出力が得
られることを特徴としたＤ−Ａ変換器。[Claims] The output of the ladder resistor network (2) whose reference voltage (5) is controlled by a digital signal is connected to the operational amplifier (3
), a voltage in phase with the reference voltage (5) is input to the operational amplifier (1).
The output is added to the non-inverting input terminal of the operational amplifier (3) by the input adder circuit (4), and the output of the operational amplifier (3) becomes the sum of the added voltage. A DA converter characterized in that, depending on the circuit configuration, an output shifted by either a positive or negative reference voltage (5) can be obtained.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25150785A JPS62111524A (en) | 1985-11-08 | 1985-11-08 | Digital/analog converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25150785A JPS62111524A (en) | 1985-11-08 | 1985-11-08 | Digital/analog converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62111524A true JPS62111524A (en) | 1987-05-22 |
Family
ID=17223837
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25150785A Pending JPS62111524A (en) | 1985-11-08 | 1985-11-08 | Digital/analog converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62111524A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6473829A (en) * | 1987-09-14 | 1989-03-20 | Seiko Epson Corp | Digital-analog converter |
| JPH0365087A (en) * | 1989-07-31 | 1991-03-20 | Gold Star Co Ltd | Speed control circuit of servo motor |
| JPH11122109A (en) * | 1997-10-09 | 1999-04-30 | Toshiba Corp | Semiconductor integrated circuit and semiconductor memory |
-
1985
- 1985-11-08 JP JP25150785A patent/JPS62111524A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6473829A (en) * | 1987-09-14 | 1989-03-20 | Seiko Epson Corp | Digital-analog converter |
| JPH0365087A (en) * | 1989-07-31 | 1991-03-20 | Gold Star Co Ltd | Speed control circuit of servo motor |
| JPH11122109A (en) * | 1997-10-09 | 1999-04-30 | Toshiba Corp | Semiconductor integrated circuit and semiconductor memory |
| KR100335033B1 (en) * | 1997-10-09 | 2002-09-27 | 가부시끼가이샤 도시바 | Semiconductor integrated circuit and semiconductor memory |
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