JPH0786848A - Signal output circuit - Google Patents

Abstract

PURPOSE:To provide complementary output signals whose center level is a reference voltage at all times even when the size of analog output signals per bit is changed by adjusting the input reference voltage of a digital/analog converter(DAC). CONSTITUTION:The output terminal of the DAC 10 for converting digital signals to complementary analog signals is connected respectively to one end of the first pair of resistors 68 and 70 whose other ends are mutually connected and one end of the second pair of the resistors 72 and 74 whose other ends are mutually connected for which a resistance value is drastically larger than the first pair of the resistors. The inverted input terminal of an operational amplifier 76 is connected to the mutual connection point of the first pair of the resistors 68 and 70 and a noninverted input terminal is connected to a reference voltage source. The first pair of the resistors 68 and 70 detects a complementary output voltage, the sum is turned to a reference potential by the operation of the operational amplifier 76 or the like and thus, the potential of the mutual connection voltage of the second pair of the resistors 72 and 74 is adjusted so as to let the complementary output voltage change with the reference voltage as a center. Thus, the complementary output signals whose center level is not changed even when the input reference voltage of the DAC 10 is adjusted can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal output circuit used in a complementary signal generating circuit.

[0002]

2. Description of the Related Art There are many types of digital-to-analog converters (hereinafter referred to as DACs) widely used in electronic equipment according to their applications, but those capable of converting an input digital signal into two complementary analog signals. Complementary output type DAC
There is. Such a DAC is, for example, sold by Triquinto as a model TQ6122.

FIG. 2 shows a conventional signal output circuit including a complementary output type DAC 10 and an output circuit related thereto. D
The AC 10 has a positive terminal which is grounded in common and always flows to the ground potential, and a current source 14 and a current source 14 which respectively output currents I 1 and I 2 which complementarily change in accordance with the value of an input digital signal supplied to a digital input terminal 12. Have 16. The currents I1 and I2 have a constant sum, and are represented by currents i + ic and -i + ic, respectively, which are currents i and -i that change in opposite polarities with respect to the same DC current level ic. In addition, the current change corresponding to 1 bit of the input digital signal is DA
It is determined by the input reference voltage supplied to the reference input terminal 13 of C10. One ends of the negative terminals of the current sources 14 and 16 are commonly connected and grounded, and the resistors 1 having the same resistance value r are provided.
It is connected to the other ends of 8 and 20, respectively. Resistors 18 and 2
The other end of 0 is connected to output terminals 26 and 28 via transmission lines 22 and 24, respectively. The output terminal 26 is a resistor 3
0 is connected to the voltage source Vs, and the output terminal 28 is connected to the voltage source Vs via the resistor 34. Resistor 30
And 34 are termination resistors, which are resistors 1 in the DAC 10.
It has a resistance r equal to 8 and 20.

Since the currents flowing through the current sources 14 and 16 are always unidirectional from 0 to the maximum value, the output voltage is 0.
In order to change the bolt as the center level, the resistor 3
0 and the voltage Vs supplied to the resistor 34 are selected to appropriate values. For example, when the sum of the currents I1 and I2 is 80 mA and the resistance value r of the resistors 30 and 34 is 50 ohms, the voltage Vs
= + 2 volts, the output voltages V1 and V2 generated at the output terminals 26 and 28 will be centered around 0 volts +
It varies from 1 to -1 volt.

[0005]

The DAC 10 shown in FIG.
Then, the output voltage per bit of the input digital signal changes according to the input reference voltage. Therefore, if the input reference voltage is adjusted so that the amplitude of the output voltage for the same input digital signal becomes 3 volts, the output voltage will increase from +1 to
It starts to change in the range of -2 volts and stops changing around 0 volt.

FIG. 3 shows a signal output circuit which can be considered to make up for the drawbacks of the signal output circuit of FIG. In addition to the configuration of FIG. 1, this circuit includes a buffer amplifier circuit including operational amplifiers 38 and 40 connected to the output terminals of the circuit of FIG. 1, an operational amplifier 42 and resistors 44, 46, 48 and 50. And a subtraction circuit. This subtraction circuit subtracts the output voltage V2 from the output voltage V1. The AC component of the output voltage V1 is v1
Then, the AC component of the output voltage V2 is −v1 and the DC components of both output voltages are equal, so the output voltage of the subtractor is 2
It becomes v1, and the output voltage is 0 regardless of the change of the reference voltage.
It changes around the bolt. However, in the DAC of FIG. 3, a complementary output signal is not obtained, and the use of a subtraction circuit in addition to the output buffer amplifier suppresses high frequency operation.

Therefore, an object of the present invention is to provide a signal output circuit which can obtain a complementary output signal whose center level does not change even if the input reference voltage of the DAC is adjusted.

[0008]

In the signal output circuit of the present invention, a DA for converting a digital signal into a complementary analog signal is used.
The output end of C is connected to each of the other ends of the first pair of resistors whose one ends are interconnected, and to the other ends of the second pair of resistors whose one ends are interconnected. The resistance value of the first pair of resistors is
It is significantly larger than the resistance value of the second pair of resistors. The inverting input terminal of the operational amplifier is connected to the interconnection point of the first pair of resistors, and the non-inverting input terminal is connected to the reference voltage source.

[0009]

The first pair of resistors detect the complementary output voltage, and the operation of the operational amplifier or the like causes the sum thereof to become the reference potential, so that the complementary output voltage changes around the reference voltage. The potential of the interconnection voltage of the second pair of resistors is adjusted. Therefore, even if the input reference voltage of the DAC is adjusted, a complementary output signal whose center level does not change can be obtained.

[0010]

1 is a circuit diagram showing a signal output circuit of the present invention. The signal output circuit of the present invention has the same DAC 10 as shown in FIG. Although description of the internal configuration of the DAC 10 is omitted, the DAC 10 outputs complementary current signals I1 ′ and I2 ′ according to the input digital signal supplied to the digital signal input terminal 60, as described above. The output current corresponding to 1 bit of the input digital signal is determined by the input reference voltage supplied to the reference input terminal 62. Since the output signal of the DAC 10 is a wideband signal, it is supplied to one end of resistors 68 and 70 via transmission lines 64 and 66 such as strip lines, respectively. The other ends of the resistors 68 and 70 are connected to each other. The resistors 68 and 70 have a relatively large resistance value of, for example, 10 kΩ. One end of the resistors 72 and 74 has a resistor 6
Each of 8 and 70 is connected to one end and the other ends are connected to each other. Resistors 72 and 74 are termination resistors and
Having a resistance value r equal to resistors 18 and 20 in 10,
For example, r has a relatively low resistance value of 50 ohms.

The inverting input terminal of the operational amplifier 76 is connected to the interconnection point of the resistors 68 and 70, and the non-inverting input terminal is connected to the ground potential source which is the reference potential source. However, the reference potential source is not limited to the ground potential. The output terminal of the operational amplifier 76 is connected to the base of the transistor 78. The collector of transistor 78 is supplied with the appropriate voltage V and the emitter is connected to the interconnection point of resistors 72 and 74. Thus, with respect to the operational amplifier 76, a negative feedback path formed by the transistor 78 and the resistors 72 and 68 and a negative feedback path formed by the transistor 78 and the resistors 74 and 70 are formed. One ends of the resistors 72 and 74 are connected to the input ends of the buffer amplifiers 80 and 82, respectively. The output signals of the buffer amplifiers 80 and 82 are output to the output terminals 84 and 8.
It is output via 6.

The resistance value of the resistors 68 and 70 is equal to that of the resistor 72.
And the resistance value of 74 is much larger, the current I
1'and I2 'substantially flow through resistors 72 and 74, respectively. Currents I1 'and I flowing through resistors 72 and 74, respectively
2 ′ is supplied from the transistor 78. As described with reference to FIG. 2, the currents I1 and I2 are composed of currents i and -i that change in opposite polarities with respect to the same DC current level ic, and are represented by I1 = i + ic, I2 = -i + ic. To be done. The resistors 18 and 20 have the same resistance value as the resistors 72 and 74, respectively. Here, if the emitter voltage of the transistor 78 is VE, the voltage V1 'at the common connection point of the resistors 68 and 72 and the voltage V2' at the common connection point of the resistors 70 and 74 are expressed as follows. It V1 '= (1/2). (VE-r (i + ic)) = (1/2). (-R.i + (VE-r.ic)) ... (1) V2' = (1/2 ). (VE-r (-i + ic)) = (1/2). (R.i + (VE-r.ic)) (2)

As described above, the operational amplifier 76, the transistor 78, and the resistors 68, 70, 72, 74 form a negative feedback amplifier, and the non-inverting input terminal of the operational amplifier 76 is grounded. Inverting terminal or resistor 68
The voltage Vc at the connection point of 70 and 70 is 0 volt. on the other hand,
When the voltage Vc is obtained from the voltages V1 'and V2' of both ends of the resistors 68 and 70, the resistance values of the resistors 68 and 70 are equal, and the following is obtained. Vc = (1/2). (V1 '+ V2') = (1/2). (VE-r.ic) (3) Since Vc is 0 volt, (VE-r.ic) = 0 ... (4) Substituting equation (4) into equations (1) and (2), V1 '= (1/2) .multidot.r.multidot.i ... (5) V2' = (1 / 2) · r · i (6) As is clear from the equations (5) and (6), the voltage V
1'and V2 'are complementary signal voltages that constantly change centered around 0 volt regardless of the input reference voltage of the DAC, and are output from output terminals 84 and 86 via buffer amplifiers 80 and 82, respectively. In this way, the output voltage of DAC 10 is 0
Since it changes around the volt, the subtraction circuit as shown in FIG. 2 is not required in the output stage, and the adverse effect on the high frequency characteristic can be minimized.

The preferred embodiment of the present invention has been described above, but it will be apparent to those skilled in the art that various modifications can be made. For example, if the output current of the operational amplifier 76 is sufficient, the transistor 78 may be omitted and the output end of the operational amplifier 76 may be directly connected to the interconnection point of the resistors 72 and 74. Also,

[0015]

According to the signal output circuit of the present invention, the DAC
Even if the input reference voltage of is adjusted, a complementary output signal whose center level does not change can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a signal output circuit of the present invention.

FIG. 2 is a circuit diagram showing a conventional signal output circuit.

FIG. 3 is a circuit diagram showing a conventional signal output circuit.

[Explanation of symbols]

 10 Digital-to-analog converter 68, 70 First pair of resistors 72, 74 Second pair of resistors 76 Operational amplifier

Claims (1)

[Claims] 1. A signal generator for generating a complementary analog signal having a variable reference level from a pair of output terminals, one end of which is interconnected and the other end of which is the signal generating circuit.
A first pair of resistors connected to the output ends of the pair and a second pair of resistors having one end interconnected and the other end connected to the other end of the first pair of resistors, respectively. An operational amplifier having an input terminal connected to the interconnection point of the first pair of resistors, a non-inverting input terminal connected to the reference voltage source, and an output terminal connected to the interconnection point of the second pair of resistors. And a signal output circuit which obtains an output signal from the other end of the second pair of resistors.