JPS6211052Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a display circuit in an electronically tuned radio receiver using a PLL synthesizer, and allows the reception frequency to be easily displayed.

An example of this will be described below with reference to the drawings.
A PLL circuit is configured by a reference oscillator 1, a phase comparator 2, a low-pass filter 3, a voltage variable oscillator (VCO) 4, and a frequency divider 5, and the division ratio of the frequency divider 5 is sequentially switched by a counter 6. By searching for reception frequencies, broadcasts of desired frequencies can be received.

On the other hand, the contents of the counter 6 are converted into decimal by the drive circuit 7.
The display can be performed by supplying the signal to the display section 8 through the display section 8.

Here, the receive channel separation Δ is 10
In the case of ×10 ^N KHz (an integer of N...), for example, the displayed value may change in the order of "102.3", "102.4", "102.5", etc., so 4 digits (5 digits if the decimal point is regarded as 1 digit) are sufficient. , if Δ is 5×10 ^N KHz, it must be 5 digits (or 6 digits). If 4
If you try to use only 5 digits, "102.3" will be displayed even if "102.35" is normal.

On the other hand, if "102.35" is to be displayed with the same display configuration as "102.3", the cost will be high.

Therefore, the present invention focuses on the fact that the second significant figure after the decimal point ("5" in the above example) cannot be a number other than "5". In other words, while the other digits display "0 to 9" even with multiple display elements, the second decimal place displays "0 to 9" with fewer elements or even one element, which is smaller than the other digits. A display element 81 that displays "5" [or "・"] is made to the right of the lowest decimal display (the first digit after the decimal point), and it also indicates whether the receiving frequency is an even multiple or an odd multiple of Δ. Judgment means 61 for judging
Further, a drive circuit 71 is provided which causes the display element 81 to display "5" when an odd value determination output is received from the determination means 61.

Therefore, while the received frequency can be displayed in the form of 102.3 or 102.3 102.3 ₅ 102.3, 102.4 102.4 102.4 ₅ 102.4, 〓,
Since "5" or "." can be formed with fewer display elements than other digits, the display section 8 itself requires less cost increase.

Also, if Δ is 10×10 ^N KHz, the display element 8
1 is no longer necessary, but if the area where Δ is 10×10 ^N KHz and 5×10 ^N KHz are also used, it is possible to perform a display according to the Δ, which is advantageous.

[Brief explanation of the drawing]

The drawing is a block diagram of a display device in an electronically tuned radio according to an embodiment of the present invention. 5... Frequency divider, 6... Counter, 7... Decimal conversion drive circuit, 8... Display section, 61... Judgment means,
71...Drive circuit, 81...Display element.

Claims (1)

[Scope of utility model registration request] A counter sets the frequency division ratio of the frequency divider of the PLL circuit, and the count value of this counter determines the number of reception frequency breaks equal to channel separation Δ(5×10 ^N KHz, N
...an integer); a display unit that displays a decimal number and has an additional display element on the right side of the lowest digit that is smaller in shape than the decimal display digit; A display device for an electronically tuned radio, comprising a drive circuit that lights up the additional display element when it is determined that the display is doubled.