JPS62110326A - Adaptive delta modulator-demodulator - Google Patents

Abstract

PURPOSE:To prevent the signal error and to simplify a circuit generating a control signal at a prescribed period by applying either up-control or down- control to an up-down counter based on a data stored in a shift register and connecting the circuit generating the control signal with a prescribed period independently of the data in the shift register for the other control. CONSTITUTION:A down-control signal generating circuit generates a down signal independently of an up-down counter control circuit 3. When an up-signal 37 has priority while an up-down counter 4 gives a minimum value, it is required to stop a down signal 91 when the up signal 37 is generated. Then a NOR gate 901, an OR gate 902 and an inverting gate 903 are combined with a down- control signal generating circuit 9, and the final down signal 92 is fed to the up-down counter 4. The down signal is generated by the down control signal generating circuit 9.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention converts an analog signal into a 1-bit digital signal.
This invention relates to a control circuit that determines the quantization step amount of an adaptive delta modulator/demodulator that converts a bit digital signal into an analog signal.

Conventional delta modulator/demodulators are used in many fields including telephones because their circuits are simple and can be realized at low cost. However, when the analog input signal changes rapidly, the modulation cannot follow it with a fixed quantization step amount, resulting in overload distortion. Increasing the quantization step size can reduce overload distortion, but on the other hand, quantization noise increases. In order to reduce overload distortion and quantization noise, the amount of quantization steps is often controlled in response to changes in the input signal. This is called an adaptive delta modulation/demodulation method, and various algorithms and modulation/demodulators that embody these algorithms have been realized.

FIG. 4 shows a block diagram of a conventional adaptive delta modulator. Comparator 1 compares the analog input signal input to input terminal 11 and the delta modulation feedback signal input to input terminal 12, and logically calculates °' depending on the magnitude of the two signals.
Outputs a 1" or 0" digital signal. This comparator 1 outputs °(11ff, It □
The digital value of 11 is analog-digital conversion (hereinafter A/
At the same time, it is taken into the shift register 2 having a storage capacity of n bits in synchronization with the output clock (CK1) 81 from the clock generation circuit 8.

From the shift register 2, a total of 2n bits, which is an n-bit stored value and a logically inverted value of the stored value, is input to an up/down counter control circuit (hereinafter abbreviated as control circuit) 3. The control circuit 3 receives 2n-bit input data from the shift register 2 and an up/down counter (hereinafter referred to as
It is abbreviated as counter. ) 4 outputs a clock (CK
2) Output a control signal to increase or decrease the value of the counter 4 in synchronization with 82.

FIG. 6 shows a circuit showing the correlation among the 4-bit shift register 2, control circuit 3, counter 4, and clock generation circuit 8. Shift register 2 is current comparator 1
The output value Q. and the values Q, ~Q, from 1 to 3 clocks ago are stored. The 4-bit value stored in shift register 2 is H.
The 4-bit logically inverted output of the stored value is input to an AND gate 301 and output to a HAND gate 302. Both NA
Outputs 31 and 32 of the ND gates 301 and 302 are output to an AND gate 303. AND game) 303 output 3
3 becomes ``0'' when all four pins of the values stored in the shift register are logically equal, and becomes ``1'' when any one of them is different. The output 33 of the AND gate 303 is input to the OR gate 306 and is also input to the inverting gate 3o.
4 to the OR gate 306. Both OR gates 3o5゜306 generate a signal 3 that increases the value of the counter 4 when all the values stored in the shift register 2 are equal.
A signal 38 is output to bring down when 7 is not equal.

FIG. 6 shows a timing chart. In this example, the output value of the counter 4 is changed upward or downward at the rising edge of the up or down signal. Counter 4 in this example has a 3-bit output, and A is M
SB and C are LSB. The output ABC of the counter 4 is output from the AND gate 3o7 and the NOR gate 30 of the control circuit 3.
8 is input. When ABC is all tll 1 n, A
Since the ND gate 307 outputs 1'', the OR gate 305 becomes 1'' in any state, and the counter 4
The up signal 37 that raises the signal stops.

When ABC is still all Te'to11, NOR gate 308
Since outputs 1'', the OR gate 3o6 becomes 1'' in any state, and the DOW/signal 38 stops.

Further, the m-bit linear digital-to-analog converter 6, which is a quantization step amount determination circuit, linearly performs D/M conversion on the m-bit output of the counter 4, and determines the quantization step amount as a voltage value. The quantization step amount is input to the positive/negative pulse generator 6.

The output value 13 of the comparator 1 is passed through a non-inverter 601 and an inverter 602 to a switch 603. This is a control signal for turning on (ON) and off (OFF) the switch 604. When the switches 603 and 604 are turned on, the voltage value of the quantization step amount is changed to the resistor 6o5. Operational amplifier 60 via resistor 608
9, and finally a positive/negative pulse whose quantization step amount changes in synchronization with the clock (GKl) of the clock generating circuit 8 is outputted to the input terminal 71 of the integrator 71. The integrator 7 inputs the input positive and negative pulses to a capacitor 7o1. Resistance 702.703. It is integrated by an operational amplifier 704 and demodulated into an analog signal.

The demodulated analog signal is applied to one input terminal 12 of the comparator 1 as a delta modulated feedback signal.

The adaptive delta demodulator is obtained by removing the comparator 1 from the modulator shown in FIG. 4, and is realized by directly inputting the digital output of the modulator to the shift register 2.

The output of the integrator 7 becomes the analog output signal of the demodulator.

Problems to be Solved by the Invention In this way, in the conventional circuit, the up/down counter 4
The up or down control of the shift register 2 is determined only by the data stored in the shift register 2. In other words, except when the outputs of counter 4 are all "1, 9 or 0", when all the data in shift register 2 are equal, up control is applied; otherwise, down control is always applied to counter 4. It turns out. This type of control works to minimize the quantization step amount, so it has the advantage of reducing quantization noise.

On the other hand, when the analog input signal changes sharply, it is difficult to drastically change the quantization step amount. Furthermore, when the digital data is continuously 1'' and the signal is changing rapidly, the shift register 2 may be affected by noise etc.
” is stored incorrectly, this error means that not only will it not be possible to issue an up control signal as many times as the number of memories in shift register 2, but on the contrary, a down control signal will not be issued to reduce the quantization step amount. This has the disadvantage that a small error can result in a large error, as it ends up creating the same number of times as there is memory.

Means for Solving the Problems In order to solve the above problems, the present invention controls only one of the up and down controls of the up-down/counter based on the data stored in the shift register,
The other end is connected to a circuit that generates a control signal at a constant cycle regardless of the data in the shift register.

Effect of the present invention With the above-described configuration, for example, when up control is controlled based on data stored in a shift register, by lengthening the period of the signal generated by the circuit that generates the signal for performing down control. It is possible to rapidly realize a large quantization step amount that follows even a steep analog input signal. Quantization noise can be reduced by shortening the period υ, and it is also easy to control the length and shortness of the period, so depending on the signal handled by the system, signal followability and quantization noise can be reduced. It is possible to set a balance between the two. In addition, erroneous accumulation of data in the shift register due to noise or the like only affects up control and is unrelated to down control, so errors can be small.

Embodiment FIG. 1 is a block diagram showing an embodiment of an adaptive delta modulator including a control circuit for determining the amount of quantization steps according to the present invention. In FIG. 1, a comparator 1, a shift register 2, an up/down counter 4, a digital-to-analog converter 6, a positive/negative pulse generator 6, an integrator 7, and a clock generator 8 are the same as those of the conventional example shown in FIG. It further includes a down control signal generation circuit 9. The down control signal generation circuit generates the down signal 91 regardless of the up/down counter control circuit 3. However, it is necessary to stop the down signal 91 when the up/down counter 4 is at the lowest value and when the up signal 37 is being generated if priority is given to the up signal 37. Therefore, NOR gate 901, OR gate) 902. The inverting gate 903 is combined with the down control signal generation circuit 9 and the final down signal 92 is applied to the up/down counter 4.

FIG. 3 shows a second embodiment in which an up signal is applied to the up/down counter 4 at regular intervals.

It has the same configuration as the first embodiment, and while the first embodiment generates the down signal by the down control signal generation circuit 9, the second embodiment generates the up signal by the up control signal generation circuit. 9' periodically to increase the value of the up/down counter 4. The down signal is sent to the sixth up/down counter control circuit 3.
It is made as shown in the figure.

Effects of the Invention As described above, according to the present invention, the adaptive quantization step amount of the adaptive delta modulator/demodulator can be changed rapidly or slowly according to the type of signal handled with a simple circuit configuration. It is.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an adaptive delta modulator/demodulator circuit according to a first embodiment of the present invention, and FIG. 2 is a timing chart showing the relationship between input and output to an up-down counter in the first embodiment. , FIG. 3 is a block diagram showing another embodiment of the present invention, FIG. 4 is a block diagram showing a conventional adaptive delta modulator/demodulator, and FIG. 6 is a block diagram showing a shift register 2, an up-down counter, and an up-down counter. A block diagram showing the relationship with the control unit, Figure 6 is a conventional adaptive delta variable
3 is a timing chart showing the relationship between input and output to an up-down counter of a demodulator. 1... Comparator, 2... Shift register, 3... Up/down counter control circuit, 4... Up/down counter, 6...
... m-bit digital analog converter, 6...
・Positive/negative pulse generator, 7...Integrator, 8...
. . . Clock generation circuit, 9 . . . Down control signal generation circuit, 9' . . . Up control signal generation circuit.

Claims (1)

[Claims] A delta modulator/demodulator compares the input analog signal and the integrator output signal bit by bit, and generates a "1" or "0" depending on whether the error sign is positive or negative. A circuit that increases or decreases the quantization step amount based on a finite number of continuous digital signal data of 1 or 0, and a circuit that decreases or increases the quantization step amount at a constant cycle regardless of the digital signal data. An adaptive delta modulator/demodulator that is characterized by having both of the following.