JPS62110173A - Semiconductive integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the time and cost required in the formation of a test pattern, by changing over a external input signal and the output signal of a combined circuit part to connect the same to the input terminal of a sequence circuit part and changing over the output signal of the sequence circuit part and the output signal of the combined circuit to output the same to the outside. CONSTITUTION:In a semiconductive integrated circuit containing a sequence circuit part 2 and a combined circuit part 1, two transfer gates constituted of FETQ1, Q2 and FETQ3, Q4 are provided to an input buffer gate 3 and an external input signal and the output signal of the circuit part 1 are changed over to be connected to the input terminal of the circuit part 2. FETQ5, Q6 and FETQ7, Q8 are provided to an output buffer gate 4 and the output signal of the circuit part 2 and that of the circuit part 1 are changed over to be outputted to the outside. By this method, without using an exclusive test terminal at the time of the testing of the sequence circuit, the sequence circuit part can be directly accessed from the outside.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to semiconductor integrated circuits, and particularly to RAM.

The present invention relates to an input/output buffer circuit for a semiconductor integrated circuit incorporating sequential circuits such as ROM and ALU.

[Conventional technology]

Conventionally, in the human output buffer of a semiconductor integrated circuit including this kind of sequential circuit, the output of the input buffer is connected to the sequential circuit section via the combinational circuit section, and the input of the output buffer is connected to the sequential circuit section as shown in FIG. Even the output of the sequential circuit section is generally connected to the output of the combinational circuit section via the combinational circuit section.

[Problem that the invention seeks to solve]

The conventional semiconductor integrated circuits mentioned above generally have a four-component structure in which a sequential circuit such as a RAM is surrounded by a combinational circuit, so it is often not possible to access the sequential circuit directly from the input/output terminal, and this building Semiconductor integrated circuits process signals from input/output terminals in combinational circuits other than RAM and write the results to RAM, or perform some processing on data read from RAM and output it from output terminals. Due to the complicated operation of RAM, it is extremely difficult to create a test pattern with a failure coverage rate equivalent to that of a normal memory chip.

In addition, by inserting a flip-flop between the input/output terminal of the semiconductor integrated circuit and the input/output terminal of the RAM, and adding a level signal to the clock signal of the flip-flop to treat the flip-flop 70 tube as a gate, it is possible to Even if it is possible to set up a one-to-one correspondence between the input/output terminals of the integrated circuit and the input/output terminals of the RAM, rigorous testing of RAM access time, etc. is impossible because it includes the delay time of flip-flops. There is a drawback that.

[Failure to solve the problem]

In a semiconductor integrated circuit including a sequential circuit and a combinational circuit, the present invention provides means for switching between an external input signal and an output signal of the combinational circuit and connecting the output signal to an input end of the sequential circuit, which is provided in an input cover sofa. It is characterized by having means provided in the buffer for switching between the output signal of the sequential circuit and the output signal of the combinational circuit section and outputting the same to the outside.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of a logic circuit showing an embodiment of the present invention.

In this embodiment, the logic circuit includes a sequential circuit section 2 and a combinational section 1.
It further comprises an input buffer gate 3 for transmitting an external signal applied from the input terminal a to the inside of the logic circuit, an output buffer gate 4 for taking out the output of the logic circuit to the outside, and an output terminal. The output of the input buffer gate 3 is connected to the input terminal g of the sequential circuit section 2 through a transfer gate composed of a P-channel field effect transfer and an N-channel field effect transfer, and is also connected to the input terminal C of the combinational circuit section 1. is also connected. Furthermore, the input terminal g of the sequential circuit section 2 is also connected to the output terminal d of the combinational circuit section 1 via a transfer gate configured with a P-channel field effect transfer and an N-channel field effect transfer. The input of the output buffer gate 4 is a P-channel field effect transistor Q.

The output end of the sequential circuit section 2 is connected to the output end of the sequential circuit section 2 via a transfer gate configured as an N-channel field-effect transfer transistor and a P-channel field-effect transistor Q? + An N-channel field effect transistor Q is connected to the output terminal f of the combinational circuit section 1 via a well-constructed transfer gate. Furthermore, the output end of the Jli sequence circuit 2 is also connected to the input terminal e of the combinational circuit section 1.

61i of the trench sequential circuit section and input/output buffer signals;
An input buffer gate 5 is connected to the selection signal input terminal i that controls the selection signal, and its output is sent via an inverter gate 6 to the transistors Q2. Q3+ Qa, Q,.

The output of the inverter gate 6 is connected to the gate electrode, and the output of the inverter gate 6 is connected to the transistor Q through the inverter gate 7.
Q4. Q,, is connected to the gate voltage hi of Q.

The operation of the logic circuit configured as described above is as follows.

First, input terminal i is at low level, that is, logic I! 1 of 121 circuits: The case of testing the simple circuit section will be described.

In this state, the output of inverter gate 6 is high level.
The output of inverter gate 7 is at low level. Therefore, the transfer gate made up of transistors Q, , Q is in a conductive state, and the transfer gate made up of transistors Q, , Q is in a cut off state, so that the signal applied to input terminal a is transmitted to input buffer gate 3 and transistor Q,
, Q are applied to the input terminal g of the sequential circuit section through different transfer gates. Also, transistor Q5. Q
, the transfer gate consisting of the transistors Q, , Q, is in the conductive state, and the transfer gate consisting of the transistors Q, , Q, is in the cut-off state, so the output end of the sequential circuit section is connected to the transistor Q.
, ,Q, and the output terminal can already be observed through the transfer gate and the output buffer gate 4. In other words, in this state, it is possible to directly access the sequential circuit section from the input terminal a and the output terminal.

Next, a case will be described in which the input terminal i is at a high level, that is, the logic circuit is in normal operation.

In this state, the output of the inverter gate 6 is at a low level, and the output i1t of the inverter gate 7 is at a high level.

Therefore, the transfer gate made up of transistors Q, , Q is in a cutoff state, and the transfer gate made up of transistors Q, , Q is in a conductive state.

Therefore, the signal applied to input terminal a is
0 input terminal C, and the signal of the output d of the ancestral matching circuit section 1 is applied to the input terminal g of the sequential circuit section 1 via a transfer gate consisting of transistors Q, .

Also, the transfer gates made up of transistors Q, ,Q are in a cut-off state, and the transfer gates made up of transistors Q, ,Q are in a conductive state.The output end of the sequential circuit section 2 is connected to the input end of the combinational circuit section, The output terminal f of the combinational circuit section 1 is connected to the input of the output buffer gate 4 via a transfer gate made up of transistors Q, , Q. Therefore, in this state, the output terminal d of the combinational circuit section 1 is directly connected to the input terminal g of the sequential circuit section 2, and the output terminal f of the combinational circuit section 1 and the input of the output buffer are directly connected. It has the same function as a circuit.

〔Effect of the invention〕

As explained in detail above, according to the present invention, by simply adding four transistor elements to each of the input buffer circuit and the output buffer circuit, there is no need to use a dedicated test terminal when testing sequential circuits, etc. Since the sequential circuit section can be directly accessed and a logic circuit that does not affect the operation of the logic circuit during normal operation can be easily constructed, the time and cost involved in creating test patterns can be significantly reduced. This has the effect of simplifying circuit design since it does not require a dedicated input terminal for sentences.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention, and FIG. 2 is a configuration diagram of a conventional logic circuit. 1... Combinational circuit section, 2... Sequential circuit section, 3.5... Input buffer gate, 4.
...output buffer gate, 6,7...inverter gate, a...output terminal of logic circuit,
b... Input terminal of logic circuit, c, e...
・Input terminal of combinational circuit section, d, f...
・Output end of combinational circuit section, g... Sequential circuit section input end, h... Sequential circuit section output end, Q, ,
Q,, Q,, Q,...P channel field effect transistor, Qt p Q4 +Q6. Q...
...N-channel field effect transistor, i...
...Selection signal input terminal. Agent Patent Attorney Uchihara Oto Figure 1

Claims (1)

[Claims] In a semiconductor integrated circuit including a sequential circuit section and a combinational circuit section, means provided in an input buffer for switching between an external input signal and an output signal of the combinational circuit section and connecting it to an input terminal of the sequential circuit section; A semiconductor integrated circuit, comprising means for switching between an output signal of the sequential circuit section and an output signal of the combinational circuit section and outputting the signal to the outside.