JPS62109341A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62109341A JPS62109341A JP24918385A JP24918385A JPS62109341A JP S62109341 A JPS62109341 A JP S62109341A JP 24918385 A JP24918385 A JP 24918385A JP 24918385 A JP24918385 A JP 24918385A JP S62109341 A JPS62109341 A JP S62109341A
- Authority
- JP
- Japan
- Prior art keywords
- film
- aluminum
- insulating film
- semiconductor device
- aluminum alloy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置の製造方法に係り、特に大規模
集積回路(以下、LSIという)における電極、配線膜
の形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming electrodes and wiring films in a large-scale integrated circuit (hereinafter referred to as LSI).
半導体集積回路(IC)においては、LSI。 In semiconductor integrated circuits (IC), LSI.
VLSIと高度に集積化されるに伴い、比例縮少則に従
って微細化されている。コンタクトホールの径はこの比
例縮少則に従って微細化されているが、層間絶縁膜は薄
くなっていない。このために、コンタクトホールのマス
ペクト比は太き(なる方向にある。そのため、これまで
一般的に用いられてきたスパッタリング法に工す半導体
基板上の絶縁層表面にそのコンタクトホールを介してア
ルミニウム合金膜を電極または配線膜として形成すると
、このアルミニウム合金膜31は、第2図に示す:うに
、半導体基板としてのシリコン基板1上に形成された層
間絶縁膜2のコンタクトホール部21でオーバーハング
状態となり、コンタクト側壁のカバレッジが悪(なる。As it becomes more highly integrated with VLSI, it is being miniaturized according to the law of proportional reduction. Although the diameter of the contact hole has been reduced in accordance with this proportional reduction law, the interlayer insulating film has not become thinner. For this reason, the contact hole has a large aspect ratio (in the direction of becoming larger).Therefore, the contact hole is used to form an aluminum alloy on the surface of the insulating layer on the semiconductor substrate using the sputtering method that has been commonly used. When the film is formed as an electrode or a wiring film, this aluminum alloy film 31 is in an overhang state at the contact hole portion 21 of the interlayer insulating film 2 formed on the silicon substrate 1 as a semiconductor substrate, as shown in FIG. This results in poor contact sidewall coverage.
このように、従来の半導体装置の製造方法では、アルミ
ニウム合金膜を形成する場合層間絶縁膜表面のコンタク
ト側壁でのアルミニウム合金膜のカバレッジが悪いため
、断線音引き起こす等の問題点があった。As described above, in the conventional method for manufacturing a semiconductor device, when an aluminum alloy film is formed, coverage of the aluminum alloy film on the contact sidewall on the surface of the interlayer insulating film is poor, resulting in problems such as disconnection noise.
この発明は上記のような問題点全解消するためになされ
たもので、電極、配線膜を形成するに際し絶縁膜表面の
コンタクト等段差部でのカバレツジの良いアルミニウム
合金膜などのアルミニウム導電膜を形成することにより
、断線に対する信頼性を同上させた半導体装置の製造方
法を提供することにある。This invention was made to solve all of the above-mentioned problems, and when forming electrodes and wiring films, it is possible to form an aluminum conductive film such as an aluminum alloy film that has good coverage at stepped parts such as contacts on the surface of the insulating film. By doing so, it is an object of the present invention to provide a method for manufacturing a semiconductor device that has improved reliability against disconnection.
この発明に係る半導体装置の製造方法は、半導体基板上
の絶縁膜表面にそのコンタクトホールを介して電極、配
線膜全形成する工程において、前記絶縁膜の表面に液体
状のアルミニウム化合物またはアルミニウムを含む溶液
を塗布してアルミニウム導電膜を形成することを特徴と
するものである。In the method for manufacturing a semiconductor device according to the present invention, in the step of completely forming an electrode and a wiring film on the surface of an insulating film on a semiconductor substrate via the contact hole, a liquid aluminum compound or aluminum is included on the surface of the insulating film. This method is characterized by forming an aluminum conductive film by applying a solution.
この発明においては、アルミニウム導電膜は塗布法にて
形成することにより、コンタクト等段差部でのカバレン
ジが良好な膜が得られる。In this invention, by forming the aluminum conductive film by a coating method, a film with good coverage at stepped portions such as contacts can be obtained.
以下、この発明の実施例を図について説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第1図はこの発明による半導体装置の製造方法の一実施
例上水す工程断面図である。この実施例において第2図
に示した従来のものと異なる点は、シリコン基板1上に
形成されたコンタクトホール21?有する層間絶縁膜2
の表面に電極、配線膜を形成するに際し、前記層間絶縁
膜20表面に液体状のアルミニウム化合物またはアルミ
ニウムを含む溶液を塗布した後、熱処理等の後処理を行
なってアルミニウム合金膜3を形成したものである。FIG. 1 is a cross-sectional view of the pouring process in an embodiment of the method for manufacturing a semiconductor device according to the present invention. This embodiment differs from the conventional one shown in FIG. 2 in that it has a contact hole 21 formed on the silicon substrate 1. interlayer insulating film 2 having
When forming electrodes and wiring films on the surface of the interlayer insulating film 20, a liquid aluminum compound or a solution containing aluminum is applied to the surface of the interlayer insulating film 20, and then post-treatment such as heat treatment is performed to form an aluminum alloy film 3. It is.
この場合、液体状のアルミニウム化合物またはアルミニ
ウムを含む溶液を構成する物質として水素。In this case, hydrogen is used as the substance constituting the liquid aluminum compound or solution containing aluminum.
炭素、酸素のいずれか1つが含有しである。Contains either carbon or oxygen.
このように、アルミニウム合金膜3全塗布法にて形成す
ることにより、このアルミニウム合金膜3は、従来のよ
うに層間絶縁膜2表面のコンタクトホール部でオーバー
ハングもなく、第1図に示す如くコンタクト等段差部で
のカバレッジが良好なものが得られる。In this way, by forming the aluminum alloy film 3 by the entire coating method, the aluminum alloy film 3 has no overhang at the contact hole portion on the surface of the interlayer insulating film 2, as shown in FIG. Good coverage at stepped portions such as contacts can be obtained.
なお、上記実施例では電極、配線膜としてアルミニウム
合金膜を用いた場合について述べたが、アルミニウム膜
を用いてもよい。In addition, although the above-mentioned example described the case where an aluminum alloy film was used as an electrode and a wiring film, an aluminum film may be used.
また、上記実施例では*1層目のアルミニウム合金膜に
適用した場合を述べたが、第2層目以後罠適用すること
もできる。Further, in the above embodiment, the case was described in which the method was applied to the first layer of the aluminum alloy film, but it can also be applied to the second and subsequent layers.
以上のようにこの発明によれば、アルミニウム合金膜ま
たはアルミニウム膜などのアルミニウム導電膜全塗布法
にて形成することにより、コンタクト等段差部でのカバ
レンジが良好な膜が得られ、これによって、断線等に対
する半導体装置の信頼性全回上させることができる効果
がある。As described above, according to the present invention, by forming an aluminum conductive film such as an aluminum alloy film or an aluminum film by a full coating method, a film with good coverage at stepped portions such as contacts can be obtained. There is an effect that the reliability of the semiconductor device can be improved in all respects.
第1図はこの発明による半導体装置の製造方法の一実施
例を示す工程断面図、第2図は従来方法の一例上水す工
程断面図である。
1・・・・ンリコン基板、2・・・・層間絶縁膜、21
・・・・コンタクトホール、3・・・・アルミニウム合
金膜。
代 埋 人 大 岩 増 雑纂1図
第2図
手続補正書(自発)
鉦 :、 乙
昭和 年 月 日FIG. 1 is a process sectional view showing an embodiment of a method for manufacturing a semiconductor device according to the present invention, and FIG. 2 is a process sectional view showing an example of a conventional method. 1...Nilicon substrate, 2...Interlayer insulating film, 21
...Contact hole, 3...Aluminum alloy film. Miscellaneous Figure 1 Figure 2 Procedural amendment (voluntary) Gong: Otsu Showa year, month, day
Claims (1)
して電極、配線膜を形成する工程において、前記絶縁膜
の表面に液体状のアルミニウム化合物またはアルミニウ
ムを含む溶液を塗布してアルミニウム導電膜を形成する
ことを特徴とする半導体装置の製造方法。In the process of forming electrodes and wiring films on the surface of an insulating film on a semiconductor substrate through the contact holes, a liquid aluminum compound or a solution containing aluminum is applied to the surface of the insulating film to form an aluminum conductive film. A method for manufacturing a semiconductor device, characterized in that:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24918385A JPS62109341A (en) | 1985-11-07 | 1985-11-07 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24918385A JPS62109341A (en) | 1985-11-07 | 1985-11-07 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62109341A true JPS62109341A (en) | 1987-05-20 |
Family
ID=17189133
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24918385A Pending JPS62109341A (en) | 1985-11-07 | 1985-11-07 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62109341A (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02288369A (en) * | 1989-04-28 | 1990-11-28 | Matsushita Electric Ind Co Ltd | Solar cell |
GB2253939A (en) * | 1991-03-20 | 1992-09-23 | Samsung Electronics Co Ltd | Forming a metal layer on a semiconductor device |
US5534463A (en) * | 1992-01-23 | 1996-07-09 | Samsung Electronics Co., Ltd. | Method for forming a wiring layer |
US5569961A (en) * | 1992-12-30 | 1996-10-29 | Samsung Electronics Co., Ltd. | Semiconductor device having a multi-layer metallization structure |
US5814556A (en) * | 1995-08-18 | 1998-09-29 | Samsung Electronics Co., Ltd. | Method of filling a contact hole in a semiconductor substrate with a metal |
DE4342047B4 (en) * | 1992-12-10 | 2004-12-09 | Samsung Electronics Co., Ltd., Suwon | Semiconductor component with a diffusion barrier layer arrangement and method for its production |
DE4329260B4 (en) * | 1992-10-05 | 2007-01-25 | Samsung Electronics Co., Ltd., Suwon | Method for producing a wiring in a semiconductor device |
-
1985
- 1985-11-07 JP JP24918385A patent/JPS62109341A/en active Pending
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02288369A (en) * | 1989-04-28 | 1990-11-28 | Matsushita Electric Ind Co Ltd | Solar cell |
US5869902A (en) * | 1990-09-19 | 1999-02-09 | Samsung Electronics Co., Ltd. | Semiconductor device and manufacturing method thereof |
GB2253939A (en) * | 1991-03-20 | 1992-09-23 | Samsung Electronics Co Ltd | Forming a metal layer on a semiconductor device |
DE4200809A1 (en) * | 1991-03-20 | 1992-09-24 | Samsung Electronics Co Ltd | METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT |
GB2253939B (en) * | 1991-03-20 | 1995-04-12 | Samsung Electronics Co Ltd | Method for manufacturing a semiconductor device |
US5534463A (en) * | 1992-01-23 | 1996-07-09 | Samsung Electronics Co., Ltd. | Method for forming a wiring layer |
US5589713A (en) * | 1992-01-23 | 1996-12-31 | Samsung Electronics Co., Ltd. | Semiconductor device having an improved wiring layer |
DE4329260B9 (en) * | 1992-10-05 | 2007-05-24 | Samsung Electronics Co., Ltd., Suwon | Method for producing a wiring in a semiconductor device |
DE4329260B4 (en) * | 1992-10-05 | 2007-01-25 | Samsung Electronics Co., Ltd., Suwon | Method for producing a wiring in a semiconductor device |
DE4342047B4 (en) * | 1992-12-10 | 2004-12-09 | Samsung Electronics Co., Ltd., Suwon | Semiconductor component with a diffusion barrier layer arrangement and method for its production |
US5572071A (en) * | 1992-12-30 | 1996-11-05 | Samsung Electronics Co., Ltd. | Semiconductor device having a multi-layer metallization structure |
US5851917A (en) * | 1992-12-30 | 1998-12-22 | Samsung Electronics Co., Ltd. | Method for manufacturing a multi-layer wiring structure of a semiconductor device |
US5569961A (en) * | 1992-12-30 | 1996-10-29 | Samsung Electronics Co., Ltd. | Semiconductor device having a multi-layer metallization structure |
US5814556A (en) * | 1995-08-18 | 1998-09-29 | Samsung Electronics Co., Ltd. | Method of filling a contact hole in a semiconductor substrate with a metal |
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