JPS62107516A - Signal switching circuit - Google Patents

Abstract

PURPOSE:To switch a signal with a large amplitude at a low voltage by extracting an output signal alternatively from any one of the 1st, 2nd and 3rd differential amplifiers in response to the level of a switching voltage so as to simplify the circuit constitution. CONSTITUTION:The circuit operation is switched in response to a change in a switching voltage given to a transistor (TR) Q11, and when the switching voltage is lower than a voltage VL, Trs Q15, Q17 are turned on and TRd Q14, Q16 are turned off. Thus, the voltage across a resistor R13 is higher than that of a resistor R12 and a voltage across a resistor R11 is the smallest of the voltages across the resistors R12 and R13. The Q31-Q33 receiving the voltages boost them higher by each base-emitter voltage and the result is impressed to TRs Q34-Q36, then a signal S11 gives the highest level Ah, a signal S12 shows the intermediate level AM and a signal S13 offers the smallest level AL respectively. A TR among the TRs Q34-Q36 receiving the level AH only is turned on with priority.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention provides a differential amplifier circuit with a signal switching circuit (, -), a small number of components of the differential amplifier circuit, and a dynamic range. Concerning a wide range of signal switching circuits.

"Technical tax of the invention" As a circuit for switching and selecting one of a plurality of different types of signals, there is a circuit using a differential amplifier as shown in FIG. The configuration of M1 is shown in the cylinder.

In FIG. 3, Pl is a terminal to which a switching voltage for switching is supplied, and Vl, V2, V3i are signal sources for switching selection signals. The switching voltage supplied to the terminal P1 is selected from any one of the signal sources V1, V2, and V3.
In this specification, the boundary levels of this signal switching are referred to as VL and vH.

The transistors Ql, Q2, Q3 to which the signals from the bind-off sources V1 to V3 are applied to their bases are transistors Q4, Q5, respectively.

A differential amplifier is configured between Q6 and JL, and A of this differential amplifier is
By the ON/A-OFF operation, one of the signals is selectively output from the collectors of the transistors Q4 to Q6. Further, the differential amplification transistors 01 to 06 have differential amplification transistors Q7, Q8, Q9 .
Controlled by QIO. The bases of these differential amplification transistors Q7 to Q10 are connected to the switching voltage from the terminal P1 with signals λ (thus forming signals @81.82.83, S
4 is applied.

The circuit consisting of transistors Q11 to Q23 is
It constitutes a circuit that forms the above-mentioned signals S1 to S4 from the switching voltage, and the switching voltage is applied to the base of a transistor Q11 whose collector is connected to the reference voltage line ]-0. On the other hand, a series circuit consisting of a resistor R1°R2, r<3 interposed between the voltage source line L1 and the reference voltage line 1-0 is connected to the switching level V11. A dividing resistor for setting Vl, which generates a voltage corresponding to Vl at the intersection P of resistors R2 and R3, and generates a voltage corresponding to Vl+ at the intersection P of resistors R1 and R2.
occurs at the intersection pH. The intersection point PL is connected to the base of a transistor Q12 whose transmitter is connected to the voltage source line 1-1 via the current source 11, and the voltage generated at the transmitter of this transistor Q12 is the voltage generated at the transmitter of the transistor Q14. Q15. It is applied to the base of transistor Q14 of a circuit block consisting of resistors R4, R5 and current source I2. Transistor Q14 of this block.
Q15 constitutes a differential amplifier, and transistor Q
The emitter of the transistor Q11 is connected to the base of the transistor Q15, and a voltage proportional to the switching voltage is applied thereto. Furthermore, ]・Langister Q14. The collector of Q15 is connected to the reference voltage line LO via the resistors R4 and R5, and the current source 13.
Transistor Q18 to the right of 14. The signals 34 and S3 are connected to the base of transistor Q19, and the signals 34 and S3 are outputted from the emitter J of these transistors 018 and Q19.

Also, the intersection pl+ is connected to the base of a transistor Q13 whose emitter side is connected to a current source I5, and the emitter of this transistor Q13 is connected to the transistor Q1G,
Q17. Connected to the base of transistor Q1B of a circuit block consisting of resistors R6, R7 and current source I6. Transistor Q16. Q17 constitutes a differential amplifier, and the transistor Q1 is connected to the base of the transistor Q17.
1 are applied to the emitters of transistors Q16.1, respectively. The collector of Q17 is connected to the reference voltage line 1.0 via resistors R6 and R7, and to the bases of the next stage transistors Q21 and Q23. Transistor Q21. Q23 is collector・■
The transmitter-X transmitter path of the -F stage transistors Q20 and Q22 is connected in series, and the voltage source side of this series connection is connected to a current source 17. R8 is connected. Upper stage transistor Q22. Q20 is connected between the base and collector, and receives the signal 81°S2 from the collector.
is outputting.

Note that the transistor Qll has a current source I9,
Transistors Q24 to Q26 are current mirror type current sources, and transistor Q27 is an output transistor whose load is current source 110. Furthermore, differential amplification transistor 09. (The mitters 510 are each connected to the base voltage line LO via a current source 111.

The operation of the conventional signal switching circuit configured as described above can be performed from time chart 1 shown in FIG.

That is, in FIG. 4, the vertical axis shows the voltages of the signals 81 to S4, and the horizontal axis shows the voltage of the switching voltage. Transistor Q1
1 is always on due to the application of the switching type I[], and a voltage proportional to the level of the switching voltage appears at the ]-mitter.

First, in the section E1 where the level of the switching voltage is lower than Vl, the differential amplification transistors Q14. R15 OJ:biR1
6, R17, R14 is A, R15 is on,
Since R16 is off and R17 is on, signals 81 to S4
As shown in Figure 4, these are high level (hereinafter referred to as “
II” level), low level (hereinafter referred to as II L
The I+ level, 16), the "1-1" level, and the "L" level. This turns on transistor Q7, turns off i-transistor Q8, turns on transistor Q9, and turns off transistor Q10.

Therefore, if the switching voltage is lower than the voltage 1"j-V l
In the interval E1 of ~V[, the differential amplification transistor Q1,
When R4 operates 1y, the signal v1 input to this amplifier
is selected and output.

Next, the section F2 in which the switching voltage is from the v rubel to the VH level
When it changes to , transistor Q14 turns on, R15 turns off, and R16 and R17 are the same as in section F1.

Therefore, the signals 81 to S4 are at the '11' level, the 111 I+ level, the II l-TI level, and the '' level, respectively.
I+” level, and transistor Q10 replaces Q9.
turns on. At this time, since the transistors Q7 and R8 are turned on and off, respectively, the differential amplification transistors Q2 and R5 are activated, and the signal v2 is selectively output.

In addition, in the section F3 where the switching voltage is higher than l, the differential amplification transistor Q14. While R15 remains in the same state, transistors Q16. The state of R17 is the same as that of transistor Q1.
6 is turned on, R17 is turned off, and the levels of signals S1 and S2 are inverted. This causes transistor Q7. Q
8 is inverted and the signal Q y 39 is selectively output.

Note that in the above circuit, the boundary values Vl and V11 are each expressed by the following equations.

V L-1, □R"------X V・・・・・・(
1) R14R2-I R3 I-1'-2-', R-J-xv... (2) R
1+R2-N13 However, ■ is the electric current J'i=supply voltage value of the source [Problem 1 in the background technology The conventional circuit consists of transistors Q1 to Q6 in the configuration of a switching stage controlled by signals 81 to 84. Transistors Q7 to Q10 act as current sources for the differential amplifier
The circuit consists of a two-stage differential amplifier, so when trying to switch and control a large-amplitude signal f), the supply voltage of the voltage source must be set to a correspondingly large value, which reduces power consumption. There was a problem that it was not suitable for installation 1.

Further, since the differential amplifying transistors Q7 to QIO are configured in two stages, transistors Q20 and R22 are also required to correspond to this configuration, which has the disadvantage of complicating the circuit.

[Object of the Invention] The present invention has been made in view of the above-mentioned points, and it is possible to switch and select a signal with a large amplitude that matches the low power supply voltage.
It is an object of the present invention to provide a signal switching circuit that can be used to switch signals and whose configuration can be simplified.

[Summary of the Invention] In order to achieve the above object, the present invention provides the following features. The first . a signal switching circuit that selectively amplifies and outputs either one of the second and third signals; Second. a third transistor;
a level setting means for producing a first level and a second level higher than this level, an area lower than the first level, an intermediate area between the first level and the second level, and a level higher than the second level; means for generating a switching voltage having a level change in the region; and a fourth . Fifth and sixth. The seventh transistor is configured with C, the bases of the fourth and sixth transistors have the switching type f[, and the bases of the fifth and seventh transistors have voltages at the first and second levels, respectively. first and second voltage comparison means supplied with voltage; and fourth. 7th
The first . a second resistor; and a fifth resistor. the first . and a third resistor smaller than the second resistor. Second. Third
Using the voltage I'T drop of the resistor of the first. 2nd, 3rd
By selectively activating any one of the transistors of the first, second, and so on. In this circuit, any one of the third signals is selected through each of the 11 differential amplifiers.

[Embodiment 1 of the invention The present invention will be described below with reference to the illustrated embodiments.

FIG. 1 is a circuit diagram showing an embodiment of the signal switching circuit according to the present invention, and FIG. 2 is an explanatory diagram showing the operation of the circuit of FIG. 1.

In FIG. 1, circuit parts having the same functions as those in FIG. At the point, the boundary voltage of the switching voltage from terminal P1) 1: V 1. ,
A voltage directed toward λ1 is set to V I+. Q12, (
:)1];1, electric 1F from intersection PI-, PH respectively
, differential amplification 1 helang transistor Q14. Q15 OJ: BiQ
16. Buffer applied to the base of Q17! ~ transistor, 11°15 is transistor Q12. The current source of Q13, 12°■6 is the differential amplification i-transistor Q14. Q15
(13 and Q?6.Q10 current source, I9 is the trough 29f90 current source.

Differential amplification transistors Q16 and Q15 are connected to the reference voltage line 10 through resistors 11 and R13, respectively, and transistors Q14 and Q17 are connected to the reference voltage line 10 through resistors R12, respectively. 10. The voltages applied to each of these resistors R11 to R3 are transmitted through transistors Q33. Q32゜ is applied to the base of Q31, and the emitters of these transistors Q31 to Q33 are connected to the voltage source line 1-1 via current sources 121- and 123, respectively, and the transistor Q
34 to Q36 and l transistors Q1 to Q6, Q
24 and Q27 output signals for actual switching control to the switching stages already configured = is11.812.813. Note that the resistance values of the resistors R11 to R13 are set in a predetermined relationship as described later.

The transistor Q34. Q35. Q36 receives signals S11 and S12.813 at its base, each emitter is connected to the reference voltage line l-0 via a resistor R14, and each collector is connected to -F stage differential amplification transistors Q1, Q4, Q2, Connected to the 1-mitter of Q5, Q3, and Q6. Then, with the signals from the collectors of these transistors Q11 to Q13, the signals V1 and V3 applied to the bases of predetermined 1H transistors of each upper stage differential amplifier are selectively switched to $l via the output transistor Q27. ! It is designed to be selectively output.

Although not explained in FIG. 3, the circuits constituting the current mirror circuit are the transistors Q24 and Q25.
The transmitter is connected to the voltage source line 11, and the transistor Q
The base and collector of the transistor Q25 are short-circuited, and the collector of the transistor Q24 (and the base of the transistor Q26 are connected).Then, the differential amplification transistor Q1
~Q3='Rector is Karen]-mirror transistor Q
24], and the differential amplification transistor Q4
~Q6]rector is current mirror transistor 026
], and its base is connected to the emitter of output transistor Q27.

The present invention is constructed as described above, and its operation will be explained with reference to FIG. 2. Note that the vertical axis in FIG. 2 represents signals 811 to 811.
The voltage axis shows the level of 813, and the horizontal axis is the voltage axis showing the level of the switching voltage. Further, the solid line shows the timing of the level change of the signal 811, the dashed line shows the timing of the signal 812, and the dotted line shows the timing of the signal S13.

Now, when a switching voltage of a predetermined value is supplied to the terminal P1, the transistor Q11 is turned on. This transistor Q1
1 introduces a voltage proportional to the switching weight to the mitter, so that the operation of the circuit is switched in accordance with the change in the switching voltage. Hereinafter, the details of the present embodiment will be explained separately depending on the level section of the switching voltage.

1) If the level of the switching voltage is lower than the threshold voltage V [smaller range]
1, the switching voltage is lower than VIJ: each differential amplifier transistor Q15. Differential amplification with respect to the electric current F1 appearing at the base of Q17] ~ transistor Q14. The voltage set to Q16 is the differential amplification 1 helang transistor Q14゜Q1.
51, one Q14 base electric is better than Ql! greater than the base voltage of i, differential amplification transistor Q16゜Q1
7, the base voltage of Q16 is larger than the base voltage of 017 by b. For this reason,]・Langister Q15°Q17
turns on and Q14. Q16 is Al.

Here, the load resistance of differential amplification transistors Q14 to Q17 is 1<11, and the resistance ratio of R13 is as follows: R11=R13=2xR12... (3)
is set to .

Therefore, to the above differential amplification transistor Q14, Q
17, the voltage across the resistor R13 is equal to the voltage across the resistor R13.
When the transistor Q16 is turned off, the voltage across the resistor R11 is higher than the voltage across the resistor R12.
12, the value that is smallest than the voltage across R13 is set first. i~ which receives the voltage of each of these resistors R11 to R13 at its base
Transistors Q31-Q33 apply the voltage applied to their bases to the base-to-Jmitter voltage (J is applied as a higher voltage to the bases of the next stage transistors Q34-036, so the signal 811 advances the highest level All, then the signal S12 advances the intermediate level AH, and the signal S13 advances the smallest level A+.

Now, each of the transistors Q34 to Q36 has a differential configuration in which the mitter is connected to the passthrough, and the level Δ11. Δ) Among I and AI, only those to which a signal of level All is supplied to the base are turned on preferentially. Therefore, except for transistor Q34, other transistors Q
35. Q36 is turned off. Transistor Q34 is A
1, the differential amplification transistor 16 = star Ql, Q4 becomes active, so that the voltage No. 18 V1 applied to the base of one of the transistors 01 is transferred from the output transistor Q of the transistor Q4 to the output transistor Q.
27 and output from its -[mitter.

2) Operation in the range F2 when the switching voltage level is -1 to -Vl+, when the switching voltage exceeds Vl-, the switching voltage level is
14. Q15t, the base voltage of transistor 015 is made higher. However, differential amplification L and transistor Q
16.017 changes /i. That is, differential amplification transistor Q14. The state of only Q15 is reversed, and the transistor Q14 is turned on and the transistor Q15 is turned off. When the transistor Q14 turns on, the current flows through the resistor R12 twice as much as in the above operation because it overlaps with the current from the transistor Q17. In this way, twice the current flowing through the resistor R12 means that it is approximately equal to the electric current applied to the resistor R13 by the current of the transistor Q15 in operation (1) described above. When the voltage is applied, the transistor Q32 is turned off and outputs a high level signal to the second transmitter. Therefore, signal 812 to transistor Q35 is at level All
of? do.

-10,000, transistor Q15. Since Q16 is off,
Transistor Q31. Q33 turns on and the signal S11
Both OJ and 813 are at the AI level. Therefore, in the interval E2 where the switching voltage is V1 to Vl+, the transistor Q35 is switched to Al, and the other transistor Q
34. Q36 is turned off. Thus, transistor Q
The differential amplifying transistors Q2 and Q5, which are activated by turning on the signal V2, can selectively switch the signal V2.

3) Operation when the switching voltage is higher than Vl+; in this case, the operating states of the differential amplifying transistors Q14°Q15 do not change, and the operating states of the differential amplifying transistors Q16 . Q1
7 is reversed. (016 on, Q17 off) Therefore, a voltage that turns off the transistor Q33 appears in the resistor R11, and the signal 813 shifts to the All level. Note that the voltage across the resistor R12 is smaller than the voltage across the resistor R11, and as the transistor Q32 operates in the saturation region, the level of (, 4, qH812)
i A H. Further, transistor Q31 remains on, and the level of signal 811 is A1. Therefore, only the 1-transistor resistor 036 is turned on and the signal 3 can be selected.

Note that each operating current when each of the transistors Q34 to Q36 is turned on is typically expressed as I6×−R−11− (4) 1×14.

Here, if the ratio of resistor R11 etc. is made small, the base bias of each transistor Q34 to Q36 is
Since it can be made sufficiently low, the die diameter range can be widened.

It should be noted that the present invention is not limited to the configuration shown in FIG. 1, but can be modified in various ways without departing from the scope of the claims, such as changing the pole M of the transistor.

[Effect of the invention] If the above-described J, sea urchin according to the present invention is applied, the credit ¥1 switching 1
The structure of the circuit that controls the first stage of 9 is simplified, and the structure of the other circuit parts can also be simplified accordingly. Furthermore, since the present invention can widen the die-nomic range by -4, it is possible to switch large amplitude signals with a low voltage.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of a signal switching circuit according to the present invention, FIG. 2 is an explanatory diagram showing the operation of the present invention, and FIG. 3 is a circuit diagram showing an example of a conventional signal switching circuit. 4 are explanatory diagrams showing the operation of FIG. 3. Q1 to Q6...Differential amplification transistors.

Claims (1)

[Claims] First, second, and third signals are inputted to the first, second, and third signals.
a first, second and third transistor forming a current source for each of these differential amplifiers and connected in a differential configuration, a first level and a second level higher than this level; level setting means for generating a voltage; and switching for changing the level to a region lower than the first level, an intermediate region between the first level and a second level, and a region higher than the second level. means for generating a voltage; and fourth and fifth transistors, the switching voltage being supplied to the base of the fourth transistor, and the voltage at the first level being supplied to the base of the fifth transistor; It has a first voltage comparison means whose emitters are commonly connected to a first potential point via a current source, and sixth and seventh transistors, and the switching voltage is supplied to the base of the sixth transistor. a second voltage comparing means, wherein the voltage at the second level is supplied to the base of the seventh transistor, and each emitter is commonly connected to the first potential point via a current source; , first and second resistors respectively connected between the collector of the seventh transistor and the second potential point and exhibiting substantially equal values to each other; and a common collector of the fifth and sixth transistors and the second resistor. A third resistor is connected between the potential points of the resistor and exhibits a smaller value than the first and second resistors, and a voltage drop caused by the first, second, and third resistors is used to reduce the voltage. selectively controlling any one of the transistors by supplying first, second, and third control signals that vary in proportion to the drop to the bases of the first, second, and third transistors, respectively; control means for operating the first, second and third switching voltages in response to the level of the switching voltage;
A signal switching circuit that selectively extracts an output signal from one of the differential amplifiers.