JPS59129992A - Sampling hold circuit - Google Patents

Abstract

PURPOSE:To attain stable sample holding by utilizing the operation of a differential amplifier circuit so as to balance the voltage of a holding capacitor with an analog input voltage. CONSTITUTION:When the analog input voltage from an analog input signal source 27 is changed, the current of a transistor (TR) 21 forming the differential amplifier circuit 23 together with a TR22 is changed and the current of a TR36 of a current mirror circuit 25 is changed also. Further, a charge or a discharge current flows to the holding capacitor 31 via a line 30 connecting the collector and base of the TR22 until the analog input voltage is made coincident with the holding voltage and the circuit 23 is made stable. Thus, stable sample hold is attained.

Description

[Detailed Description of the Invention] [Industrial Application Field] Regarding the Akira Honse &
It is suitable for application to.

[Background technology and its problems]

Sampling and holding circuits that can be configured on an IC are used in various electronic devices to sample and hold input analog signals.
There is a circuit in which a current-driven sampling transistor 3 is connected in series with a hold capacitor 2 which is placed outside the CI, thereby optically multiplexing the input analog voltage.

This sampling and holding circuit has an input transistor 4 connected as an emitter follower, the collector of which is connected to a constant voltage source V. 0 and the emitter is connected to a sufficiently large load resistance 5
is grounded through. An analog input signal source 7 connected top to column to a current bias voltage source 6 is connected to the base of the input transistor 4 through a resistor 8, so that the analog input signal source 7 corresponds to the analog human power voltage ein of the analog input voltage source 7. Current source ■. 0 to the load resistor 5 through the collector emitter of the transistor 4, and the voltage drop generated at the non-grounded connection point Pl of the load resistor 5 is obtained as the analog input voltage Vi.

This connection point P1 is connected to the hold capacitor 2 through the collector emitter of the sampling transistor 3. The base of the sampling transistor 3 is connected to a constant voltage source V through a resistor 9. 0 and is connected to K so that it can be grounded through the switching transistor 10. Normally, the switching transistor 0 is on, and by grounding the base of the sampling transistor 3, it is turned off, and from this state, the switching transistor 3 is turned off.

By applying a sampling pulse signal SP to the base of the sampling transistor 30 to turn it off, a constant voltage source V is applied to the base of the sampling transistor 30. Apply a voltage of 0 to turn it on. When the sampling transistor 3 turns on, the analog input voltage V at the connection point P1 is sampled to the hold capacitor 2, and when the sampling transistor 3 turns off, the sampled voltage v8 is held.

The non-grounded connection point P2 of the hold capacitor 2 is output to the output terminal 13 through the output transistors 1 and 12 connected in a Darlington-connected emitter-follower connection.

The configuration shown in FIG. 1 can be said to be suitable for forming on an IC, but when the sampling transistor 3 is turned on and the analog input voltage Vi is sampled to the capacitor 2, the base current of the transistor 3 during the on operation is The problem is that the current flows through the emitter and flows into the capacitor 2, causing a deviation (offset) in the sampling voltage vs of the capacitor 2. Furthermore, the configuration shown in FIG. 1 has a problem in that it exhibits asymmetric impedance characteristics when charging and discharging the capacitor 2 through the sampling transistor 3. These problems
To solve this problem, conventionally, as shown in FIG. 2, in place of the sampling transistor 3, a pair of sampling transistors 15 and 16 whose collector emitters are connected in antiparallel to each other has been used.

However, even if this method is used, the following problems still occur, and it is still insufficient since the analog input voltage is sampled at a high iM[. First, a current-driven sampling transistor 15 is connected in series with the hold capacitor 2,
Since the transistors 15 and 16 are inserted, there is a drawback that the offset of the sampling voltage Vs based on the base current during on operation cannot be completely eliminated.
There is a drawback that the response of the sampling voltage vs to changes in the analog input voltage V□ is delayed due to the impedance of the collector emitter when the 16 is turned on.
Furthermore, since the impedance seen from the capacitor 2 side cannot be made close to infinite when the transistors 15 and 16 are turned off, there is a drawback that the charging load of the capacitor 2 is reduced and the sampling voltage v3 decreases. When the transistors 5 and 16 are turned on, the resistance change characteristics with respect to changes in the analog input voltage Vx are non-distortionate, so that there is a drawback that distortion occurs in the sampling voltage V of the capacitor 2.

Second, the analog input voltage ein of the analog input signal source 7 is the sampling voltage Vs of the capacitor 2 and the sampling output voltage V of the output terminal 13.

Looking at the signal level of input transistor 4, the base of input transistor 4 -
Emitter voltage V and output run sister 1 and H 12 output emitter voltage. A voltage shift occurs and therefore the analog input voltage ei of the analog input signal source 7
A sampling output voltage V having the same signal level as the signal level of n. There is a drawback that you can only get it.

[Purpose of the invention]

The present invention has been made with the above points in mind, and it is an object to propose a sampling bold circuit that does not lack such defects.

[Summary of the invention]

In order to achieve such an object, the present invention has an analog intermediate circuit of a heavy pressure follow-up operation type consisting of a differential amplifier circuit. The emitters of the transistors 21 and ρ are connected in common, and their connection point is connected to a constant current source 24 whose end is grounded. The collectors of transistors 21 and n are connected to a voltage source V via a current mirror circuit δ. Connected to 0.

An analog input signal source n connected in series with a Km bias voltage source is connected to the base of the 10,000 transistor 21 through a resistor, and the constant current source is sampled and controlled for opening operation for a sufficient sampling time. By doing so, transistors 21 and n are operated differentially. The base and collector of the other transistor 22 are connected by another pin 30, and the non-grounded end of a hold capacitor 31 whose one end is grounded is connected to the base, and the sampling voltage v8 generated at the connection point P3 is applied to the output buffer circuit 3.
2 to the output terminal 33.

The current mirror circuit 5 includes a pair of PNP transistors 35 and 36 whose bases are connected to each other, and each transistor A and 36 is connected to the transistors 21 and 22, respectively.
The base and collector of one of the transistors are connected to each other, so that the transistor 22 operates as a diode as shown in FIG.

In the above configuration, the transistor 2 of the differential amplifier circuit
When the voltages applied to the bases of 1 and n are equal to each other, the differential amplifier circuit is balanced and stable, and when the constant current source string is turned on, the constant current I of the constant current source string. is the direct current flowing through the transistors 35 and 36 of the current mirror circuit 6 and the transistors 21 and 22 of the differential amplifier circuit.In this stable state, the current of the analog input signal source n and that transistor also becomes . Therefore, the total current flowing from the current mirror circuit 5 to the differential amplifier circuit is . The constant current of the constant current source array is ■. Yes, the difference current ±21 flows through the line 30 between the base and collector of the transistor B to the hold capacitor 31 as a charge or release current. Thus, the sampling voltage v of capacitor 31
8 rises or falls, the current flowing into the constant current source string through the transistor 22 functioning as a diode and U7 increases or decreases, and the vt current flowing through the transistor 21 and hence 35 decreases or increases accordingly. This change also occurs in the current of transistor 36. Eventually, when the sampling voltage Vs matches the analog input voltage vin of the analog input signal source n due to the differential operation of the transistors 21 and n, the differential amplifier circuit returns to a stable state.

In this way, the sampling voltage v8 of the capacitor 31
is the analog input signal source n: pressure vi
It will change following n.

On the other hand, when the constant current source 24 turns off, current does not flow through the transistors 21 and n of the differential amplifier circuit and they become inoperative, and the current mirror circuit 5 also becomes inoperable. The sampling voltage v8 is maintained as it is.

As described above, according to the configuration shown in FIG. 3, the sampling voltage, voltage v8, of the hold capacitor 31 is charged and discharged so as to match the analog input voltage vin by the voltage balancing operation based on the differential operation of the differential amplifier circuit. As a result, the drawbacks caused by the sampling transistors 3°15 and 16 of the single current drive type as in the case of FIGS. 1 and 2, that is, the offset of the sampling voltage, are eliminated.
Problems such as sampling voltage response delay, sampling voltage drop during hold, and asymmetrical changes when sampling voltage rises and falls can be eliminated. Furthermore, the configuration shown in FIG. 3 does not have the disadvantage that the signal level of the sampling voltage V 1 shifts from the analog input voltage vin.

FIG. 5 shows a second embodiment of the invention, in this case a third embodiment.
In place of the pair of transistors 21 and n in the differential amplifier circuit B shown in the figure, transistors 4 each are connected to Darlington.
1, 42 and 43, 44. In this way, the same effect as in the above case can be obtained. In addition, according to the configuration shown in FIG. 5, the input impedance of the differential amplifier circuit B to the analog input voltage v1n and the sampling voltage v8 can be suppressed, thereby further stabilizing the differential operation.

FIG. 6 shows a third embodiment of the invention. In the current mirror circuit area of FIG. 3, four currents are passed through one set of transistors 51 and 36 to the circuit on the transistors 21 and 22 side. The same current is made to flow through the transistor 21 and the (b) path of η1iI11 through the transistors 52, 53, 55 and 56. Even in this case, the same effect as in the case of FIG. 3 can be obtained.

FIG. 7 shows a fourth embodiment. In this case, as shown by assigning the same reference numerals to the parts corresponding to those in FIG. 3, the current mirror circuit 25, which was wired with W in transistor 21 and η in FIG. Electrician. A current mirror circuit diagram is formed by a transistor 62 connected to a current constant current source 61 and a transistor 63 connected to the collector side of the transistor. Also, while changing the constant current flowing from the constant current source array of the differential amplifier circuit B to 2■o,
The constant current sources 24 and 61 are simultaneously turned on or off by the control circuit 4.

In the configuration shown in FIG. 7, when the differential amplifier circuit is stable, a current flows from the constant current source array to each transistor 21°. is flowing. In this state, the analog input voltage vin applied to the transistor 21 rises or falls, and the current of the transistor 21 becomes . When it becomes +1, the current flowing from transistor n into the constant current source array decreases or increases by that amount, and becomes ①o-1:i. On the other hand, a constant current ■ flows through the transistor 63 of the current mirror circuit 64. , a current of ±i is given to the capacitor 31 as a charging or discharging current.

As a result, when the sampling voltage V of the capacitor 31 increases or decreases, the current flowing from the transistor η into the constant current source array increases or decreases, and the current of the transistor 21 decreases or increases accordingly.

In the end, differential amplifier circuit B is the sampling of capacitor 31'
It becomes stable when the city voltage V matches the analog input voltage vin.

Therefore, also with the configuration of FIG. 7, it is possible to obtain the sampling voltage n voltage v8 that matches the analog input voltage V· at the capacitor 31, and the same effect as described above with respect to FIG. 3 can be obtained.

In the above description, the differential amplifier circuit n is configured with an NPN) transistor, and a current mirror circuit is added and 1. ) 4 is configured with a PNP) transistor, but
Even if the conductivity type of the transistor is reversed, a sampling and holding circuit can be constructed which can obtain the same effect as in the above case.

〔Effect of the invention〕

As described above, according to the present invention, the sampling voltage v8 of the hold capacitor 31 is balanced so as to match the analog input voltage vin by utilizing the differential operation of the differential amplifier circuit. 2, it is possible to easily obtain a sunblink-hold circuit suitable for an IC, which eliminates the drawbacks of the conventional configuration described above with reference to FIG.

[Brief explanation of the drawing]

1 and 2 are connection diagrams showing a conventional sampling and holding circuit, FIG. 3 is a connection diagram showing an embodiment of a sampling and holding circuit according to the present invention, and FIG. 4 is a connection diagram showing its principle configuration, 5 to 7 are connection diagrams showing other embodiments of the present invention. (a)...IC, 23...Differential amplifier circuit, power...
Constant current source, B...Carlen Miller (B) path, 26.
・・DC bias voltage source, n・−・Analog cutting edge temperature, 4・・Sampling control circuit, 31・・Hold capacitor, 32・・−Output buffer circuit, 61・・Constant current source, 64−・・Car Rent mirror circuit. Applicant's agent 1) Megumi Be, 2nd figure Kazuo Wakasugi, Commissioner of the Patent Office 1. Display of the case Showa μS Patent Application No. 4250 2, Name of the invention Sampling hold circuit 3, Person making the amendment Relationship to the case Patent applicant name (218) Sony Corporation 4, Agent address 150 (Telephone 03-) 470-6591
)Address: 3-10-5 Jingumae, Shibuya-ku, Tokyo ``Claims'' and ``Detailed Description of the Invention'' of the specification subject to amendment
Column 6, Contents of amendment (1) The scope of the claims of the present application is corrected as shown in the attached sheet. (2) Specification, page 3, line 1, page 5, line 15, line 10
On page 18, correct "current drive type" to "voltage drive type". (3) Same, page 3, lines 9 to 10, "resistance 8" is corrected to "signal source resistance 8". (4) Same, page 6, line 18, "same signal level as the signal level" is corrected to "J, same as the DC bias voltage." (5) Same, page 7, last line, "resistance section" should be changed to " Signal source resistance
I am corrected. Scope of claims 1. (a) A hold capacitor; and (b) a first transistor whose base receives an analog input voltage; and a second transistor whose base is connected to the hold capacitor; the emitters of the second transistor are commonly connected to each other to form a first constant voltage source; (C) a differential amplifier circuit connected to the collector sides of the first and second transistors and connected to the base and collector of the second transistor; and a current mirror circuit that causes a current corresponding to the change to flow through the hold capacitor when the voltage changes in accordance with the analog input voltage. 2. The current mirror circuit is configured to flow a current having the same current value as the current value of the collector 1Ill of the first transistor to the collector side of the second transistor. sampling and holding circuit. 3. The sampling according to claim 1, wherein the current mirror circuit is configured to flow a current having the same current value as the current value of the second current source to the collector side of the second transistor. hold circuit.

Claims (1)

[Claims] 1 (a) a hold capacitor; (b) the emitters of a first transistor receiving an analog input voltage at its base and a second transistor whose base is connected to the hold capacitor are commonly connected to each other; a differential amplifier circuit connected to a first constant current source and connected to the base and emitter of the second transistor; (e) a collector III! of the second transistor;
and a current mirror circuit connected to the current mirror circuit, which causes a current corresponding to the change in the current of the first transistor to flow through the hold capacitor when the current of the first transistor changes in accordance with the analog input voltage. 2. In the current mirror circuit, a current having the same N and H values as the current value on the collector side of the first transistor flows through the collector side of the second transistor, as claimed in claim 1. The sampling and hold circuit described in . 3. The current mirror circuit is configured to direct a current having the same current value as the current value of the second constant current source to the collector side of the second transistor. sampling and holding circuit.