JPS6210388B2 - - Google Patents

Info

Publication number
JPS6210388B2
JPS6210388B2 JP54054355A JP5435579A JPS6210388B2 JP S6210388 B2 JPS6210388 B2 JP S6210388B2 JP 54054355 A JP54054355 A JP 54054355A JP 5435579 A JP5435579 A JP 5435579A JP S6210388 B2 JPS6210388 B2 JP S6210388B2
Authority
JP
Japan
Prior art keywords
aging
lines
input
terminals
input signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54054355A
Other languages
Japanese (ja)
Other versions
JPS55146938A (en
Inventor
Yoshiaki Hayasaka
Isao Ookura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHO ERU ESU AI GIJUTSU KENKYU KUMIAI
Original Assignee
CHO ERU ESU AI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHO ERU ESU AI GIJUTSU KENKYU KUMIAI filed Critical CHO ERU ESU AI GIJUTSU KENKYU KUMIAI
Priority to JP5435579A priority Critical patent/JPS55146938A/en
Publication of JPS55146938A publication Critical patent/JPS55146938A/en
Publication of JPS6210388B2 publication Critical patent/JPS6210388B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/326Application of electric currents or fields, e.g. for electroforming
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2855Environmental, reliability or burn-in testing
    • G01R31/286External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2863Contacting devices, e.g. sockets, burn-in boards or mounting fixtures

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Description

【発明の詳細な説明】 この発明は半導体素子の種類により、エージン
グ基板上で入出力端子の接続を任意に切換えて動
作エージングする半導体素子エージング装置に関
するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device aging device that performs operational aging by arbitrarily switching connections between input and output terminals on an aging substrate depending on the type of semiconductor device.

一般に、半導体素子のエージングは製造工程中
に欠陥を含んだ半導体素子を高温動作させ、欠陥
を加速して不完全な半導体素子を不良にして、高
信頼度の半導体素子を得ることである。そして、
ある種類の半導体素子をエージングする場合には
第1図に示すように、その半導体素子に固有のプ
リント配線による端子接続を行ない、抵抗および
容量などの回路部品をとりつけたエージング基板
1を製作する。なお、第1図に示すエージング基
板1において、2a〜2dはそれぞれ図示せぬ半
導体素子を挿入するソケツト、3aおよび3bは
それぞれ電源電圧(接地電圧を含む)のプリント
配線、4aおよび4bはそれぞれ入力信号のプリ
ント配線である。そして、このように構成したエ
ージング基板1を多数枚第2図に示すエージング
装置5に入れて動作エージングを行なうものであ
る。すなわち、第2図に示すエージング装置5に
おいて、6は多数枚のエージング基板1を入れ、
高温(50〜200℃)を維持する恒温槽、7は温
度、供給電圧および入力信号などを制御する制御
パネル、8は入力信号の必要な端子を切換えるス
イツチである。そして、動作エージングを行なう
場合には制御パネル7により、恒温槽6の温度を
一定に保つと共に切換スイツチ8によつて必要な
端子を選択して入力信号を加え、半導体素子に所
定の電源電圧および入力信号電圧を供給し、動作
エージングを行なうものである。
In general, aging of semiconductor devices involves operating semiconductor devices containing defects at high temperatures during the manufacturing process to accelerate defects and make imperfect semiconductor devices defective, thereby obtaining highly reliable semiconductor devices. and,
When aging a certain type of semiconductor element, as shown in FIG. 1, an aging board 1 is manufactured by connecting terminals using printed wiring specific to the semiconductor element and mounting circuit parts such as resistors and capacitors. In the aging board 1 shown in FIG. 1, 2a to 2d are sockets into which semiconductor elements (not shown) are inserted, 3a and 3b are printed wirings for power supply voltage (including ground voltage), and 4a and 4b are inputs, respectively. This is printed signal wiring. A large number of aging substrates 1 thus constructed are placed in an aging device 5 shown in FIG. 2 and subjected to operational aging. That is, in the aging device 5 shown in FIG. 2, 6 contains a large number of aging substrates 1;
A constant temperature bath maintains a high temperature (50 to 200°C), 7 is a control panel that controls the temperature, supply voltage, input signals, etc., and 8 is a switch that switches the necessary terminals of input signals. When performing operational aging, the control panel 7 maintains the temperature of the thermostatic chamber 6 constant, and the changeover switch 8 selects the necessary terminals and applies input signals to the semiconductor devices at a predetermined power supply voltage and It supplies an input signal voltage and performs operational aging.

しかしながら、従来の半導体素子エージング装
置では他の種類の半導体素子をエージングする場
合には別の種類のエージング基板を製作しなけれ
ばならない。また、ゲートアレイ、トランジスタ
アレイのように、120端子にもおよび多数の入出
力端子を持ち、用途により入出力端子を変更する
ような汎用性のある論理素子をエージングする場
合にも、固定化したプリント配線をすると、多種
類のエージング基板を必要とする。また、全端子
をプリント配線しておき、汎用性を持たせると、
入出力端子の変更により、出力端子となつた場
合、スイツチなどの方法で切離す必要がある。そ
のうえ、全端子をプリント配線すると、この配線
の面積のために、エージング基板を大きくする
か、またはエージング基板に搭載する半導体素子
数を減す必要がある。一方、端子へのプリント配
線数を減し、搭載数を増そうとすれば、素子の種
類によつて入力端子が異なるため、入力端子がプ
リント配線されているか否かは確率的なものとな
つて充分なエージングを行なえない。このよう
に、論理素子をエージングする場合、多数の配線
と抵抗を要し、エージング基板を大きくするか、
あるいは素子の搭載数を少なくしなければならな
い。また、ある用途に限定した素子のエージング
基板を作る場合、入力端子を変更して使用する素
子については多種類のエージング基板を必要とす
る。そこでエージング基板の入力信号配線を除
き、電源電圧および接地電圧のみ配線し、エージ
ング基板面積を有効に利用して素子の搭載数を増
加させたものが提案されている。この場合、エー
ジング装置の入出力端子切換スイツチは不要とな
るが、素子が充分な動作状態におかれず、初期不
良素子を完全に取除くことができず、高信頼度の
素子が得られないなどの欠点があつた。
However, in the conventional semiconductor device aging apparatus, if another type of semiconductor device is to be aged, a different type of aging substrate must be manufactured. In addition, when aging general-purpose logic elements such as gate arrays and transistor arrays, which have as many as 120 input/output terminals and whose input/output terminals can be changed depending on the application, fixed Printed wiring requires many types of aging boards. Also, if all terminals are printed and wired for versatility,
If you change the input/output terminal and it becomes an output terminal, you will need to disconnect it using a switch or other method. Moreover, if all the terminals are printed and wired, it is necessary to increase the size of the aging board or reduce the number of semiconductor elements mounted on the aging board due to the area of the wiring. On the other hand, if you try to reduce the number of printed wiring to terminals and increase the number of installed terminals, the input terminals will differ depending on the type of element, so whether or not the input terminals are printed wiring becomes a probabilistic matter. Therefore, sufficient aging cannot be performed. In this way, when aging a logic element, a large number of wiring lines and resistors are required, and the aging board must be made large.
Alternatively, the number of mounted elements must be reduced. Furthermore, when making aging substrates for elements limited to certain uses, many types of aging substrates are required for elements whose input terminals are changed. Therefore, it has been proposed to remove the input signal wiring on the aging board and wire only the power supply voltage and ground voltage, thereby effectively utilizing the area of the aging board to increase the number of mounted elements. In this case, the input/output terminal switch of the aging device is not required, but the device is not kept in a sufficient operating state, and initial defective devices cannot be completely removed, making it impossible to obtain a highly reliable device. There were some shortcomings.

したがつて、この発明の目的は多数の入出力端
子を持ち、用途により、入出力端子が変更される
論理素子のエージングにおいても対応でき、素子
の搭載数も多くできる汎用性のある半導体素子エ
ージング装置を提供するものである。
Therefore, an object of the present invention is to provide a versatile semiconductor device aging device that has a large number of input/output terminals, can be applied to the aging of logic devices in which the input/output terminals are changed depending on the application, and can be equipped with a large number of devices. It provides equipment.

このような目的を達成するため、この発明はエ
ージング基板上に必要数の電源線、接地線、およ
び入力信号線をプリント配線し、この電源線、接
地線、入力信号線あるいはこれらの一部線上に接
続すると共に先端に接続ピンをもつ延長配線と、
半導体素子を挿入するソケツトから全端子を引出
し、その先端に接続端子を設け、所望の接続ピン
を接続端子に接続し、用途あるいは半導体素子の
種類により、変更した入力端子を任意に選択接続
し、このエージング基板を恒温槽に入れて高温動
作させ、エージングするものであり、以下実施例
を用いて詳細に説明する。
In order to achieve such an object, the present invention prints a necessary number of power supply lines, ground lines, and input signal lines on an aging board, and connects the power lines, ground lines, input signal lines, or some of these lines by printing them on the aging board. An extension wiring that connects to the terminal and has a connecting pin at the tip,
Pull out all the terminals from the socket into which the semiconductor element is inserted, provide a connection terminal at the tip, connect the desired connection pin to the connection terminal, and arbitrarily select and connect the changed input terminal depending on the application or type of semiconductor element. This aging substrate is placed in a constant temperature bath and operated at a high temperature for aging, and will be described in detail below using examples.

第3図はこの発明に係る半導体素子エージング
装置の一実施例を示す平面図である。同図におい
て、9はその詳細を第4図に示すエージング基板
である。
FIG. 3 is a plan view showing an embodiment of the semiconductor device aging apparatus according to the present invention. In the same figure, 9 is an aging board whose details are shown in FIG.

なお、第4図に示すエージング基板9におい
て、10a〜10dは図示せぬ半導体素子を挿入
するためのソケツト、11aおよび11bはこの
エージング基板9上にプリント配線した電源線お
よび接地線、12aおよび12bはこのエージン
グ基板9上にプリント配線した入力信号線、13
はソケツト10a〜10dの全端子からそれぞれ
プリント配線によつて延長され、先端に接続端子
13aを持つソケツト延長配線、14は入力信号
線12aおよび12b上にそれぞれ接続し、先端
に接続ピン14aを持ち、この接続ピン14aを
必要なソケツト延長配線13の接続端子13aに
接触するための延長配線、15は使用しない延長
配線13の接続ピン14aを接触保持するための
レストピンである。
In the aging board 9 shown in FIG. 4, 10a to 10d are sockets for inserting semiconductor elements (not shown), 11a and 11b are power supply lines and ground lines printed on the aging board 9, and 12a and 12b. is an input signal line printed on this aging board 9, 13
14 is a socket extension wiring which is extended from all the terminals of the sockets 10a to 10d by printed wiring and has a connecting terminal 13a at the tip, and 14 is connected to the input signal lines 12a and 12b, respectively, and has a connecting pin 14a at the tip. , an extension wire for contacting this connecting pin 14a with the connecting terminal 13a of the necessary socket extension wire 13, and a rest pin 15 for holding the connecting pin 14a of the unused extension wire 13 in contact.

なお、この場合、制御パネル上に入出力端子を
切換える切換スイツチは不要であることはもちろ
んである。
In this case, it goes without saying that there is no need for a switch on the control panel to switch between input and output terminals.

次に、上記構成に係る半導体素子エージングの
動作について説明する。
Next, the operation of semiconductor device aging according to the above configuration will be explained.

まず、ソケツト10a〜10dに動作エージン
グすべき半導体素子を挿入する。そして、入力信
号線12aおよび12b上の延長配線14の接続
ピン14aをソケツト10a〜10dの端子から
延長したソケツト延長配線13の入力信号の必要
とする接続端子13aに接続する。そして、この
エージング基板9を第3図に示す半導体素子エー
ジング装置の恒温槽6に入れ、一定温度を維持
し、半導体素子に所定の電源電圧(接地電圧を含
む)および入力信号電圧を供給して動作エージン
グを行なう。
First, semiconductor devices to be subjected to operational aging are inserted into the sockets 10a to 10d. Then, the connection pin 14a of the extension wiring 14 on the input signal lines 12a and 12b is connected to the connection terminal 13a required for the input signal of the socket extension wiring 13 extended from the terminals of the sockets 10a to 10d. Then, this aging substrate 9 is placed in a constant temperature chamber 6 of a semiconductor device aging device shown in FIG. 3, and a constant temperature is maintained, and a predetermined power supply voltage (including ground voltage) and input signal voltage are supplied to the semiconductor device. Perform motion aging.

なお、以上は多数入出力端子を持ち、用途によ
つて入出力端子を変更する論理素子のエージング
装置について説明したが、半導体素子の種類に限
定されるものではなく、必要数の電源線、接地
線、入力信号線をあらかじめ配線しておけば、あ
らゆる半導体素子の端子接続を変更することによ
り、エージングすることができることはもちろん
である。
The above explanation describes an aging device for logic elements that has a large number of input/output terminals and changes the input/output terminals depending on the application. Of course, if the lines and input signal lines are wired in advance, aging can be performed by changing the terminal connections of any semiconductor element.

また、実施例では電源線が固定の場合について
説明したが、入力信号線と同様に電源線を接続ピ
ンによる配線にすれば、電源ピンの異なつた多種
類の半導体素子に適用できることはもちろんであ
る。
In addition, although the example explained the case where the power supply line is fixed, it goes without saying that if the power supply line is wired with connection pins in the same way as the input signal line, it can be applied to many types of semiconductor devices with different power supply pins. .

以上、詳細に説明したように、この発明に係る
半導体素子エージング装置によればエージング基
板に多数の配線が不必要になり、有効面積が大き
く、半導体素子の搭載数の拡大を図ることができ
る。しかも、多数の入出力端子を持ち、用途によ
り入出力端子が変更される半導体素子についても
対応できる汎用性を有し、動作状態でのエージン
グができ、高信頼性の半導体素子が得られるなど
の効果がある。
As described above in detail, the semiconductor device aging apparatus according to the present invention eliminates the need for a large number of wiring lines on the aging board, has a large effective area, and can increase the number of semiconductor devices mounted. Moreover, it has the versatility to handle semiconductor devices that have a large number of input/output terminals and whose input/output terminals are changed depending on the application, and can be aged in the operating state, resulting in highly reliable semiconductor devices. effective.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のエージング基板を示す上面図、
第2図は第1図に示すエージング基板を装着した
従来の半導体素子エージング装置を示す正面図、
第3図はこの発明に係る半導体素子エージング装
置の一実施例を示す正面図、第4図は第3図に装
着するエージング基板を示す上面図である。 1…エージング基板、2a〜2d…ソケツト、
3aおよび3b…プリント配線、4aおよび4b
…プリント配線、5…エージング装置、6…恒温
槽、7…制御パネル、8…スイツチ、9…エージ
ング基板、10a〜10d…ソケツト、11aお
よび11b…電源線および接地線、12aおよび
12b…入力信号線、13…ソケツト延長配線、
13a…接続端子、14…延長配線、14a…接
続ピン、15…レストピン。なお、同一符号は同
一または相当部分を示す。
Figure 1 is a top view showing a conventional aging board;
FIG. 2 is a front view showing a conventional semiconductor device aging apparatus equipped with the aging substrate shown in FIG.
FIG. 3 is a front view showing an embodiment of the semiconductor device aging apparatus according to the present invention, and FIG. 4 is a top view showing an aging substrate mounted on the device shown in FIG. 1... Aging board, 2a to 2d... Socket,
3a and 3b...printed wiring, 4a and 4b
...Printed wiring, 5...Aging device, 6...Thermostatic chamber, 7...Control panel, 8...Switch, 9...Aging board, 10a to 10d...Socket, 11a and 11b...Power line and ground line, 12a and 12b...Input signal Line, 13... socket extension wiring,
13a... Connection terminal, 14... Extension wiring, 14a... Connection pin, 15... Rest pin. Note that the same reference numerals indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 1 エージング基板上に必要数の電源線、接地線
および入力信号線をプリント配線し、この電源
線、接地線、入力信号線、あるいはこれらの一部
線上に接続すると共に先端に接続ピンを持つ延長
配線と、半導体素子を挿入するソケツトから全端
子を引出し、この先端に接続端子を設け、所望の
接続ピンを接続端子に接続し、用途および半導体
素子の種類により、変更した入力端子を任意に選
択接続し、このエージング基板を恒温槽に入れて
高温動作させ、エージングすることを特徴とする
半導体素子エージング装置。
1 Print the required number of power lines, ground lines, and input signal lines on the aging board, connect them to the power line, ground line, input signal line, or some of these lines, and connect an extension with a connecting pin at the tip. Pull out all the terminals from the socket into which the wiring and semiconductor element will be inserted, provide a connection terminal at the end of this, connect the desired connection pin to the connection terminal, and select the changed input terminal arbitrarily depending on the application and type of semiconductor element. A semiconductor device aging device characterized in that the aging substrate is placed in a constant temperature bath, operated at high temperature, and aged.
JP5435579A 1979-05-02 1979-05-02 Aging device for semiconductor element Granted JPS55146938A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5435579A JPS55146938A (en) 1979-05-02 1979-05-02 Aging device for semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5435579A JPS55146938A (en) 1979-05-02 1979-05-02 Aging device for semiconductor element

Publications (2)

Publication Number Publication Date
JPS55146938A JPS55146938A (en) 1980-11-15
JPS6210388B2 true JPS6210388B2 (en) 1987-03-05

Family

ID=12968317

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5435579A Granted JPS55146938A (en) 1979-05-02 1979-05-02 Aging device for semiconductor element

Country Status (1)

Country Link
JP (1) JPS55146938A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5914074U (en) * 1982-06-18 1984-01-27 利昌工業株式会社 Insulating substrate for semiconductor device testing
JPS5917870U (en) * 1982-07-24 1984-02-03 利昌工業株式会社 Flat semiconductor package test substrate
JPS6033661U (en) * 1982-07-31 1985-03-07 利昌工業株式会社 Small outline package type semiconductor device testing board
JPH04198776A (en) * 1990-11-28 1992-07-20 Mitsubishi Electric Corp Burn-in device

Also Published As

Publication number Publication date
JPS55146938A (en) 1980-11-15

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