JPH03150482A - Static burn-in board - Google Patents
Static burn-in boardInfo
- Publication number
- JPH03150482A JPH03150482A JP1270988A JP27098889A JPH03150482A JP H03150482 A JPH03150482 A JP H03150482A JP 1270988 A JP1270988 A JP 1270988A JP 27098889 A JP27098889 A JP 27098889A JP H03150482 A JPH03150482 A JP H03150482A
- Authority
- JP
- Japan
- Prior art keywords
- board
- pin socket
- socket
- burn
- pins
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003068 static effect Effects 0.000 title abstract description 6
- 239000000758 substrate Substances 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体集積回路(以下ICと称する)に負荷
を与えた状態で行なわれテス)K用いられるテスト用基
板(以下バーンインボードと称する)に関し、多品種に
対応できる様に標準化し、コストが安く作製できるもの
である。[Detailed Description of the Invention] [Industrial Application Field] This invention is carried out with a load applied to a semiconductor integrated circuit (hereinafter referred to as IC). Regarding this, it has been standardized so that it can be applied to a wide variety of products, and it can be manufactured at low cost.
第4図は従来のバーンインボード全示す斜視図である。 FIG. 4 is a perspective view showing the entire conventional burn-in board.
図において(9)は、工0’i固定するICソケット。In the figure, (9) is the IC socket to which the workpiece 0'i is fixed.
(lO)は前記工0を固定するICソケット(9)を並
べるプリント基板、121は前記IOを固定するICソ
ケット(9)の電源供給用のコネクタ、131 d I
Q紀ICソケット(91に装着した工Cである。(lO) is a printed circuit board on which IC sockets (9) for fixing the IO are lined up; 121 is a connector for power supply to the IC socket (9) for fixing the IO; 131 d I
Qi IC socket (This is the engineering C installed on 91.
従来のバーンインボードは、バーンインヲ行う工C(3
1をICソケット(9)に挿入した後に/< −ンイン
を行っていた。Conventional burn-in boards require a burn-in process C (3
1 was inserted into the IC socket (9), /<- was performed.
従来のバーンインボードは、前記の様に構成されている
ので形状の異った工OKはそれに対応する工0ソケット
を備えたバーンインボードを使用しなければならない。Conventional burn-in boards are constructed as described above, so if you want to use a different shape, you must use a burn-in board with a corresponding socket.
また、バーンインボードを作製するコストが高いなどの
問題点があった。In addition, there were other problems such as the high cost of manufacturing the burn-in board.
この発明はこのような問題点を解決する為になされたも
ので、形状の異ったICに対応できコストが安くなるこ
とを目的とする。This invention was made to solve these problems, and its purpose is to be compatible with ICs of different shapes and to reduce costs.
この発明は、複数のピンを有する工C倉俣数取り付けて
、これらのIOに負荷を与えた状態でテストするものに
おいて、前記IOと同一ピッチであり、前記工Oのピン
が挿入される複数の穴を備えたものである。In this invention, a number of pins are installed in a factory C Kuramata having a plurality of pins, and a test is carried out with a load applied to these IOs. It is equipped with a hole.
この発明によれば、形状の異った工0にも適応でき、コ
ストの安いスタティックバーンインボードを作製するこ
とができる。According to the present invention, it is possible to manufacture a static burn-in board that can be applied to workpieces having different shapes and is inexpensive.
この発明の一実施例を第1図、第2図及び第8図に示す
。第1図において、理解の便宜上、穴内の構造及び穴内
に埋め込むピンソケットは省略して示しである。An embodiment of the invention is shown in FIGS. 1, 2, and 8. In FIG. 1, for convenience of understanding, the structure inside the hole and the pin socket embedded in the hole are omitted.
11[、ICに電圧を与えることができる構造を持ち多
数の穴のあいた基板、12)は萌記工0に電圧を与える
ことができる構at持ち多数の穴のあいた基板Ill:
電圧金供給する従来と同様なコネクタである。・3:は
前記基板Illに装着したIC114)は前記10Kt
Etを与えることができる構造を持ち多数の穴のあいた
基板Illの穴の一つである。11) A board with a structure capable of applying voltage to the IC and having many holes; 12) A board having a structure capable of applying voltage to the IC and having many holes Ill:
It is a connector similar to the conventional one that supplies voltage.・3: The IC114) mounted on the board Ill is the 10Kt
This hole is one of the holes in the substrate Ill, which has a structure that can provide Et and has many holes.
第2図は前記ICに′電圧を与えることのでき遭0
る構造を袴 のあいた基板の穴の一つ14)の斜視図
t−示す。・6(は電源電圧(I−流すことのできる導
体層、(6)は絶縁層、17)は接地層である。FIG. 2 shows a perspective view of one of the holes 14) in the perforated board, which shows the structure that allows voltage to be applied to the IC.・6 (is a conductor layer through which the power supply voltage (I) can flow, (6) is an insulating layer, and 17) is a ground layer.
第8図に前記IOK電圧を与えることのできる構造’に
4?ち多数の穴のあいた基板の穴の1つ4)にピンソケ
ットを挿入した状態を示す断面図を示す。Figure 8 shows a structure capable of applying the IOK voltage to '4? This is a cross-sectional view showing a state in which a pin socket is inserted into one of the holes 4) of a board with many holes.
(8)は従来と同様な構造を持つピンソケットであるO
この9111において、例えばピンソケット(8)に電
源電圧?与えたい場合、前記工OKm圧を与えることが
できる構造を持ち多数の穴のあいた基板の穴の一つnl
Kピンソケット+81 ft伸入し。(8) is a pin socket with the same structure as the conventional one. In this 9111, for example, the pin socket (8) has a power supply voltage? If you want to apply pressure, use one of the holes in the board with many holes, which has a structure that can apply the above-mentioned pressure.
K pin socket +81 ft extension.
前記電源電圧を流すことのできる導体層nn’c接触さ
せ、ピンソケット(8)に電源電圧(f−与える。A conductive layer nn'c through which the power supply voltage can flow is brought into contact, and a power supply voltage (f-) is applied to the pin socket (8).
このピンソケットにICピンを挿入することにより工0
1C11を源電圧を加えることができる。接地を与える
場合も而様な方法により行うことができる。このように
構成されたスタティックノく一ンインボードにおいて、
ピンソケット(8)ヲ用いることで基板の各所に電源電
圧を与えたり、接地を与えることができる。By inserting the IC pin into this pin socket, you can
1C11 can be applied as a source voltage. Grounding can also be provided in various ways. In the static kuichi inboard configured in this way,
By using the pin socket (8), power supply voltage and grounding can be applied to various parts of the board.
以上のように、この発明によれば、スタティックバーン
インボードに工Cのピンが挿入される複数の穴を備えた
ので、ピンソケットを用いることで形状の異りなIOK
も適応ができ、コストが安くなるという効果が得られる
。As described above, according to the present invention, since the static burn-in board is provided with a plurality of holes into which the pins of the design C are inserted, by using the pin socket, the IOK of different shapes can be inserted.
It can also be adapted and has the effect of reducing costs.
第1図はこの発明の一実旌例倉示すスタティックバーン
インボード図、第8図は、第1図の穴の詳細な構造を示
す断面斜視図、第3図はピンソケットを装着した状態で
の断面図である。
第4図は従来のバーンインボードを示す斜視図である。
図において、111は基板、(21はコネクタ、131
にIO,+41に工OK電圧を与えることのできる構造
をもった穴、+51に電源電圧層、(6)は絶縁層、8
)ハピンソケットである。
なお、各図中、同一符号に同一
部分を示す。Fig. 1 is a static burn-in board diagram showing a practical example of this invention, Fig. 8 is a cross-sectional perspective view showing the detailed structure of the hole in Fig. 1, and Fig. 3 is a diagram showing a state in which a pin socket is installed. FIG. FIG. 4 is a perspective view showing a conventional burn-in board. In the figure, 111 is a board, (21 is a connector, 131
IO, +41 is a hole with a structure that can give a working voltage, +51 is a power supply voltage layer, (6) is an insulating layer, 8
) It is a hapin socket. In addition, the same parts are indicated by the same reference numerals in each figure.
Claims (1)
れらの集積回路装置に負荷を与えた状態でテストするも
のにおいて、前記集積回路装置と同一ピッチであり、前
記集積回路装置のピンが挿入される複数の穴を備えたス
タテイツクバーンインボードIn a test in which a plurality of integrated circuit devices having a plurality of pins are attached and a load is applied to these integrated circuit devices, the pitch is the same as that of the integrated circuit device, and the pins of the integrated circuit device are inserted. State burn-in board with multiple holes
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1270988A JPH03150482A (en) | 1989-10-17 | 1989-10-17 | Static burn-in board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1270988A JPH03150482A (en) | 1989-10-17 | 1989-10-17 | Static burn-in board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03150482A true JPH03150482A (en) | 1991-06-26 |
Family
ID=17493832
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1270988A Pending JPH03150482A (en) | 1989-10-17 | 1989-10-17 | Static burn-in board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03150482A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100688544B1 (en) * | 2005-04-20 | 2007-03-02 | 삼성전자주식회사 | Module for testing burn-in stress of semiconductor package |
JP2013088343A (en) * | 2011-10-20 | 2013-05-13 | Renesas Electronics Corp | Method for manufacturing semiconductor device |
-
1989
- 1989-10-17 JP JP1270988A patent/JPH03150482A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100688544B1 (en) * | 2005-04-20 | 2007-03-02 | 삼성전자주식회사 | Module for testing burn-in stress of semiconductor package |
JP2013088343A (en) * | 2011-10-20 | 2013-05-13 | Renesas Electronics Corp | Method for manufacturing semiconductor device |
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