JPS62102485A - Digital signal recording and reproducing device - Google Patents

Abstract

PURPOSE:To write as many as reproduction data in an error correction memory by adding an address showing the block order of divided data so as to decide whether an error can be pinpointed at an address or not and controlling writing data in the error correction memory. CONSTITUTION:A demodulator 7 demodulates a divided data block which is reproduced by a recording and reproducing device, and an address block generator circuit 9 generates the address added in order to show the block order at the time of writing. Only when the error place is decided at the address, writing block data in the error correction memory 11 is inhibited through a memory write control circuit 10. Accordingly the block data including an error is also written in the memory 11. A number of reproduction data ensure the probability of the error correction, whereby cases decided to be correction impossible can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application 3 B/ The present invention relates to a digital signal recording and reproducing apparatus for recording and reproducing digital data.

BACKGROUND OF THE INVENTION Conventional digital signal recording and reproducing devices include, for example, 8
There is a PCM audio recording and reproducing device for M video tape recorders. The outline of this is as follows: Television Society of Japan Technical Report VR61-
About 2r8mi IJ Video (2) Focusing on Audio Technology''.

FIG. 5 shows a typical block configuration of this conventional digital signal recording/reproducing apparatus. 21 is a data division circuit that divides digitized audio data;
22 is a block address addition circuit that assigns addresses to data divided into blocks; 23 is a cyclic code (CRCC) for error detection and correction; P; an error detection and correction code configuration circuit that generates two parity codes; 2゛4 is”
: A synchronization signal addition circuit that adds a synchronization signal to the block configured with the code; 25 is a modulation circuit; 26 is a recording/reproducing device;
27 is a demodulation circuit, 28 is an intra-block error detection circuit that detects block errors, 29 is an error correction memory, 3o is an error correction circuit, and 31 is an output interface that rearranges the data string in the same manner as when it is input and outputs it. .

In the conventional digital signal recording and reproducing apparatus configured as described above, the error detection and correction code configuration circuit 23 performs the following operations.
After interleaving the divided audio data between blocks to generate two parities P and Q, 8 words of block address 8 bits, data 16 bits,
CRCC is applied to a total of 168 bits of data, including 16 bits of 1 word of P parity and 16 pits of 1 word of Q parity.
Generates 16 bits. Then, the synchronization signal addition circuit 24
At this point, a 3-bit synchronization signal for block synchronization is added. As a result, the recorded signal sequence takes the form shown in FIG. This is then modulated by the modulation circuit 25 and recorded in the recording/reproducing device 26.

During reproduction, the demodulated data becomes the same signal sequence as shown in FIG. 6 as during recording, but this contains data errors and requires error detection and correction. To perform error detection and correction, the reproduced page data must first be written to memory along with the error detection information within the block. When writing into this memory, the memory writing position is determined using the reproduction address. Therefore, if the reproduction address is incorrect, it will lead to subsequent error correction malfunctions. Therefore, in this conventional example, a CRCC for error detection is added to the address as well, so if an error is detected, it is assumed that the address may also be an error, and the error detection by this CRCC is used to write the address to the memory. Prohibits clumping of reproduced data, and writes information with error detection flags set for all data in the block to memory. The intra-block error detection circuit 28 performs this.

Problems to be Solved by the Invention However, in the above configuration, even if a data error during playback is part of data other than a block address, it is treated as a block address error and is stored in the error correction memory. does not write any data, and all of the data in that block is erroneous and becomes completely different data. Therefore, a flag signal indicating that the block contains 6 pages of errors is added, and the reproduced data is stored in the memory. The problem is that there is a higher probability of error correction using the data written in the memory and the flag signal than when the data is written into the memory. Further, even if only the block address is in error and the data in that block is correct, the data is treated as an error and the data is not written, so there is a problem in that the probability of uncorrectability increases as in the above case.

In view of this, the present invention writes as much reproduced data as possible even if it contains errors when writing reproduced data to an error correction memory before performing an error correction operation, thereby making error correction impossible. It is an object of the present invention to provide a digital signal recording and reproducing device that reduces the probability that

Means for Solving the Problems The present invention provides means for adding check symbols to block addresses and block data to enable error position detection, means for detecting error positions, and block address data. The present invention is a digital signal recording and reproducing apparatus that includes means for making a determination, and means for controlling writing of reproduced block data into an error correction memory based on the result.

According to the present invention, with the above-described configuration, a check symbol that can detect the error position is added to the reproduced block, so this is used to determine whether the error position is in the block address section, and if the error position is not in the block address, the check symbol is added to the reproduced block. The reproduced data is written to the error correction memory according to the block address, and if there is an error in the block address, the reproduced data is written to the error correction memory according to the block address and error detection result by the block address generation means. By controlling writing and writing as much reproduced data as possible to the error correction memory, it is possible to reduce the chances of determining that error correction is impossible during the error correction operation.

Embodiment FIG. 1 shows a block configuration of a digital signal recording and reproducing apparatus in an embodiment of the present invention. In FIG. 1, 1 is a data division circuit that divides digital data, 2 is a block address addition circuit that adds addresses to the divided data, 3 is an error detection and correction code configuration circuit that adds check symbols for error detection and correction; 4 is a synchronization signal addition circuit that adds a synchronization signal to the coded signal; 6;
6 is a recording/reproducing device; 7 is a demodulation circuit that demodulates data from the reproduced signal; 8 is an intra-block error detection/judgment circuit for detecting errors within a block; 9 is a synchronization circuit. a block address generation circuit that generates a block address from a signal; 10 a write control circuit that controls writing of reproduced data to an error correction memory;
11 is a memory circuit for error correction; 12 is an error correction circuit;
Reference numeral 13 denotes a data output interface circuit that outputs the same data string as that at the time of input.

The operation of the digital signal recording/reproducing apparatus of this embodiment configured as described above will be described below.

In this embodiment, the input digital data goes to 9-
7 4 bytes (hereinafter abbreviated as 4KB).

The data input to the data division circuit 1 is divided into 32B each.
Divided into 28 groups. A block address 15 is added to each group of data by a block address adding circuit 2. The data to which the block address has been added is subjected to error detection and error detection during reproduction in the error detection and correction code configuration circuit 3.
Check data (check symbols) C1 and C2 necessary for correction are added. The following code structure is constructed on the Galois field C;F(2) in which 1B is one symbol. Then, a synchronization signal 14 is added to each group by a synchronization signal adding circuit 4,
The signal configuration is as shown in FIG. Furthermore, in the synchronization signal addition circuit 4, 4K is added to the top of the blocks shown in FIG.
Unit synchronization 2o indicating the start of recording data of B.
It is added together with the preamble signal 19 for clock phase synchronization during clock reproduction to create the signal sequence shown in FIG.

Here, the test symbol is configured as shown below, for example. The test symbols denoted by C1 are four symbols, and are a (36,32)1o Page Norm code in the Galois field GF(28). This generates 4 test symbols C1 from 32 symbols of data taken out by shifting the position in the block by 1 symbol every 3 blocks, and arranges it at the position shifted by 1 symbol every 3 blocks.

The parity check matrix H1 for generating test symbols is shown by equation (1), and α1 is an element of GF(2'').

The generation equation is shown by equation (2).

Hlwl-o・old・mark・(2) Here, Wl is data”+1 (block address i
(j-th data of block address i) and check symbol c1..1v1 (j-th check symbol of block address i) as an element.

Wl = (D(m:], OID(m+3), 1
(m+3n), n:”'°°D(m+cho 31'...
...D C111fn+93], 0I01[m+96], 1tC
1 [m+99], 21” (m+102), 3)
--゛knock-----(1) 11 to-/ [] indicates the value of mod128.

0≦m≦127, 0kon≦31 According to this check symbol, it is possible to correct a 2-symbol error among the symbols of Wl, and if the error position is known, it can be corrected with a 4-symbol error. .

Next, a check symbol C2 is generated from the address, data, and C1 in the same block. C2 is a 2-symbol Reed-Solomon code of (39, 37) in Galois field GF(2”). Check matrix H2 for generating check symbols
is shown by equation (4), and the generation equation is shown by equation (6).

H2WIT-〇 ・・・・・・・・・(6
) However, W2-(Am+ Dm, O9Dm, 1""" D
m, n"""Dm, 31 + "m, O...
...C1m, 3. C2m,. .

02m1) Here, Am, D, C1m・C2・respectively represent the address, data, and C1°C2 of the block address m. According to this test symbol, it is possible to detect three types of errors: no error, error position detected by one symbol error, and error of two or more symbols. Showing the series of Wl and W2, the fourth
It will look like the figure.

The signal configured as described above is input to the modulation circuit 5, converted into a modulation signal necessary for recording, and sent to the recording/reproducing device 6 for recording.

The signal is reproduced from the recording/reproducing device 6 and demodulated by the demodulation circuit 7 to obtain the signal sequence at the time of recording (Fig. 3), but this contains errors, and these errors are detected and corrected. There is a need to. For this purpose, the check symbols C1 and C2 are added as described above. In order to correct this error, it is necessary to once store the reproduced data in memory. At this time, since an address is added to the block, even if the synchronization of the block is disrupted, data can be recorded in a predetermined location in the memory based on the address, reducing the probability that errors cannot be corrected due to synchronization errors. It can be lowered.

However, if the configuration shown in the conventional example is 13 base/base, even if there is an error somewhere other than the address in the block, the address is considered to be incorrect and the entire block is treated as error data and the data must not be written to the memory 11. However, it has the disadvantage of increasing the number of error data. In order to prevent the number of error data from increasing, the following operation is performed.

The demodulated signal is sent to an intra-block error detection/judgment circuit 8 to determine whether or not there is an error in the W2 sequence and its location. This is the lead of W2 series (39°3).
Since the Solomon code is composed of (4), (5) 2K, J:, the syndrome S shown in equation (6) is
This is done by generating .

W2i is the first element of the received data of W2 The result of this syndrome calculation S○ =31==Q ......('7)14
If it is b/ , it indicates no error. If there is one symbol error, the result of syndrome calculation is 5o=Ei
~O 3-E i al 40 111111 ,,,
(8) becomes. Here, E is an error pattern of an error symbol, and satisfies 0≦i≦38 (9). And, i is the element ai according to the following formula
From this, we can find i. Next 2
If the error is more than a symbol, i〉38 (11).

On the other hand, the block address generation circuit 9 detects the unit synchronization signal, initializes the block address counter,
Counts based on block synchronization signal detection. Even if this block synchronization signal is not detected, a pseudo block synchronization signal is generated at a predetermined position to prevent the count value from shifting. Then, the playback address is compared with the Callan) address, a match/mismatch signal is generated, and after the mismatch continues/ζ, the address value for which no error was detected in the W2 series block is counted as the block address counter. It is used to reset the block address counter and correct errors in the block address counter.

Next, the memory write control circuit basically writes data other than the W2 address to the memory based on the reproduction address so that the next error correction can be performed, but if the address is wrong, Since error correction cannot be performed correctly,
j Using the output of the block error detection judgment circuit 8 and the output of the block address generation circuit, write the memo I shown in Table 1.
Jli control and error detection flag settings.

Table 1 Here, the meaning of the error detection flag is...
・Possibility of symbol error is less than 0 and @ is smaller than 17ba@... The probability of symbol error is small...
...The symbol is highly error-prone @...The symbol rri is all < error. In the case of the conventional example, if an error is detected, the error detection flag is set to an error state without writing to the memory. This is true M
In the case of Table 1 in the example, this is a case where there is an error of 2 or more symbols and the address and counter do not match, and in the conventional example, all of Table 1 are in this state. As is clear from this, the conventional example has the disadvantage that the error condition is magnified to a point larger than the actual error.

The error correction circuit 12 performs error correction using the data and check symbols CI and C2 written in the error correction memory 11 together with the error detection flag.

According to the check symbol C1, errors of up to two symbols can be corrected, and erasure correction is possible, which can correct up to four symbols if there is a pointer indicating the error position. After performing correction using C1, further error detection is performed using C2,
Data errors can be removed by further performing corrections using C1 for 18 pages/page. Various methods can be considered for this correction, but
Since this is not the purpose of the present invention, it will not be discussed here. However, since the memory contains as much information about the reproduced data as possible, it is easy to imagine that correction will become possible even in a state where correction was impossible in the conventional example.

The data for which error correction has been completed is outputted from the memory 11 through the data output interface 13 as the same data string as input.

Note that in this example, two symbols were used as C2, but
Similar operations can be achieved even with a larger number of symbols. Further, although the Reed-Solomon code is used, the spirit of the present invention does not change in any way even if other error detection codes capable of detecting error positions are used.

As described in detail, according to the present invention, when performing error correction on reproduced data, it is possible to write as much reproduced data as possible to the error correction memory. It is possible to reduce the chances of making a judgment, and there is almost no situation in which incorrect data is obtained, and it is possible to confuse the data, which has a great practical effect.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a digital signal recording and reproducing apparatus according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of a signal configuration of the embodiment, FIG. 3 is a recording signal configuration diagram of the embodiment, and FIG. 4 is an explanatory diagram of the error detection and correction code configuration of the same embodiment, and FIG. 6 is a block diagram of a conventional digital signal recording and reproducing apparatus.
The figure is a signal configuration diagram of the conventional example. 2...Block address addition circuit, 3...
...Error detection and correction code configuration circuit, 4...Synchronization signal addition circuit, 8...Intra-block error detection and determination circuit, 9...Block address generation circuit, 1o...
...Memory write control circuit.

Claims (2)

[Claims] (1) When recording and reproducing digital data in units of a certain capacity, a means for dividing said capacity into a plurality of blocks, and a means for adding a block address, which is data indicating the order of each block of the divided data. means for adding a check symbol to the block address and data in the block to enable detection of the position of an error; means for detecting an error in the block during playback; 1. A digital signal recording and reproducing apparatus, comprising: means for determining whether or not there is an error correction block; and means for controlling writing of reproduced block data into an error correction memory according to the result of the determination means. (2) means for dividing the capacity into a plurality of blocks when recording and reproducing digital data in units of a certain fixed capacity; means for adding a block address indicating the order of each block of the divided data; means for adding a check symbol to enable error position detection to address and block data; means for adding a block synchronization signal to the beginning of these blocks; and means for adding a block address, check symbol, and block synchronization signal. means for arranging the blocks in chronological order and adding a unit synchronization signal to the beginning of the blocks; means for detecting errors in the blocks during playback; means for counting block synchronization signals and generating block addresses; As a result, a first determining means determines whether the error position is at the block address, a second determining means compares and determines the reproduced block address and the block address generated during the reproduction, and the first and A digital signal recording and reproducing apparatus comprising means for controlling writing of reproduced block data into an error correction memory based on the second determination result.