JPS62102228A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To expand the life of an active matrix type liquid crystal display device by reading out a voltage being impressed to a liquid crystal display picture element at present at the time of refreshing operation, inverting and amplifying the voltage and applying the inverted and amplified voltage to the picture element again. CONSTITUTION:The capacity levels C14, C16 of dummy cells 8, 9 are precharged to intermediate potential levels '1', '-1' respectively by precharge voltage generating circuits 10, 11. When signals (a), (c) are turned to 'H' at time t1, prescribed switch elements are closed, a scanning signal line (m) is connected to dummy lines na, nb to make both the signal lines equal potential and disconnected at time t2. At time t3, the scanning electrode l1 of a picture element 1 and the line (b) are turned to 'H', prescribed elements are closed, respective potential levels of the C14, C16 are divided by respective capacity values and stray capacity values and the potential of C3 is also divided by floating capacity CA. The voltage of the scanning line (m) is compared with that of the dummy lines na, nb by comparators 6, 7 respectively, the compared values are converted into ternary value by a ternary conversion output circuit 12 on the basis of the prescribed method, and at time t5, the dummy lines na, nb are connected to the scanning signal line (m) by a signal (d). Since an alternate voltage is applied to a capacity C in an element 1 on the basis of the ternary conversion output (k) during the period until an element 2 is turned off and an AC field can be impressed to a liquid crystal element 4 every refreshing operation, the life of the display device can be expanded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a liquid crystal display device, and particularly to an active matrix type liquid crystal display device having an inversion refresh function suitable for using a liquid crystal cell as a memory element.

[Background of the invention]

In recent years, large images have been used as display devices to reduce power consumption.

Active matrix type liquid crystal display devices have attracted attention in terms of flatness and miniaturization, and some have even appeared that have added a display data entertainment function and a display data refresh function to these devices, and use the display device itself as a RAM. An example of such a device is the one described in Japanese Patent Laid-Open No. 59-24892.

However, this device applies a DC voltage to the liquid crystal material.

As is well known, liquid crystal materials undergo electrolysis due to direct current electric fields, which significantly shortens the life of the liquid crystal.

Therefore, the above-mentioned device has a practical problem in terms of service life.

[Purpose of the invention]

The purpose of this fan is to read data, refresh
It is possible to extend the life of an active matrix liquid crystal display device with

[Summary of the invention]

The present invention provides an active matrix type liquid crystal device having a data reading and refreshing device Df, which reads the voltage currently applied to the liquid crystal display pixel during the refresh operation, inverts and amplifies the voltage, and then applies it to the pixel again. It is characterized by alternating the voltage applied to the liquid crystal pixels.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. The novelty of the present invention lies in the refresh operation of the liquid crystal pixel (1), and the normal data writing (9) display operation is the same as that of a well-known scattering crystal display device, so a description thereof will be omitted. These are display pixels defined by this, and each display pixel 1 is arranged in a matrix to form a display section (not shown). Tosoyapashita 3 and each Yar
It is composed of liquid crystal elements 4 connected to V HASHITARO, each of which serves as a memory cell. IA of each row = lOS
Scanning to connect the gates of transistor 2 in common ~('y
y and the drains of the 1v10S transistors in each column are commonly connected, and +5 electrodes m are insulated and separated at the valley junction and arranged orthogonally.

Each signal 1u pole m (rL refresh circuit 51) is connected.

Refresh circuit 5 is a WJl with two-man power.

2nd Compan-Taro, 7 and 1st. Second dummy cell 8
, 9 and 1st. Second precharge voltage generation circuit 10.1
1 and a three-value conversion output circuit 12 which is controlled by the output of the comparator and generates a predetermined 'ζ pressure, and each signal stream 4''.
It consists of an MQS transistor that selectively controls the ``mechanism''.

A dummy line n11 is connected to one terminal of the first comparator 6, and a first dummy cell 8 including a MOS transistor 15 and a capacitor 14 is connected to this dummy line n1. A dummy line nb is similarly connected to the second comparator 7, and a second dummy cell 9 including a MOS transistor 15 and a capacitor 16 is connected to this dummy line nb.

The gates of the IVIOS transistors of the memory cells in each column are commonly connected to a control line. 10 is a half-1 precharge voltage generator for inputting 41 reference voltages into the first tummy cell 8; 11 is a second dummy cell 9;
t is a second precharge voltage generator for writing a second reference voltage.

The stray capacitance σAl of the dummy line n, , is set to be almost equal to the stray capacitance CA of the scanning signal line m.
Set it so that it is almost equal to .

The refresh operation works fine if the read information is newly inserted ^), but even if the capacitor 6 is charged at the 11" level, the voltage decreases over time due to leakage from the MOS transistor 2, etc. Therefore,
Even if the read voltage is lower than the initially written voltage, when writing a new voltage, the original voltage must be written or sufficient display or information storage operations will not be possible.1- Further, the liquid crystal element 4 has a drawback that its lifespan is shortened if an IN current electric field is continuously applied thereto. In the present invention, the voltage applied to the capacitor 3 during the refresh operation is divided into six types, ie, '1''.
, '0'' and '-1'' levels. As a result, by setting the common electrode of the liquid crystal element 4 at a certain potential, an alternating current electric field can be applied to the liquid crystal element 4 (the electric field applied to the liquid crystal element 4), and the life of the liquid crystal element 4 can be extended.

Next, the refresh operation of the embodiment shown in FIG. 1 will be explained with reference to the timing chart shown in FIG.

First, the first precharge voltage generator 10 charges the capacitor 14 of the first dummy cell 8 to an intermediate level a1//. Similarly, the second precharge voltage generator 11 charges the capacitor 1 of the second dummy cell 9.
6. Charge to level % -1// medium III potential.

At the first time tl of the refresh operation, control #a
becomes H level, the switching elements 17, 18, 19 are closed together with the control line C, which was previously at H level, and the scanning signal Jm and the dummy cells 71a v nb connected to the dummy cells 8 and 9 become one current. Target 1 continued, the above scanning No. 15 1-m and two dummies Ugly +1. ．． :11) becomes equipotential. At time t2, switching element 17.1
8 is open n1 scanning signal line m and two terminals h na T
nb is electrically disconnected. Furthermore, at time t3J, scan electrodes 61 and b connected to the gates of transistors 2 and 13.15 in display pixel 1 and switching elements 13.15 in dummy cells 8.9 go to H level, respectively, and MOS transistors 2. and switching element 1
3 and 15 are closed, and the potentials precharged in the capacitors 14 and 16 are connected to the dummy lines n and nb+floating capacitance MC'AI and the cavantor 14. Stray capacitance C'A2
The voltage is divided by the capacitor 16 and the capacitor 16. Similarly, regarding the scanning signal line m, the potential charged in the capacitance jitter 3 is divided by the capacitance jitter 3 and the stray capacitance CA.

Next, depending on the value of the voltage appearing on the scanning signal line m, $
1. The outputs of the second comparators 6 and 7 are divided into the following three cases. This is shown in Figure 3.

That is, in the first case, the logic level 5 is at the logic level '1''.
If the scanning signal line m is charged to a potential of , the input 4S number sh in the second comparator 7,
The magnitude relationship of the voltage at t is h≦i, and the output j is at L level. Similarly, in the second case, if the canister 3 is at a potential of logic level 10'', the output gtlL of the first converter 6 and the output J of the converter 7 of g2 become L. 6, if the ivy 5 is at the potential of logic level 1-1'', the output g of the first comparator 6 is at L level and the output j of the second comparator 7 is at H level.

Next, a ternary conversion output circuit 12ij inputting the output of the converter Jl, name 2, has a logic level of 1-1'' in the first case, and a logic level 10 in the second case. In the sixth case (in this case, logic level 11) is a circuit that uses W power.The output of this three-value conversion output circuit 12 is shown in the timing chart of FIG. Since the element 19 opens and the switching element 20 closes, it is electrically connected to the scanning signal electrode m.Therefore, until time t6 when the MOS transistor 2 is closed, the capacitor 3 is connected to the 5-value conversion output circuit 12. A charging operation is performed with the output potential of , and rewriting, that is, a refresh operation is performed.

One refresh operation has been completed in the above manner, but in the next ↑ cycle, the refresh operation is performed for the pixel selected by the scan electrode 12. In this way, pixels are selected one after another and a refresh operation is performed.

When one refresh operation described above is completed,
The potential charged in the capacitor 5 is at logic level ""0"
Except in the case of , the sign is reversed. Therefore, in this embodiment, since the electric field applied to the liquid crystal pixel is reversed during the refresh operation, it is possible to extend the life of the display pixel while maintaining the storage capacity within the display pixel.

〔Effect of the invention〕

Since the electric field applied to the liquid crystal pixels can be alternated by the refresh operation, this has the effect of extending the life of the device.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing one embodiment of Akira Hongen, Fig. 2 is a circuit diagram showing an embodiment of Akira Hongen.
FIG. 3 is a state diagram showing the input/output relationship of the six-value f conversion output circuit in FIG. 1. 5... Reflex circuit 6.7... Comparator 8.9... Dummy cell 10, 11... Precharge circuit 12... Three-value conversion output circuit 13, 15.17.1B, 19.20...・Switching element 5, 14.16...Capacitor CAI C'AI + (-'A2...Katsuo Ogawa, patent attorney representing floating capacitors - Fig. 1

Claims (1)

[Claims] 1) In a liquid crystal display device in which memory cells each consisting of a liquid crystal element and a transistor/capacitor array are arranged in a matrix in correspondence with pixels, each column of the transistor/capacitor array has a first memory cell consisting of a transistor and a capacitor; a second dummy cell and a first dummy cell that compares the amount of charge of the capacitor in each dummy cell with the capacitor of the selected row in the transistor/capacitor array;
, a second comparator, a three-value conversion output circuit that outputs one of three potentials according to the output values of the first and second comparators, and an output voltage of the three-value conversion output circuit. 1. A liquid crystal display device comprising: rewriting means for applying voltage to a capacitor in a selected row in the transistor/capacitor array, and having a memory display function capable of inverting and refreshing.