JPS6150282A - Semiconductor memory device of charge accumulation type - Google Patents

Abstract

PURPOSE:To obtain a highly-sensitive read mechanism suitable to super integrated semiconductor memory by providing a charge supply mechanism in such a way that it is connected to a data line. CONSTITUTION:A word line 51 and dummy word line 52 are selected, and a signal charge and reference charge are supplied to data lines 11 and 12 from a memory cell capacity 14 and a dummy cell capacity 17. A precharge pulse phiP is impressed from a time t1 to t3, and simultaneously a transfer gate pulse phiT is impressed from the time t1 to t2. Then a data line potential VH-VT (VT: gate threshold values of transfer gates 24 and 25; VH: high level of charge transfer transistors 24 and 25) is set to VH-VT. A pulse phiS during the standby period is impressed and a voltage across a gate and source of the charge transfer transistors 24 and 25 are generously set. Afterward, the transfer gate pulse phiT is impressed again, and the signal charge is transferred. The a phiSA is impressed to operate an information deciding mechanism composed of transistors 28 and 29, and a signal voltage is amplified.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] Kiyo 1jlJ wrote a large number of cells M, using the '6moe carrier in the half body as an information source, and the information stored in these cells. The so-called R has a mechanism for reading 1j'r information according to specified address information and writing information to cells.
AM (Random Access Memory)
In particular, ultra-high integration 1 having an extremely sensitive readout mechanism also relates to AM.

[Background of the invention]

As a RAM whose information source is the chest of drawers carrier in the cow conductor,
The well-known configuration of a memory cell with one transistor and one capacitor Jj! A conventional structure of a so-called one-transistor type dynamic RAM (ITr-dRAM) is shown in FIG.

In Fig. 1, 11 is the capacity for storing the signal range carrier which is the information source, and 2 is the capacity of the MUS which is the word gate.
Word to open/close switch 2 by specifying address in 3i1X direction, 4.
5 is a data line for @transmission of the chest of drawers carrier, 6 is an address decoder that specifies addresses in the X direction, and a word driver that moves the word line 3 (hereinafter abbreviated as the X decoder); 7 is a data line. Address decoder 2 in the Y direction and input/output section (hereinafter referred to as Y decoder)
110), 8 is a sense amplifier, 9 (inside the broken line) is a tummy lunch for comparing the difference grooves, and 10 is a dummy card gate MOST. One terminal of Nakatani Ml, 9 is indicated by a circle, for example, this is the highest DC pen pressure V of the system. This shows that it is connected to 0.

In such a conventional dRAM, a specific numerical example is 4 pF, 5 orp (r: femto 10-15), and a chest carrier stored in an amount of 1, and a data green 4 of about 2 pF. Turn it up and detect this voltage change. Therefore, when the signal voltage stored in each ff1l of the memory cell is detected, the signal voltage of the system is approximately 100mV (for example, in the above example, it is approximately 100mV). For this reason, a simple detection method requires an amplifier due to accuracy issues, so if, as shown in Figure 1, ) stored in dummy capacitor 9 (within the dashed line)'
The charge carriers are taken out to the data acid 5, and the information stored in the valley it1 is determined by the differential sense amplifier 8.

In the conventional D-type A to 11, a differential sense amplifier (as an amplifier, due to the ffr+simplicity of its configuration, a flip
Flop type sense amplifiers are being used all at once, Fl, I (5fpin K, U, 1972 1SS
CCdigest of technical
papers p56-57).

However, one sense amplifier is required for each pair of data amplifiers, and in order to realize a high-performance amplifier, one high-performance, complicated circuit is required.
11. Because there is no reason to use something that requires force,
With the above method, C also has the signal nj on the data gauze.
As for the pressure, lOOmV6i is considered to be the limit including a practical margin. Therefore, the ratio Cs/C9 of storage cell storage cell valley 1rCs and data line valley 11i:CD is approximately 1/
40 or more, and it is difficult to reduce the storage capacity C8 by an order of magnitude compared to the above example.
The high integration of RAM has become a serious obstacle.

In particular, when high integration is achieved by setting the amount of accumulated charge to three or more values, such as in a multi-value storage device (described in % Patent Application No. 58-120364, Japanese Patent Application No. 58-242021), ,
Since the signal voltage on the data center is a reciprocal multiple of the number of multilevel levels, it is difficult to realize this without a sophisticated readout mechanism.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide an extremely sensitive k-extrusion mechanism suitable for ultra-highly integrated semi-conductor memories.

[Summary of the invention]

In order to achieve the above object, in the present invention, as an information reading mechanism, charges 1, 1, 1, 1, 1, -/, f-1, are connected to the data line. 00 and are set up sequentially,
The structure also includes a charge supply mechanism connected to the data line. As a result, the output signal charge output on the data line can be transferred to the input terminal in front of the information judgment device without loss, so that the output signal charge on the data line can be transferred to the input terminal in front of the information judgment device with almost no loss. It is possible to output the output signal '1 of ~1/20 of the working pressure with the same accuracy and at high speed.

[Embodiments of the Invention] The present invention will be described in detail below. In the following examples, electrons are used as charge carriers that carry information, and electron transfer gates are used as charge transfer gates. We will explain the case where an N-channel transistor that performs It can be applied in exactly the same way by appropriately selecting the source, the polarity of the pulse, and the amount of charge supplied from the 41! type and '1 (L charge supply mechanism) of the half body.

(Example 1) Fig. 2 shows an example of a charge accumulation type conductor memory (hereinafter abbreviated as DRAM) according to the present invention.For convenience,
A P-channel MOS transistor is shown with an arrow to distinguish it from an N-channel MOS transistor. In addition,
Description of the writing mechanism and addressing mechanism will be omitted. In addition, one data line pair in the memory cell array in the figure is shown focusing on one pair. In FIG. 2, 40 is a memory cell array carrying charges carrying information; 41 is the other data line that is paired with the data line connected to the selected memory cell when reading information from the memory cell array; This is a tummy cell that supplies the acid with a charge for sericulture. Further, 42 indicates a charge supply mechanism, which is the gist of the present invention, 43 indicates a reset gate, 44 indicates a charge transfer mechanism, 45 indicates a precharge gate, and 46 indicates an information determination mechanism. The operation of this memory device will be explained in detail below.

One memory cell and one dummy cell are selected by a word line and a dummy word line arranged orthogonally to the data line pair 11 and 12. In this example, word i51 and dummy word line 52 are selected, and signal charge and charge are supplied to memory cell capacitor 14, dummy cell capacitor 17, and color data line 11.12, respectively.The presence or absence of signal charge is determined. In order to do this, the value of the signal charge is selected to be approximately 1/2 of the signal charge amount.For this purpose, the value of the dummy cell [17] is already approximately 1/2 of the memory cell capacity 14.
tCharge supply mechanism Consists of two capacitors 20 and 21 and a control line 55.The voltage amplitude applied to the control line is Δv5,
Each fL is 05. Then, a charge of Δv5×C is supplied to the data line. The charge filling mechanism is composed of M (JS transistors 24 and 25). For information judgment, a (G, flip-flop, and P type sense amplifier is used. In other words, two MOS transistors are used.
It consists of transistors 28 and 29, one gate and the other drain being hi hT. Figure 3]
Driving waveforms (a) to (f) during readout of this circuit
6, the data line M (g), and the operation waveforms of the load transfer section output terminal (h) are shown. Prior to reading, reset pulse φ
□ resets the dummy cell S*fa and the data line portion to the ground potential. At the same time, between 0tl and t2, a precharge pulse φ is applied from time t1 to [, and the condition is set to a low level where starvation can be performed.
i-<transmission gate pulse φ, is applied, and the data LT,
The potential is set to V□-V, (Va is the gate threshold voltage of the transfer gate 24.25, vH is the high level of pulse φ7!i). With this setting, the charge transfer gate 24I25 waits in a subthreshold region, that is, a region in which there is an exponential relationship between the gate-source voltage and the channel current. In order to accelerate the transfer of signal charges, the channel'? ! It is necessary to choose a large value for l flow. For this purpose, a pulse φ5 is applied during the standby period to cause charges (electrons in this case) to flow from the power supply mechanism to the data line, and to reduce the voltage between the gates and sources of the charge transfer transistors 24 and 25 (time ( 5 to t6) At the same time, the signal charge is extracted during this period (time t4)
~L5). After that, transfer gate pulses ψ and r are applied at Pr degrees, and the charge is transferred (signal) (times t6 to 17),
Thereafter, φ3A is applied to operate the information determination mechanism (time 18-1), and the minute signal voltage is amplified to a voltage level that can be handled by the digital cooking circuit. Signal charge transfer T?
In order to accelerate s, we can consider shortening the φ1 pulse width during precharging and transfer to increase the operating current, but the pulse width may change due to fluctuations in the power supply voltage, etc. In this case, setting 11 will vary greatly, so you can't expect a simple M work. In addition, as described later, multiple 11r [like a memory sense circuit, a several times information @
In the case of performing nail cutting, the signal charge transfer acceleration method described in the present invention is effective. This is because it only needs to be done once, which saves wasted time and wasted acid power caused by charging and discharging the data line multiple times.In this way, in order to accelerate the transfer of signal charges, It is effective to supply a certain amount of electric charge.For convenience, this electric charge will hereinafter be referred to as a carrier charge.

As the means for supplying carrier charges to the data lines, the one shown in FIG. 4 can be applied. In the figure, the data line pair 551 is the drive signal line of the carrier collision supply mechanism. (The one shown in aJ is the same as that used in FIG. 2. This is an example in which 1 (20, 21) are each configured with 5 ift MOS transistors, and here,
Depletion type MOS transistors 60 and 61 are used. (C) has the same configuration as the dummy cell'
It is an α charge supplying means, and consists of capacitors (64, 65), charge transfer transistors (62, 63), and reset transistors (66, 67) of approximately J°C for each ffl'. In (a) and (b), a signal voltage that transitions to a lower voltage is applied to the drive signal line, and in the case of (C), it is transferred to Apply signal voltage.1t1: Positive amplitude value Δ■3, valley IL
If the value of t is 08R, then the carrier 1 and the carrier λS supplied to the valley data line are approximately ΔV,×08. becomes. (
In the method C), the 'C+ tile for supplying carrier charge is not read as data, and the key point is that the signal voltage of the data line is increased.

Further, the carrier dL charge supplying means is connected to the dummy cell (reference charge supplying cell) with a skewer extending north. It is also possible to reduce the number of drive signal lines. What is shown in FIG. 5 is another one. (a) shows the two driving fjTJIM lines φB and φD.
W'2 (70, 71)b and four capacitors (72, 73, 74) connected between each and the two data lines.
, 75).

When a memory cell connected to the data line 11 is selected, the drive signal is 70i, and when a memory cell connected to the data line 121 is selected, the main signal is 71i.
C1 has an equal capacitance of 172.75 of n0 value applied to
The value of valley angle 73, 74 is 02, drive signal.

If the amplitude of the signal is Δ■DW, then the reference α Samurai π(((C2
-01)×ΔV91. becomes. (C2-C,)XΔVo
w's f straight (; The signal from the moss-filled valley of the memory cell to the data line should be approximately 1/2 of the signal I load. This example uses the same concept as the example shown in C), that is, shows a method to realize it without increasing the data. (82, 83) Four transfer transistors connected to E and 80, 81, four reset transistors connected to No. 2.83, and a carrier voltage:
ji+Set the amount of charge on the capacitor.・One capacitance is equal to one. The l principle (same as the case of sai (a)),
A drive signal is applied to 80 when the number of data lines connected to the selected memory cell is 11, and to 81 when it is 12. The reference charge amount is C1,8 for the capacitance 1 of 84 and 87.
Assuming that the capacitance value of 5,86 is C2 (C2>CI) and the BA drive signal amplitude is Δ■o, approximately (C2-C1) x ΔVD
It becomes W.

As shown in Example 1, when the charge transfer mechanism is constructed using one MOS transistor for one data line, signal charges can be efficiently transferred by providing carrier charge supply means for each data line. Transfers well.

(Example 2) Next, another example of the present invention is shown in FIG. here,
An example will be shown in which a charge transfer mechanism including one drive gate and two transfer gates is used for one data line.

In the figure, 40 is a memory cell array, 106 is a carrier charge and reference charge supply image structure, 43 is a reset gate, 45 is a precharge gate, 46
indicate the information determination mechanism. The charge transfer mechanism includes four drive gates 102 and 103 made up of depletion type MOS 1" ET, and a transfer gate 10.
It consists of 0,101,104°105. The charge supply mechanism is the same as that shown in FIG. 5(a). Further, the configuration of the other 1 Sb except for the charge transfer device TI'7 is the same as that of the first embodiment.

In this example, to illustrate the effect of the charge supply mechanism on signal charge transfer, Figure M7 is shown below.

The operation will be explained using drive and operation waveforms.

FIGS. 7(a) to (h) show the drive pulse waveforms of each signal line,
FIG. 7(i) and ('') show operating waveforms of the data line and the output end of the charge transfer mechanism. Reset pulse φ at period ◎
R is applied and the data line is set to the ground potential ■as. After that, in period ■, two transfer gates T.

A gate Nihalus φT31φ of (100, 101) and T, (104, 105) is applied, and a precharge pulse φ is similarly applied to precharge the data line. What is important at this time is to set the gate F potential barrier of T3 higher than that under the T1 gate, control the threshold voltage of the transfer gate, or control the pulse height (Tlffi dynamic pulse height). ``rs>T3 drive pulse height vT3).In this example, this is achieved by setting a difference of approximately 0.2 to 0.3v between the pulse heights of ``r3 and T1.'' Now, in that case, the precharge voltage 110 of the data line is approximately V, -V□.8.
The voltage is set to approximately Here, ■TH(T3) is the threshold voltage of the transfer gate 1-T3. FIG. 8(b) shows the potentials of the data line, charge transfer gate, and charge transfer gate output terminal valley at this time. Data line potential 127 is T3 gate bottom potential 12
The charge is increased until it becomes equal to 8, and in this case, an outflow of the current (current) occurs. Similarly, Figure 8 (C) shows the waiting period ■ (see Figure 7)
shows the potential diagram for . From this state,
During the period ■, a high voltage is applied to the word gland, and the data written in the memory cell is
A signal is applied to the data line in response to 0"=low abrasive pressure) ("1"--no change, "02--potential drop due to electron outflow).

Figure 7 shows the data line waveform when the signal °0'' is read out (V(11)o. Note that no mini drop occurs because no signal is applied to the reference data line. No (v(12)).Furthermore, in period ■, the charge supply mechanism operates in synchronization with the input of the drive signal φ'9w2,
The reference charge S and the carrier 1 load are output to the data forest. Among the changes in the data line potential seen in the 7th iV(i), the data line 11 is connected to the selected memory cell.
1st place (11) K conversion Δ■ 1 is carrier '4', contribution of only load, on the other hand, change in potential V (12) of data line 12 Δ■ 2 is 1,000 years') Refer to Ami Moe This is the contribution of the power supply +i door・'su (dummy charge). Therefore, in period ■, 2
The data line 4 pressure difference (V(12)-V(11)l) is approximately 1/2 of the signal amplitude.As shown in FIG. The potential of the data storage is rising due to the contribution of carrier charges, carrier charges, and dummy charges (129).
From period (2) to period (2), a pulse is applied to the transfer gate T2, the transfer gate 'L'3, and T1. ≠ In order to accelerate the -UC charge transfer to the bottom of the J gate (16 m from the data gate), a bias charge Qn is injected from the drive gate to the data line (Fig. 8(e)). .

In the case of bias charge, for example, data capacitance: l
At pF, it is about 100 to 200 fc (femto coulombs). As mentioned in the previous example, the purpose of this is to increase the flow to the channel of the transfer gate T3 during transfer and accelerate the transfer of signal charges. With the above bias and load, the channel sleep vL is 1 to 2.
This increases by an order of magnitude, and the signal transfer time also decreases by one to two orders of magnitude. Further, in the period (3), the transfer gate T1 is made to pass four times, and the charge transfer 131 from the steady gate T2 to the output terminal of the charge transfer device 17 is simultaneously carried out. The transfer ys130 under T3 is accelerated by the effects of biases 1B and mQB, but the transfer 131 under °1゛1 has a large effect of the carrier ``load''.

In other words, QB is the one between the drive gate T2 and the data line.
In order to efficiently perform the transfer under 'r1, it is necessary to supply other charges, and this role is played by the carrier 'I! This means that tA is in debt. In this way, after the load is transferred, the signal output generated by the load is amplified by the sense amplifier.
By using a method of overlapping the pulses of 3 and T1, the feedback effect can be reduced, and this can be achieved by making the valley 1IiC of the drive gate smaller than the data valley 1IC0.

According to experimental analysis results, the efficiency of transferring signal charges to CD-)CB is determined by how many times the operating current increases depending on the amount of bias charge. For example, the tail coefficient αz 60 mV /
Decade height, QB/C, = 60 rnv
.

That is, when the operating current increases by one order of magnitude, about 10% of the charge is left behind, and when the operating current increases by 120 mV, that is, by two orders of magnitude, about 1% of the charge is left behind. Now, assume that the pulse amplitude applied to the drive gate is 5vPP. 1
In order to leave less than 俤, the ratio of CB and CD is C0/
The value of CD must be approximately 1/40 or more. However, when a flip 70 block type sense amplifier as described in this example is used as a sense amplifier, it is possible to tolerate up to about 10 inches of signal charge remaining, and the CB/C
D should be about 1/80 or more. Actually α
= 80 to 100 mV/decade (room temperature), so it is desirable that CB/CD be a little larger.

FIG. 9 shows the effect of carrier charge quantitatively for the first time. This indicates the ratio of the signal charge amount left behind under the drive gate to the carrier charge amount Q. Note that the signal charge amount is 6fc. As can be seen from this figure, by supplying the data line with a carrier charge equivalent to the amount of signal charge, the number of unidentified lines is greatly reduced, and it is possible to transfer the signal charge almost completely. . The size of the capacitance used for the carrier charge supply mechanism is 50 to 100.
fF, which is comparable to that of a memory cell, and the ratio of the charge supply mechanism to the entire memory can be about 0.1%.

Now, from the above two examples, we are proud to say that this semiconductor device is capable of efficiently detecting minute signals and loads. Next, this performance is expressed as ll′
An example of application to a semiconductor multilevel memory is shown below.

(Example 3) A semiconductor multilevel memory is a 1Tr-
It allows IC memory cells to store information of three or more values.
This is an extremely effective method for increasing memory integration. The inventors have already invented a method of applying step wave pressure (9) to word lines or plates (Japanese Patent Application No. 1203/1986).
64, patent application No. 58-242021). In this memory n
When storing a value, the amount of signal IJL phrases to be determined is 1/(n-,1) times that of DRAM. For example, n
= 16, the voltage on the data leg is 10
The voltage is approximately 20 mV, which is below the detection sensitivity of a sense amplifier commonly used in DRAMs, and stable operation cannot be expected. However, the book'zhT3A
If f is used, not only n=16 but also n=32 is possible. The operation will be described below with reference to FIGS. 10 and 11.

FIG. 10 shows one configuration example of a semiconductor multilevel memory. In the figure, 40 indicates a memory cell array 140, a carrier 4 load and a reference charge (kumi=1! load) supply mechanism, 43 is the reset gate 141 is the 7-loading equipment, 1
42 (ma'OL load transfer mechanism), 143 (ma'information determination mechanism, 45 (ba' precharge gate, 144 is a selector for outputting determination information by switching one of the data line pairs) Although only one data line pair is shown here, this data line pair is actually arranged directly adjacent to a plurality of word lines.

Now, if the signal a for selecting one of the data line pair becomes a high voltage (for example, V.0), the staircase wave generated by the voltage generating circuit 146 will become a staircase wave (well, four lines state). Through a transistor 147, a signal line 149 is connected to a high voltage. (for example, V). Then, the transistor 151 becomes conductive, and a staircase wave is output from 149 to the word edge 152. Therefore, a signal is output from the memory cell connected to that word edge to the data line. In the example shown,
η due to transistor 153 and VJ+t, 15/1
When the data X is generated, a signal charge is outputted from the memory cell formed by the three-dimensional circuit. For example, since the four-line width of the staircase wave is 200 mV and the memory cell capacity (or 50 fcf9 degrees), this signal charge amount is about 10 fc.On the other hand, the staircase wave also applies to the reference charge and carrier charge supply mechanism 140. In this example, a staircase wave is applied to the gates of transistors 157 and 158, and (carrier charges) and (
Output 1 carrier + reference cage). The carrier load is also about the same as the signal load, that is, about 10 fc.The signal charge output on the data edge, the reference charge,
4 carriers are 4 carriers/transmitters'? From 14142+, it is transferred to its output terminals 155 and 156. The size of each carpet weight (the hook body is determined by the information judgment method j1"q. That is, (1) the signal bearing amount (reference ton) When Moe≦, 155 is the high level (for example, power supply t3i voltage V...),
156 becomes a low potential (for example, ground potential V8.
Contrary to (1), 155 is low, 156 is high,
It becomes difficult to make judgments. As long as the voltage applied to the memory cell (word line ′-: voltage) is wide by 1, the Im-go chest of drawers does not output and is in the state of (1), but the voltage becomes constant and (
When the word line area pressure)>(memory cell seedling pressure)+(memory cell transistor (T53) gate line pressure) is reached, a signal t is output to the screen data line. , the state of (11) is reached, the Kanai transfer machine, 4 output terminals 155
, 156 is reversed. in this way,
Is it possible to read out the information (damage level) stored in the memory cell at the timing when the magnitude relationship of the potential at the output terminal of the load transfer mechanism is reversed? It is 5J north.

FIG. 11J is a timing diagram for setting the operation in more detail.

between 1 and 2: Apply lyse, dopa, and set the data line to 53 (161°16
In 2), set the potential to 1 and sovsa.

Period ■: At the same time as applying the precharge pulse φ,
T31φ7□ is applied, the charge transfer gate T3T1 is made conductive, and the data line is precharged.

At this time, in order to realize a potential state as shown in FIG. 8(b), a difference is created in the threshold voltages of the T3 and T1 transistors, or a difference is created in the peak value of φ7. Then, the potential of the data line is (peak value of φ, 3)
- (threshold voltage of T3).

During period 01, the staircase wave φx is applied to the word line, and at the same time carrier charge and reference i! Outputs the load to the data line. In this example, since the word line potential does not exceed the accumulation peak of the capacitor 154, the voltage + (threshold voltage of the transistor 153), the signal charge should be output to the data line. Therefore, the potential V (11) of the data line 11 is the potential V (11) of the data line 12.
This value is larger than (12).

Period (2): φr3 and φT2 are applied, and a bias 11L load is injected from the drive gate to the data line to connect 11 'B1: 荀-.1-bar combinations.

Period 0~■:φ72';e 1tlj+'LIJ:
The voltage (for example, VC6) is returned by 1, and φT1 is applied to transfer the a load. During this period, signal charges, carriers (liquid charges, almost all diagnostic charges) are transferred to the first and Y output terminals 155 and 156 of the load transfer device.The voltage difference V(1
55)-V(156) is the data pressure difference v(11
1) -V(112) is amplified by α times (capacitance of the output end of the charge transport mechanism). The value of α is about 10 to 20 for -breakage.

The voltage difference between 155 and 156 during the period is further cooled by an NMOS flip-flop amplifier (consisting of 28 and 29).

Period ■: φ. is applied, transistor 167°168%
247 PM OS flip-flop amplifier 1
Therefore, the high voltage level is clamped to a high voltage fXf, (f!AJ is 1M, rM voltage ■Cc).

Period ■; Apply precharge pulse φ, 1 ”
゛・"°21ゝ(ilJ, if"...9゛") to prepare for the next readout.

In the semi-dedicated multi-direction memory, this cycle is repeated k(n-1) times (Ω: the number of multilevel levels to be stored), and the timing at which a signal flows out from the memory cell to the data line is detected. In this example, in the second read, the signal T (1) flows out to the data line, and the potential of data IvJ!11 changes to data line 1.
2, and as a result, if the magnitude relationship of the potential at the output terminal of the charge transfer mechanism is first (V(155)>V(156)
) is inverted (V(155) <V(156)).

As shown in this example, when particularly minute signal charges need to be read out, such as in the escape mechanism of a semiconductor multilevel memory, a means for transferring signal charges without loss is essential. The charge supply mechanism according to the present invention occupies a small area of the memory array, and is very effective in improving transfer efficiency.

FIG. 2I shows another implementation of the charge supply devices 11 used in FIG. In this example (for example, to drive the carrier charge supply mechanism, the same staircase wave φ applied to the word line is applied to the illumination charge supply mechanism), or another staircase wave generation mechanism 188 generates an amplitude A different staircase wave φx/ is applied.It is desirable that the reference voltage Mf1t is 1/2 of the signal charge amount output from the memory cell.One way to achieve this is to use a drive pulse. This is a method of keeping the amplitude of the (Katsu wave) the same and reducing the hm for supplying the illumination charge to 1/2 of the memory cell capacity.However, as the capacity of the memory increases, the memory cell area becomes smaller. However, it is not easy to form a capacity that is exactly 1/2, and in the case of memory cells that have a three-dimensional structure, it takes a lot of trial and error.
You have to make decisions based on errors, which is a hassle. In this example, in order to avoid this, the capacitance value for supplying the reference charge is made to match that of the memory cell capacitance, while the amplitude of the staircase wave is made different (specifically, the step is set to 1α of φ8). This is achieved by reducing the pressure to 1/2 of the pressure step.

[Effect of 1-minute delivery] As explained above, in the present invention, this highly sensitive readout mechanism, which is a particularly important element in a large-capacity memory device,
A charge transfer mechanism provided on each data line, a 46tI supply mechanism that supplies Ia to the data line prior to reading, and a charge transfer mechanism located at the 'Lli load transfer &ff'j output end to transfer the charge to the output end. This invention was realized by a device for determining the size of a quantity (11).The present invention has a small circuit scale and improves the sensitivity by more than one order of magnitude, and is suitable for use with super This makes it possible to easily realize a memory with a high concentration of ATI.

+7i)ir"L Explanation of the Drawings Figure 1 is a circuit diagram of a conventional ITr-d A.M.
FIG. 3 and FIG.
A circuit diagram and an operation timing diagram showing one embodiment of a readout mechanism with 10 pcs. Transfer search (,
Figure 8 is a circuit diagram and potential diagram showing the operating principle of the charge transfer mechanism, and Figure 9 is the relationship between charge transfer efficiency and carrier charge amount. 10 and 111 are a circuit diagram and an operation timing diagram showing another embodiment in which the present invention is applied as a reading mechanism of a semiconductor multilevel memory, and FIG. FIG. 7 is a configuration diagram showing another embodiment of the configuration of war+1.

Explanation of symbols 40...ITr-IC memory cell array 41...Dummy cell, 42...'load supply machine inlet, 43...Reset gate, 44...Charge transfer mechanism, 45... Precharge gate, 46... Judgment mechanism, 140... Charge supply mechanism, 141... 4 of Jōshun! f-loading mechanism, 142... Charge transfer mechanism, 143... Determination mechanism for alarm, 145... Row selection circuit (row decoder), 144...
Selector, 146...Staircase wave generation circuit Fig. 1 Fig. 2 Fig. 3 ) (b)V
σ 71 σri σl gut sykuzu6I21 Name 7 Figure No. 3 笥 '7121 1 Maria Amount of haiku 0 [ChiC]

Claims (1)

[Claims] 1. An array consisting of a plurality of cells storing charge carriers in a semiconductor as an information source, an addressing mechanism for specifying the position of each cell, and a memory cell specified by the addressing mechanism. The reading device comprises at least a voltage applying means for applying a read voltage, a data line connected to the cell to transmit charge carriers serving as an information source, and an information writing mechanism and a reading mechanism connected to the data line, respectively, and As a mechanism, an information determination mechanism, a charge transfer mechanism provided between the determination mechanism and the data line, and a charge supply mechanism provided connected to the data line and operated at the time of reading;
A charge storage type semiconductor memory device comprising at least a reset gate connected to a data line and a precharge gate connected to a connection end of a charge transfer mechanism output terminal and an information determination mechanism. 2. In the semiconductor memory device according to claim 1, one piece of information is provided for a pair of data lines, a pair of charge transfer mechanisms, a pair of charge supply mechanisms, a pair of reset gates, and a pair of precharge gates. The information determining mechanism has two input terminals, each of which is connected to the charge transfer mechanism, and the addressing mechanism for specifying the location of the memory cell includes a pair of data lines. A charge accumulation type semiconductor memory device characterized in that two or more memory cells among a plurality of memory cells connected to the memory cell are not specified at the same time. 3. A charge storage type semiconductor memory device according to claim 1, wherein the charge transfer mechanism is constituted by a charge transfer gate made of at least one MISFET. 4. In the semiconductor memory device according to claim 1, the charge transfer mechanism includes a capacitor constituting a bias charge supply mechanism and a MISFET provided between the bias charge supply mechanism and the data line. 1. A charge storage type semiconductor memory device comprising at least one charge transfer gate and a second charge transfer gate formed of a MISFET provided between the bias charge supply mechanism and the information determination mechanism. 5. In the semiconductor memory device according to claim 4, the capacitor constituting the bias charge supply mechanism is MISFE.
A charge storage type semiconductor memory device, characterized in that it is formed of T. 6. A charge accumulation type semiconductor memory device according to claim 4, wherein a capacitor constituting the bias charge supply mechanism is formed by a depletion type MISFET. 7. In the semiconductor memory device according to claim 2, in one read operation, one of the binary information is output from the memory cell specified by the addressing mechanism to the data line in accordance with the binary information. Binary signal charge amount Q_s
_0, Q_s_1 Amount of charge Q_ that is output to the first data line from the first charge supply mechanism connected to the first data line
1. Between each of the charge amounts Q_2 outputted to the second data line from the second charge supply mechanism connected to the second data line paired with the first data line |Q_s_0−Q_s_1|> A charge storage type semiconductor memory device characterized by having the following relationship: Q_1-Q_2| 8. In the semiconductor memory device according to claim 2, the first charge supply mechanism is formed by first and second charge supply means connected to the first data line, and the second charge supply mechanism is formed by third and fourth charge supply means connected to the second data line, and when a memory cell connected to the first data line is specified by the addressing mechanism during reading, the first and fourth charge supply means are connected to the second data line. A charge accumulation type characterized in that when the third charge supply means and a memory cell connected to the second data line are specified, the second and fourth charge supply means operate respectively. Semiconductor storage device. 9. In the semiconductor memory device according to claim 8, each of the first, second, third, and fourth charge supply means includes one charge transfer gate and one capacitor connected to one end of the charge transfer gate. The first and third charge transfer gate electrodes, the second and fourth charge transfer gate electrodes, and one reset gate connected to their connection ends and provided so as to set the connection ends to a predetermined potential. What is claimed is: 1. A charge storage type semiconductor memory device characterized in that these are formed in common. 10. In the semiconductor memory device according to claim 8, each of the first, second, third, and fourth charge supply means each comprises one capacitor whose one end is connected to the data line. A charge storage type semiconductor memory device characterized by: 11. In the semiconductor memory device according to claim 8, the first charge supply mechanism includes a first reference charge supply means connected to the first data line and a first charge supply means; The second charge supply mechanism includes a second reference charge supply means connected to the second data line and a second charge supply means, and during reading, the first and second charge supply means receive approximately equal amounts of power. when the memory cell connected to the first data line is addressed by the addressing mechanism, the second reference charge supply means supplies the second reference charge charge to the first and second data lines, respectively; 1. A charge accumulation type semiconductor memory device, wherein a first reference charge supply means operates when a memory cell connected to a data line is specified. 12. The semiconductor memory device according to claim 2, wherein a pair of data lines are arranged close to each other in parallel, and a pair of data line charge supply mechanisms, a pair of charge transfer mechanisms, and an information determination mechanism are provided. A charge storage type semiconductor memory device characterized by being arranged in this order. 13. In the semiconductor memory device according to claim 1, information of at least two or more n values is stored and accumulated in the memory cell as a corresponding amount of charge, and when reading the information, an addressing mechanism is used. A voltage of n value generated by the read voltage application means is applied in time series to the memory cell designated by A charge storage type semiconductor memory device characterized in that each gate is activated n times. 14. In the semiconductor memory device according to claim 2, information of at least two or more n values is stored and accumulated in the memory cell as a corresponding amount of charge, and when reading the information, an addressing mechanism is used. A voltage of n value generated by the read voltage applying means is applied in time series to the memory cell designated by A charge storage type semiconductor memory device characterized in that a supply mechanism and a pair of precharge gates are each activated n times. 15. A charge accumulation type semiconductor memory device according to claim 14, characterized in that a flip-flop type sense amplifier is used as the information determination mechanism.