JPS6210007B2 - - Google Patents

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Publication number
JPS6210007B2
JPS6210007B2 JP53112076A JP11207678A JPS6210007B2 JP S6210007 B2 JPS6210007 B2 JP S6210007B2 JP 53112076 A JP53112076 A JP 53112076A JP 11207678 A JP11207678 A JP 11207678A JP S6210007 B2 JPS6210007 B2 JP S6210007B2
Authority
JP
Japan
Prior art keywords
film
openings
photosensitive resin
emulsion type
impurities
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53112076A
Other languages
Japanese (ja)
Other versions
JPS5538085A (en
Inventor
Manzo Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP11207678A priority Critical patent/JPS5538085A/en
Publication of JPS5538085A publication Critical patent/JPS5538085A/en
Publication of JPS6210007B2 publication Critical patent/JPS6210007B2/ja
Granted legal-status Critical Current

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Description

【発明の詳細な説明】 本発明は半導体装置の製造方法に関する。[Detailed description of the invention] The present invention relates to a method for manufacturing a semiconductor device.

集積回路製造過程に於て絶縁膜に同時開孔され
た複数個の開孔中特定の開孔にのみ不純物を導入
させる工程が必要な場合があり、この際には不純
物を導入しない開孔は感光性樹脂で遮蔽される。
しかしながら不純物を導入させる開孔と導入させ
ない開孔との距離が隣接していると、すなわち素
子が微細化されるにつれ該両開孔間距離は接近
し、該開孔間距離が目合わせ誤差距離程度に接近
すると、前記感光性樹脂で該両開孔を再現性よく
分離する事は困難となる。これは距離が狭くなる
から開孔による凹凸の段差の影響が顕著にあらわ
れるからである。
In the integrated circuit manufacturing process, it may be necessary to introduce impurities only into specific holes among multiple holes simultaneously drilled in the insulating film. Shielded with photosensitive resin.
However, if the distance between the aperture that introduces impurities and the aperture that does not introduce impurities are adjacent to each other, that is, as the element becomes finer, the distance between the two apertures becomes closer, and the distance between the apertures becomes the alignment error distance. If the two apertures are close to each other, it becomes difficult to separate the two apertures with good reproducibility using the photosensitive resin. This is because as the distance becomes narrower, the effect of the difference in unevenness due to the opening becomes noticeable.

第1図は従来技術を説明するもので、第一の導
電型を有する半導体基体1上に第1の絶縁膜2た
とえば二酸化シリコンを成長し、該絶縁膜に複数
個の開孔を開ける。開孔3には不純物を導入する
必要はなく、開孔4にのみ不純物を導入する必要
がある時、開孔3は感光性樹脂5で遮蔽され、次
にイオン注入法などにより不純物が基体中に導入
される。この時、開孔4には不純物が導入される
が、感光性樹脂5が保護膜となり、開孔3には不
純物は導入されない。この方法では感光性樹脂端
6を開孔3と4との間に位置せしめる必要があ
り、素子が微細化し、開孔3,4間距離lが短か
くなるにつれ、該樹脂端6を該開孔間距離l内に
再現性よく収めるのが困難となる。
FIG. 1 explains a conventional technique in which a first insulating film 2, for example silicon dioxide, is grown on a semiconductor substrate 1 having a first conductivity type, and a plurality of openings are formed in the insulating film. When it is not necessary to introduce an impurity into the opening 3 and only into the opening 4, the opening 3 is shielded with a photosensitive resin 5, and then the impurity is introduced into the substrate by ion implantation or the like. will be introduced in At this time, impurities are introduced into the openings 4, but the photosensitive resin 5 serves as a protective film, and no impurities are introduced into the openings 3. In this method, it is necessary to position the photosensitive resin end 6 between the openings 3 and 4, and as the device becomes finer and the distance l between the openings 3 and 4 becomes shorter, the resin end 6 must be positioned between the openings 3 and 4. It becomes difficult to keep the distance within the hole distance l with good reproducibility.

本発明は、かかる従来技術の見合せ精度によら
ず、自己整合で所望の開孔にのみ保護膜を形成す
る事を目的とする。
An object of the present invention is to form a protective film only in desired openings by self-alignment, regardless of the alignment accuracy of the prior art.

本発明は半導体基体上の絶縁膜に複数個の開孔
を有し、該開孔中の特定の開孔にのみ不純物を導
入し、他の開孔には不純物を導入しない半導体装
置の製造方法において、半導体基体表面に凹凸を
減少せしめる性質を有し、感光性樹脂とは異なる
材質の第1の膜を形成し、該膜の前記凸部に形成
された部分を除去した後に、第2の膜を形成し、
該感光性樹脂よりなる第2の膜の前記主表面上の
任意の凹部を含む領域を選択的に開孔し、該第2
の膜を保護膜として前記任意の凹部の前記第1の
膜を除去し、次に該第2の膜を除去した後に、前
記第1の膜を用いて不純物を半導体基体中に導入
する構成を有する。このような本発明を用いれ
ば、感光性樹脂の位置合わせ精度によらず自己整
合で所望の開孔にのみ保護膜を形成出来、かつ保
護膜を形成しない開孔部にのみ不純物を導入出来
る効果を有する。
The present invention provides a method for manufacturing a semiconductor device having a plurality of openings in an insulating film on a semiconductor substrate, introducing impurities only into specific openings among the openings, and not introducing impurities into other openings. In this step, a first film having a property of reducing unevenness on the surface of a semiconductor substrate and made of a material different from a photosensitive resin is formed, and after removing a portion of the film formed in the convex portion, a second film is formed. form a film,
A region including any recesses on the main surface of the second film made of the photosensitive resin is selectively opened;
The first film in the arbitrary concave portion is removed using the film as a protective film, and after the second film is removed, impurities are introduced into the semiconductor substrate using the first film. have By using the present invention, a protective film can be formed only in desired openings by self-alignment regardless of the alignment accuracy of the photosensitive resin, and impurities can be introduced only into openings where no protective film is formed. has.

第2図は本発明の第1の実施例の説明図であ
る。半導体基体21上に絶縁膜22たとえば二酸
化シリコン膜を形成し、該膜22に複数の開孔を
形成し、次にエマルジヨン型オキサイドを塗布
し、焼成する。このとき、回転塗布機の回転数が
4000回転の場合、エマルジヨン型オキサイド厚は
1000Å前後であり薄いので、必要に応じて回転数
を落とすか、2重塗布、3重塗布を行なえば所望
のオキサイド膜厚を得られる。このようにして形
成されたエマルジヨン型オキサイドの膜厚は、前
記絶縁膜22上は薄く、開孔23,24上は厚く
塗布される。したがつて膜22上の薄く形成され
たエマルジヨン型オキサイド除去後にも開孔2
3,24中にはエマルジヨン型オキサイド26,
27が残る。次に感光性樹脂25にて開孔23を
蔽うように選択開孔する。このとき、感光性樹脂
25は図のように開孔24上の一部を蔽つていて
もよい。次に該樹脂25を保護膜としてエマルジ
ヨン型オキサイド26を除去すると、開孔23中
に残余せるエマルジヨン型オキサイド27は樹脂
25を除去した後にも残る。次に不純物をイオン
注入法などを用いて導入すれば、開孔24には不
純物が導入されるが、開孔23は残余せるエマル
ジヨン型オキサイド27が保護膜となり、開孔2
3には不純物は導入されない。又、エマルジヨン
型オキサイドの下にシリコン窒化膜など異なつた
種類の第3の膜を形成しておき、エマルジヨン型
オキサイドをマスクとして他の異なつた膜を除去
し、該選択的に除去された第3の膜を保護膜とし
て不純物を導入してもよい。また、不純物導入の
方法としてイオン注入法のみならず、熱拡散など
他の方法を用いてもよい。
FIG. 2 is an explanatory diagram of the first embodiment of the present invention. An insulating film 22, such as a silicon dioxide film, is formed on the semiconductor substrate 21, a plurality of openings are formed in the film 22, and then an emulsion type oxide is applied and fired. At this time, the rotation speed of the rotary coating machine is
At 4000 rpm, the emulsion type oxide thickness is
Since it is thin, around 1000 Å, the desired oxide film thickness can be obtained by lowering the rotation speed or performing double or triple coating as necessary. The emulsion type oxide thus formed is thin on the insulating film 22 and thick on the openings 23 and 24. Therefore, even after removing the thinly formed emulsion type oxide on the membrane 22, the openings 2 remain.
3, 24 contains emulsion type oxide 26,
27 remain. Next, selective holes are made with photosensitive resin 25 so as to cover the holes 23. At this time, the photosensitive resin 25 may partially cover the opening 24 as shown in the figure. Next, when the emulsion type oxide 26 is removed using the resin 25 as a protective film, the emulsion type oxide 27 remaining in the opening 23 remains even after the resin 25 is removed. Next, if an impurity is introduced using an ion implantation method or the like, the impurity will be introduced into the opening 24, but the emulsion type oxide 27 remaining in the opening 23 will serve as a protective film, and the opening 23 will become a protective film.
No impurities are introduced into 3. Also, a third film of a different type, such as a silicon nitride film, is formed under the emulsion type oxide, and the other different type of film is removed using the emulsion type oxide as a mask, and the selectively removed third film is removed. Impurities may be introduced using the film as a protective film. Furthermore, as a method for introducing impurities, not only the ion implantation method but also other methods such as thermal diffusion may be used.

第3図は本発明の第2の実施例の説明図であ
る。第3図aに示された如く、第1の導電型を有
する半導体基体31上にゲート絶縁膜32及びゲ
ート電極33を形成した後エマルジヨン型オキサ
イド34を塗布し、該オキサイドの電極33上に
相当する部分を除去する。次に第3図bに示す如
く感光性樹脂35は少なくともエマルジヨン型オ
キサイド34Aは遮蔽するように形成した後、該
樹脂35を保護膜としてエマルジヨン型オキサイ
ド34Bを除去する。次に第3図cに示された如
く、オキサイド34Aを保護膜として、イオン注
入法等により基体の導電型とは異なる第2の導電
型を有する不純物を導入すると、エマルジヨン型
オキサイドのない開孔部分に不純物領域36が形
成される。次に第3図dに示された如くオキサイ
ド34Aを除去した後に第2の導電型を有する不
純物を熱拡散域いはイオン注入法で導入する。不
純物領域36の形成されていた部分には不純物領
域深さが深く、電気的抵抗が低い領域37が形成
され、領域36が形成されていなかつた部分には
電気抵抗は高いが不純物領域深さの浅い領域38
が形成される。次に第3図eに示す如く電極39
及び40を形成する。電極40をドレイン、電極
39をソースとすると、ソース、ドレイン間耐圧
が高く、しかもソース領域電気抵抗の低い電界効
果トランジスタが得られる。第3図a〜eで説明
した如く、本発明の方法を用いれば素子が微細化
し、ゲート電極33の幅が狭くなつた場合にもゲ
ート電極33幅には関係なく、再現性良く実現出
来る。
FIG. 3 is an explanatory diagram of a second embodiment of the present invention. As shown in FIG. 3a, after forming a gate insulating film 32 and a gate electrode 33 on a semiconductor substrate 31 having a first conductivity type, an emulsion type oxide 34 is applied to a portion corresponding to the electrode 33 of the oxide. Remove the part. Next, as shown in FIG. 3B, a photosensitive resin 35 is formed to shield at least the emulsion type oxide 34A, and then the emulsion type oxide 34B is removed using the resin 35 as a protective film. Next, as shown in FIG. 3c, by using the oxide 34A as a protective film and introducing an impurity having a second conductivity type different from the conductivity type of the substrate by ion implantation or the like, an emulsion-type oxide-free hole is formed. An impurity region 36 is formed in that portion. Next, as shown in FIG. 3d, after removing the oxide 34A, an impurity having a second conductivity type is introduced by a thermal diffusion region or by ion implantation. In the part where the impurity region 36 was formed, a region 37 with a deep impurity region depth and low electrical resistance is formed, and in the part where the region 36 was not formed, a region 37 with a high electrical resistance but with a low impurity region depth is formed. shallow area 38
is formed. Next, as shown in FIG. 3e, the electrode 39
and 40. When the electrode 40 is used as a drain and the electrode 39 is used as a source, a field effect transistor with high breakdown voltage between the source and drain and low electric resistance in the source region can be obtained. As explained with reference to FIGS. 3a to 3e, by using the method of the present invention, even when the device is miniaturized and the width of the gate electrode 33 becomes narrow, it can be realized with good reproducibility regardless of the width of the gate electrode 33.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来技術による半導体装置の製造方法
を示す断面図であり、第2図は本発明の一実施例
を示す断面図である。第3図a乃至第3図eは本
発明の他の実施例を工程順に示した断面図であ
る。 尚、図において、1,21,31は半導体基
体、2,22は絶縁膜、3,4,23,24は開
孔、5,25,35は感光性樹脂、6は感光性樹
脂端、26,27,34,34A,34Bはエマ
ルジヨン型オキサイド、32はゲート絶縁膜、3
3はゲート電極、36は第2の導電型の不純物領
域、37は電気的抵抗が低い領域、38は電気的
抵抗が高い領域、39,40は電極である。
FIG. 1 is a sectional view showing a method of manufacturing a semiconductor device according to the prior art, and FIG. 2 is a sectional view showing an embodiment of the present invention. FIGS. 3a to 3e are cross-sectional views showing another embodiment of the present invention in the order of steps. In the figure, 1, 21, 31 are semiconductor substrates, 2, 22 are insulating films, 3, 4, 23, 24 are openings, 5, 25, 35 are photosensitive resins, 6 is photosensitive resin ends, 26 , 27, 34, 34A, 34B are emulsion type oxides, 32 is a gate insulating film, 3
3 is a gate electrode, 36 is a second conductivity type impurity region, 37 is a region with low electrical resistance, 38 is a region with high electrical resistance, and 39 and 40 are electrodes.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体基板の一主表面上の凹凸を有する表面
上にエマルジヨン型オキサイドからなる第1の膜
を該凹部には厚く該凸部には薄く形成せしめる工
程と、前記凸部に薄く形成された第1の膜を除去
して該凸部の上面と該凹部内の該第1の膜の上面
とをほぼ平坦とした後に、感光性樹脂よりなる第
2の膜を該凸部上面および該凹部内の該第1の膜
の上面に形成する工程と、該第2の膜の前記主表
面上の所定の凹部を含む領域を選択的に開孔し、
該第2の膜を保護膜として前記所定の凹部内の前
記第1の膜を除去する工程と、該第2の膜を除去
した後に残存せる前記第1の膜を保護膜として不
純物を半導体基体中に導入することを特徴とする
半導体装置の製造方法。
1. Forming a first film made of emulsion type oxide on the uneven main surface of a semiconductor substrate, thicker in the recesses and thinner in the convex parts; After removing the first film to make the top surface of the convex portion and the top surface of the first film in the concave portion substantially flat, a second film made of photosensitive resin is applied to the top surface of the convex portion and inside the concave portion. selectively opening a region including a predetermined recess on the main surface of the second film;
removing the first film in the predetermined recess using the second film as a protective film; and removing impurities from the semiconductor substrate using the first film remaining after removing the second film as a protective film. 1. A method for manufacturing a semiconductor device, characterized by introducing the semiconductor device into a semiconductor device.
JP11207678A 1978-09-11 1978-09-11 Production of semiconductor device Granted JPS5538085A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11207678A JPS5538085A (en) 1978-09-11 1978-09-11 Production of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11207678A JPS5538085A (en) 1978-09-11 1978-09-11 Production of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5538085A JPS5538085A (en) 1980-03-17
JPS6210007B2 true JPS6210007B2 (en) 1987-03-04

Family

ID=14577462

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11207678A Granted JPS5538085A (en) 1978-09-11 1978-09-11 Production of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5538085A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0378122B2 (en) * 1988-03-23 1991-12-12 Kurita Machinery Manuf

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5087834B2 (en) * 2005-11-15 2012-12-05 日産自動車株式会社 Manufacturing method of semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50138769A (en) * 1974-04-23 1975-11-05
JPS5391676A (en) * 1977-01-24 1978-08-11 Matsushita Electric Ind Co Ltd Manufacture for semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50138769A (en) * 1974-04-23 1975-11-05
JPS5391676A (en) * 1977-01-24 1978-08-11 Matsushita Electric Ind Co Ltd Manufacture for semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0378122B2 (en) * 1988-03-23 1991-12-12 Kurita Machinery Manuf

Also Published As

Publication number Publication date
JPS5538085A (en) 1980-03-17

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