JPS62100023A - Counter control circuit - Google Patents

Abstract

PURPOSE:To ensure the accuracy by stopping the count tentatively only when a counter read request exists and correcting the count of the stopped counter after a time required to read the count. CONSTITUTION:When a counter read request exists, a counter read request signal is turned of for one system clock. Then a non-inverting output of a FF1 is turned on and the inverting output is turned off by the next system clock. Since the inverting output of the FF1 is turned off, a binary counter 2 executes no count and the output of the FF1 is turned on, a read register 4 reads the count of the binary counter 2. Then an update logic circuit 3 applies control to add '2' to the count of the binary counter 2 by the next system clock to correct the error by the count stop.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a counter control circuit for an electronic computer.

[Conventional technology]

Various types of counters are used in electronic computers, and are usually implemented as binary counters that count up or down at certain intervals. The time interval for counting up or down takes various values depending on the purpose of use, but the system clock counter is an example of one with the shortest counting time interval.

When a counter value is required, the counter control circuit that has received the counter read request reads the counter value into a counter read register and outputs it to an external circuit.

A counter read register is provided separately from the counter.
The reason why the counter value is once read into the counter read register is related to the constantly changing counter (i.e., the purpose is to enable the counter value to be output to an external circuit when a counter read request is made).

[Problem that the invention seeks to solve]

However, due to circuit implementation constraints, it may not be possible to mount the counter and the counter read register close to each other. On the other hand, as electronic computers become faster, system clocks also tend to become faster, and when the counter value changes rapidly like the system clock counter mentioned above, the counter value cannot be changed within one counter clock. A problem arises in that the data cannot be read and read into registers.

An object of the present invention is to provide a counter control circuit that solves these problems.

[Means for solving problems]

The counter control circuit of the present invention includes means for stopping counting for a number of count clocks corresponding to the time required to read the counter value when a counter reading is requested, and a means for stopping counting for a number of count clocks corresponding to the time required to read the counter value, and a means for stopping counting for the number of count clocks necessary for reading the counter value before restarting counting. The present invention is characterized by comprising means for adding a count clock number corresponding to the time to the counter.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a system clock counter control circuit which is an embodiment of the present invention, and shows flip-flops 1 and 2.
It consists of a binary counter 2, an update logic circuit 3 for controlling this binary counter, and a read register 4. The non-inverting output terminal 5 of the flip-flop 1 is connected to the control input terminal 7 of the read register 4 and the control input terminal 13 of the update logic circuit 3, and the inverting output terminal 6 is connected to one of the control AND gates 8 of the binary counter 2. are connected to the respective input terminals. The other input terminal of each A N D gate 8 is connected to each output terminal 9 of the update logic circuit 3,
Each output terminal 10 of the binary counter 2 is connected to each input terminal 11 of the update logic circuit 3 and to each input terminal 1 of the read register 4.
2 are connected to each other. Note that the counter reading request signal is input to the flip-flop 1.

Next, the operation of this embodiment will be explained.

When there is no counter read request, the counter read request signal is off, the non-inverted output of the flip-flop 1 is off, and the inverted output is on (2). At this time, since the flip-flow knob 10 inversion output is off,
The update logic circuit 3 outputs a control output to add 1 to the value of the binary counter 2, and the binary counter 2 counts the system clock under the control of the update logic circuit 3. Also, since the non-inverting output of the flip-flop 1 is off, the read register 4 retains the previously read counter value.

If there is a counter read request, the counter read request signal is on for l system clocks. Then, at the next system clock, the non-inverted output of flip-flop 1 is turned on and the inverted output is turned off. At this time, since the inverted output of flip-flop 1 is turned off, the binary counter 2 does not count, and furthermore, the read register 4 is set to 2 because the output of flip-flop 1 is turned on.
Read the value of decimal counter 2. Also, flip-flop 1
Since the non-inverting output of the update logic circuit 3 is on, the update logic circuit 3
outputs a control output to add 2 to the value of binary counter 2.

At the next system clock, the counter read request signal is already off, the non-inverted output of flip-flop 1 is turned off, and the inverted output is turned on. In addition, since the update logic circuit 3 outputs a control output to add 2 to the value of the binary counter 2, the binary counter 2 adds 2 to the count value.
is added to correct the counting error caused by the stoppage of the binary counter 2 that occurred during the previous system clock. Further, the read register 4 holds the counter value at the time of the previous counter read request.

Furthermore, after the next system clock, there is no counter read request as described above, the binary counter 2 continues counting the system clock, and the read register 4 continues to hold the previously read counter value.

In this embodiment, for simplicity, an example is given in which the read request pulse is equivalent to one system clock, but in order to stop counting for multiple system clocks, the counter read request signal is made into a pulse equivalent to multiple system clocks, and this pulse This can be easily done by sampling the output of the binary counter 2 into the readout register 4 using the trailing edge differential pulse, and by setting the value added to the binary counter 2 at the time of restarting counting as the value added by 1 to the number of stopped system clocks. This is possible.

Further, although the above embodiment has been explained using a system cross counter as an example, it is obvious that the present invention can also be applied to other counters, such as an instruction execution number counter, a timer counter, etc.

〔Effect of the invention〕

As explained above, the present invention temporarily stops counting only when a counter reading request is made, and after the time required to read the counter value has elapsed, the stopped counter value is corrected and the counting is resumed. The effect is that it can be restarted.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention in red. 1...Flip-flop 2...Binary counter 3...Update logic circuit 4...Read register 8...AND gate

Claims (1)

[Claims] (1) When a counter reading request is made, a means for stopping counting for the number of count clocks necessary to read the counter value, and a count clock for the time necessary for reading the counter value before restarting counting. A counter control circuit comprising: means for adding a number to the counter.