JPS6197237U - - Google Patents

Description

[Brief explanation of the drawing]

Figure 1 is a waveform diagram for explaining the operation of the integral type AD converter according to this invention, and Figure 2 is a flowchart for explaining the outline of a program for operating the integral type AD converter according to this invention. , FIG. 3 is a block diagram for explaining the structure of the integral type AD converter according to this invention and a conventional integral type AD converter, and FIG. 4 is a waveform diagram for explaining the operation of the conventional integral type AD converter. It is a diagram. 1: Input terminal, 2: Common potential terminal, 3: Calibration voltage terminal, 4: Common potential point, 6, 8: Selection circuit, 7
: Preamplifier, 9A, 9B: Reference voltage source, 10:
Switch drive circuit, 11: Analog integration circuit, 1
2: voltage comparator, 13: counter, 14: clock source, 15: calculation means, 16: display, T ₁ : first integration period, T ₂ ... second integration period, T ₃ : processing period.

Claims (1)

[Scope of utility model registration request] The voltage to be measured is first integrated for a certain period of time by an analog integrator, and a reference voltage of opposite polarity to the voltage to be measured is secondly integrated until the integrated voltage of the analog integrator returns to the initial value. A clock with a known frequency is counted by a counter, and the counted value obtained by the counter is taken into a calculation means, and a correction calculation is performed on the counted value to obtain the voltage value to be measured.
An integral type AD converter configured to start the next first integral operation at the time when the operation of taking in the count value from the counter to the calculation means is completed.