JPH01107993U - - Google Patents

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Publication number
JPH01107993U
JPH01107993U JP335688U JP335688U JPH01107993U JP H01107993 U JPH01107993 U JP H01107993U JP 335688 U JP335688 U JP 335688U JP 335688 U JP335688 U JP 335688U JP H01107993 U JPH01107993 U JP H01107993U
Authority
JP
Japan
Prior art keywords
signal
counter
minute
reset switch
minute counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP335688U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP335688U priority Critical patent/JPH01107993U/ja
Publication of JPH01107993U publication Critical patent/JPH01107993U/ja
Pending legal-status Critical Current

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  • Electric Clocks (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本考案の一実施例に係るデジタル時
計の回路図。第2図a,bは、第1図の修正動作
を示すタイムチヤート。 14…分カウンタ、36…リセツトスイツチ。
42…振り分け修正回路、48…分検出回路、6
0…第2カウンタ、66…減算修正回路、72…
第1カウンタ、80…加算修正回路。
FIG. 1 is a circuit diagram of a digital watch according to an embodiment of the present invention. FIGS. 2a and 2b are time charts showing the corrective operation of FIG. 1. 14...minute counter, 36...reset switch.
42...Distribution correction circuit, 48...Minute detection circuit, 6
0...Second counter, 66...Subtraction correction circuit, 72...
First counter, 80...addition correction circuit.

Claims (1)

【実用新案登録請求の範囲】 基準信号を発生する基準信号発生器と、この基
準信号により時刻の分をカウントする分カウンタ
と、この分カウンタからの桁上げ信号により時刻
の時をカウントする時カウンタと、この時・分カ
ウンタでカウントされた時刻を表示する表示部と
、前記分カウンタのカウント値が30〜59内で
あることを検知して検知信号を出力する分検知回
路と、外部操作可能なリセツトスイツチと、この
リセツトスイツチからの操作信号に応答して前記
分検知回路からの検知信号発生時には前記分カウ
ンタをクリアするとともに前記時カウンタを1歩
進させる第1の信号を出力し、検知信号非発生時
には前記分カウンタをクリアする第2の信号を出
力する振り分け回路と、を有するデジタル時計に
おいて、 前記分カウンタを加減算可能なアツプダウンカ
ウンタで構成するとともに、 前記リセツトスイツチが操作される毎にカウン
トを開始して一定時間後に出力信号を発生する第
1カウンタと、 前記リセツトスイツチがオン操作されている間
のみカウントしてそのカウント値が一定値になつ
たときに出力信号を発生する第2カウンタと、 前記第1および第2カウンタからの出力信号の
非発生時における前記リセツトスイツチのオン操
作に応答して前記分カウンタに加算信号を供給す
る加算修正回路と、 前記第2カウンタの出力信号発生時にのみ前記
基準信号発生器からの信号に対応した減算信号を
前記分カウンタに供給する減算修正回路と、 を設けたことを特徴とするデジタル時計の修正
回路。
[Claims for Utility Model Registration] A reference signal generator that generates a reference signal, a minute counter that counts the minutes of the time using this reference signal, and an hour counter that counts the hours of the time using a carry signal from the minute counter. , a display section that displays the time counted by the hour/minute counter, a minute detection circuit that detects that the count value of the minute counter is within 30 to 59 and outputs a detection signal, and can be operated externally. a reset switch, and in response to an operation signal from the reset switch, outputs a first signal that clears the minute counter and advances the hour counter by one step when a detection signal is generated from the minute detection circuit; A digital clock having a distribution circuit that outputs a second signal that clears the minute counter when the signal is not generated, wherein the minute counter is configured with an up-down counter that can add and subtract, and each time the reset switch is operated. a first counter that starts counting and generates an output signal after a certain period of time; and a second counter that counts only while the reset switch is turned on and generates an output signal when the count value reaches a constant value. an addition correction circuit that supplies an addition signal to the minute counter in response to an on operation of the reset switch when output signals from the first and second counters are not generated; and an output of the second counter. A correction circuit for a digital timepiece, comprising: a subtraction correction circuit that supplies a subtraction signal corresponding to a signal from the reference signal generator to the minute counter only when a signal is generated.
JP335688U 1988-01-13 1988-01-13 Pending JPH01107993U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP335688U JPH01107993U (en) 1988-01-13 1988-01-13

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP335688U JPH01107993U (en) 1988-01-13 1988-01-13

Publications (1)

Publication Number Publication Date
JPH01107993U true JPH01107993U (en) 1989-07-20

Family

ID=31204919

Family Applications (1)

Application Number Title Priority Date Filing Date
JP335688U Pending JPH01107993U (en) 1988-01-13 1988-01-13

Country Status (1)

Country Link
JP (1) JPH01107993U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55101075A (en) * 1979-01-29 1980-08-01 Citizen Watch Co Ltd Electronic watch with reset-to-zero unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55101075A (en) * 1979-01-29 1980-08-01 Citizen Watch Co Ltd Electronic watch with reset-to-zero unit

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