JPS6195543A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6195543A JPS6195543A JP59216251A JP21625184A JPS6195543A JP S6195543 A JPS6195543 A JP S6195543A JP 59216251 A JP59216251 A JP 59216251A JP 21625184 A JP21625184 A JP 21625184A JP S6195543 A JPS6195543 A JP S6195543A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- film
- silicon nitride
- etching
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/763—Polycrystalline semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
Abstract
Description
【発明の詳細な説明】 〔発明の利用分野〕 本発明は半導体装置の製造方法に係り、特に。[Detailed description of the invention] [Field of application of the invention] The present invention relates to a method of manufacturing a semiconductor device, and particularly relates to a method of manufacturing a semiconductor device.
絶縁物による素子分離技術に好適な半導体装置の製造方
法に関する。The present invention relates to a method of manufacturing a semiconductor device suitable for element isolation technology using an insulator.
従来、半導体集積回路における素子分離技術として半導
体基板の一部分を窒化シリコン等をマスクとして選択的
に酸化する選択酸化法、あるいは、半導体基板に溝を設
け、絶縁膜、あるいは、絶縁膜を介して多結晶シリコン
を堆積し、この溝を充填することにより、分離領域を形
成する方法等が知られている。選択酸化法は高温処理が
必要であり、また、バーズビークと呼ばれる熱酸化膜の
横方向への伸びがある等の欠点がある。これに対し、分
離溝を充填する方法は高温処理を必要とせず、バーズビ
ークの発生もないことに加えて、分離領域の厚さを任意
に設定できる等の特長がある。このため、素子分離領域
の縮小が可能であり、またｐｎ接合分離に比べて寄生容
量が低減できる等の利点がある。Conventionally, element isolation techniques for semiconductor integrated circuits include selective oxidation, in which a part of the semiconductor substrate is selectively oxidized using silicon nitride, etc. as a mask; A method is known in which an isolation region is formed by depositing crystalline silicon and filling the trench. The selective oxidation method requires high-temperature treatment and has drawbacks such as the lateral extension of the thermal oxide film called bird's beak. On the other hand, the method of filling the separation grooves does not require high-temperature treatment, does not generate bird's beaks, and has the advantage that the thickness of the separation region can be set arbitrarily. Therefore, it is possible to reduce the element isolation region, and there are advantages such as reducing parasitic capacitance compared to pn junction isolation.
これらの素子分離領域はｐ型拡散層とｎ型拡散磨の境界
およびこれらの拡散層の所定の領域に形成される。とこ
ろが、分離溝の充填による素子分離技術では分離領域の
巾が狭いため、所定の領域に分離溝を形成する際に、形
成領域のずれが生じやすく、このため、素子特性の劣化
やばらつきを生じやすいという欠点があった。These element isolation regions are formed at the boundaries between the p-type diffusion layer and the n-type diffusion layer and at predetermined regions of these diffusion layers. However, in device isolation technology that involves filling isolation trenches, the width of the isolation region is narrow, so when forming the isolation trench in a predetermined region, the formation region tends to shift, resulting in deterioration and variation in device characteristics. The drawback was that it was easy.
本発明の目的は、分離溝による素子分離領域を二つの異
なった導電型の拡散層の境界およびこれらの拡散層のい
ずれか一方の任意の領域に自己整合的に形成できる半導
体装置の製造方法を提供することにある。An object of the present invention is to provide a method for manufacturing a semiconductor device in which an element isolation region using an isolation trench can be formed in a self-aligned manner at the boundary between two diffusion layers of different conductivity types and at an arbitrary region of either of these diffusion layers. It is about providing.
本発明は半導体基板上に被着された膜をフォトリソグラ
フィ一工程によってウェットエツチングする際に起こる
サイドエツチングを巧みに利用して、異なった導電型の
拡散層の形成と自己整合的にこれらの境界に分離溝を形
成し、いずれが一方の拡散層内の任意の領域に同じく拡
散層の形成と自己整合的に分離溝を形成するにある。The present invention skillfully utilizes the side etching that occurs when a film deposited on a semiconductor substrate is wet-etched in a single photolithography step to form diffusion layers of different conductivity types and to form these boundaries in a self-aligned manner. An isolation groove is formed in any region within one of the diffusion layers, and the isolation groove is formed in a self-aligned manner with the formation of the diffusion layer.
以下１本発明の一実施例を図面を用いて説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図（ａ）〜（Ｒ）は本発明を適用した一実施例の断
面構造図である。まず、（ａ）に示すように単結晶シリ
コン基板４の表面を熱酸化し２例えば４３０人の熱酸化
膜５を形成する０次に、耐酸化マスクとなる膜、例えば
、厚さ１５００人の窒化シリコン膜６を形成する。さら
に、窒化シリコン臆６の上に例えば、厚さ１０００人の
ポリシリコン膜３を形成する。FIGS. 1A to 1R are cross-sectional structural views of an embodiment to which the present invention is applied. First, as shown in (a), the surface of the single crystal silicon substrate 4 is thermally oxidized to form a thermal oxide film 5 of, for example, 430 mm thick. A silicon nitride film 6 is formed. Furthermore, a polysilicon film 3 having a thickness of, for example, 1000 wafers is formed on the silicon nitride film 6.
さらにポリシリコン膜３の上に厚さ５０００人のＨＬＤ
膜７を形成する。ここで、酸化膜５は必ずしも形成され
なくともよい、また、ポリシリコン膜３の上に形成する
膜７はウェットエツチング法を選定することによって［
ｌｉ６及び膜３よりエツチング速度が十分速い条件が得
られる膜であるなら、他の膜を用いてもかまわない、［
７の厚さは後述する（ｇ）までにエツチングされないよ
うに設定される。膜５．６，３．７の厚さは、これらの
膜厚の和が分離溝が形成されるまでの後述する工程でエ
ツチングされない厚さであるならば任意に設定される０
次に、（ｂ）に示すようにフォトレジスト８を、通常の
フォトリソグラフィ一工程でパターニングし、（Ｃ）に
示すように、ＨＬＤ膜７およびポリシリコン膜３をドラ
イエツチング法によって除去する０次に、例えば、フッ
化アンモニア液を用いてウェットエツチングを行なうこ
とにより、（ｃｌ）に示したように、パターン巾の狭い
部分ではＨＬＤｇＩ７は除去され、ポリシリコンの狭い
部分９が形成される。また、パターン巾の広い部分では
、サイドエラチンブレこよってＨＬＤＩＩ％７でその上
にない部分１０が形成される０次に、フォトレジスト８
を除去し、窒化シリコン膜が除去されるまで、ドライエ
ツチングを行なうことにより、（ｅ）に示したように、
巾の狭いパターン９．１０が形成される。（ｄ）に示し
たウェットエツチング条件は、狭いパターン９の上のＨ
ＬＤ膜が除去され、かつ、パターン１０の巾の設定値が
得られるように決められる。フォトマスク上のパターン
９の１１１の設定値は、パターン１０の巾の設定値の二
倍以下に限定される。また、ＨＬＤ膜７の代わりに酸化
膜および窒化シリコン膜の両者よりエツチング速度が十
分速いウェットエツチング条件が得られる膜を用いるな
らば、（ｃ）で酸化膜５が露出するまでエツチングして
もかまわない、また、この場合、ポリシリコン膜３は形
成しなくてもよい１次に、（ｆ）に示すように酸化膜５
が露出している部分に、イオン打込み法によってｎ型不
純物リン１１が打込まれ、ｎ型拡散層１２が形成される
０次に、必要ならば、９及び１０に残余しているポリシ
リコン膜を除去する。Furthermore, an HLD with a thickness of 5000 on the polysilicon film 3
A film 7 is formed. Here, the oxide film 5 does not necessarily have to be formed, and the film 7 formed on the polysilicon film 3 can be etched by selecting a wet etching method.
Other films may be used as long as they provide a sufficiently faster etching rate than li6 and film 3.
The thickness of 7 is set so that it will not be etched until (g) which will be described later. The thickness of the films 5.6 and 3.7 can be arbitrarily set to 0 as long as the sum of these film thicknesses is a thickness that will not be etched in the process described later until the separation groove is formed.
Next, as shown in (b), the photoresist 8 is patterned in one step of normal photolithography, and as shown in (c), the HLD film 7 and polysilicon film 3 are removed by dry etching. Then, by performing wet etching using, for example, an ammonium fluoride solution, the HLDgI 7 is removed in the narrow portion of the pattern, and a narrow portion 9 of polysilicon is formed, as shown in (cl). In addition, in a wide pattern width part, due to side erachin blur, a part 10 that is not above HLDII%7 is formed.
By removing the silicon nitride film and performing dry etching until the silicon nitride film is removed, as shown in (e),
A narrow pattern 9.10 is formed. The wet etching conditions shown in (d) are as follows:
It is determined so that the LD film is removed and the set value of the width of the pattern 10 is obtained. The set value of 111 of pattern 9 on the photomask is limited to twice or less the set value of the width of pattern 10. Furthermore, if a film is used in place of the HLD film 7 that provides wet etching conditions that allow the etching rate to be sufficiently faster than both the oxide film and the silicon nitride film, etching may be performed until the oxide film 5 is exposed in (c). Also, in this case, the polysilicon film 3 does not need to be formed, and the oxide film 5 is formed as shown in (f).
An n-type impurity phosphorus 11 is implanted into the exposed portion by ion implantation to form an n-type diffusion layer 12. If necessary, the polysilicon film remaining on 9 and 10 is removed. remove.
あるいは、後述する（ｇ）の酸化の後に除去してもよい
０次に、（ｇ）に示すように窒化シリコン＠６をマスク
として、例えば、４０００人の熱酸化膜５′が形成され
る。酸化膜５′の厚さは後述するシリコンドライエツチ
ング後にイオン打込みのマスクとして十分な厚さになる
よう設定される９次に、パターン９，１０の部分の窒化
シリコン膜を、例えば、熱リン酸液で除去し、酸化膜を
エツチングすると、（ｈ）に示したようにシリコンの露
出した＋ｔＪの狭い領域１３．１４が形成される１次に
、（ｉ）に示すように、シリコンをドライエツチングし
て、溝１３’ 、１４’ を形成する。次に、必要なら
ば、溝底部のチャネルストッパー１７を形成するため、
例えば、フッ化ボロンをイオン打込みし、アニール熱処
理を施こす０次に、残存するＨＬＤ膜７を除去し、窒化
シリコン膜６を熱リン酸液で除去した後、ｐ型不純物と
して１例えば。Alternatively, as shown in (g), a thermal oxide film 5' of 4,000 layers is formed using silicon nitride@6 as a mask, which may be removed after the oxidation in (g), which will be described later. The thickness of the oxide film 5' is set to be sufficient as a mask for ion implantation after silicon dry etching, which will be described later. When the oxide film is removed with a liquid and the oxide film is etched, a narrow region 13.14 of +tJ with exposed silicon is formed as shown in (h).First, as shown in (i), the silicon is dry etched. Grooves 13' and 14' are thus formed. Next, if necessary, to form a channel stopper 17 at the bottom of the groove,
For example, boron fluoride is ion-implanted, annealing heat treatment is performed, the remaining HLD film 7 is removed, the silicon nitride film 6 is removed with a hot phosphoric acid solution, and then, for example, 1 is implanted as a p-type impurity.
フッ化ボロン１５をイオン打込みし、（ｊ）に示すよう
にｐ型拡散Ｎ境界を形成する。この時、醸化膜５′はフ
ッ化ボロン１５のイオン打込みのマスクとして十分な厚
さになるよう設定する必要があるため、必要ならば窒化
シリコン膜６を除去する前に再酸化してもよい。この後
、通常の工程で分離溝を充填し、素子分離領域が形成さ
れる。例えば、（ｈ）に示したように溝内部を酸化した
後。Boron fluoride 15 is ion-implanted to form a p-type diffusion N boundary as shown in (j). At this time, it is necessary to set the fostered film 5' to a sufficient thickness as a mask for ion implantation of boron fluoride 15, so if necessary, it may be reoxidized before removing the silicon nitride film 6. good. Thereafter, the isolation grooves are filled in a normal process to form element isolation regions. For example, after oxidizing the inside of the groove as shown in (h).
窒化シリコン膜１８を被着せしめ、その後、多結晶シリ
コン１９で溝を埋める１次に選択酸化領域をパターニン
グし、ｐ型拡散層の選択酸化領域に。A silicon nitride film 18 is deposited, and then a primary selective oxidation region filling the trench with polycrystalline silicon 19 is patterned to become a selective oxidation region of a p-type diffusion layer.
例えば、フッ化ボロンをイオン打込みしてチャネルスト
ッパー２０を形成し、選択酸化を行なう。For example, the channel stopper 20 is formed by ion implantation of boron fluoride, and selective oxidation is performed.
さらに、必要ならば、酸化膜の段差を小さくする工程を
加え、（ｆｌ）に示したように、素子分離領域が完成す
る。この工程によって、Ｐ型拡散層と。型拡散層の境界
およびｎ型拡散層の任意の部分に素子分離溝が形成され
た構造が得られる。この後、各分離領域内に、通常の方
法でバイポーラおよびＣＭＯ３構造を形成し素子が形成
される。Further, if necessary, a step of reducing the step of the oxide film is added, and the element isolation region is completed as shown in (fl). This process creates a P-type diffusion layer. A structure is obtained in which element isolation grooves are formed at the boundaries of the type diffusion layer and at arbitrary parts of the n-type diffusion layer. Thereafter, devices are formed by forming bipolar and CMO3 structures in each isolation region using conventional methods.
以上の工程で、窒化シリコン膜６とポリシリコン膜３の
上下を入れ換えた構造、あるいは、さらに、他の膜を被
着せしめ、三層以上とした構造でも上記と同様の工程を
実現できる。また、窒化シリコン膜６とポリシリコン膜
３の代わりに、厚さを適宜に設定した窒化シリコン膜を
一層とし、この膜のエツチングを膜厚の半ばまで行なう
ことによっても同様の工程が実現できる。In the above process, the same process as described above can be realized with a structure in which the silicon nitride film 6 and the polysilicon film 3 are interchanged vertically, or with a structure in which other films are deposited to form three or more layers. Furthermore, the same process can be realized by using a single layer of silicon nitride film with an appropriately set thickness instead of the silicon nitride film 6 and polysilicon film 3, and etching this film to the middle of the film thickness.
上記の実施例では、ｐ型・ｎ型拡散層境界とｎ梨拡散層
内に溝を形成する工程を示したが、ｐ型７）・型拡散Ｎ
境界とｐ型拡散層内の任意の部分に分離溝を形成した構
造、あるいは、濃度の異なる二Ｍ１類のｐ型、あるいは
、ｎ型拡散層の異濃度拡散層間の境界と、いずれか、一
方の領域内の任意の部分に分離溝を形成した構造、ある
いは、単一のｐ型あるいはｎ型拡散層の所定の部分に分
子ｉ溝を形成した構造などにも適用できることは明らか
である。In the above embodiment, the process of forming grooves at the boundary between p-type and n-type diffusion layers and within the n-type diffusion layer was shown, but
A structure in which a separation groove is formed at any part of the boundary and the p-type diffusion layer, or a boundary between two M1 type p-type or n-type diffusion layers with different concentrations. It is clear that the present invention can also be applied to a structure in which an isolation groove is formed in any part of the region, or a structure in which a molecular i-groove is formed in a predetermined part of a single p-type or n-type diffusion layer.
また、シリコ、ン基板に代わって、ｐ型、ｐ型あるいは
これらの両者が埋込み層として形成され、その上部にエ
ピタキシャルシリコン層が形成された基板、あるいは、
絶縁層１例えば、ＳｉＯ，ｕの上に単結晶Ｓｉ層が形成
された、いわゆる、５ＯＩ（Ｓｉｌｉｃｏｎ ｏｎ Ｉ
ｎ５ｕｌａｔｏｒ） ｊｌｔ造の基板などにも本発明が
適用できることは明らかである。In addition, instead of a silicon substrate, a substrate in which p-type, p-type, or both of these are formed as a buried layer and an epitaxial silicon layer is formed on top of the buried layer, or
Insulating layer 1 For example, a so-called 5OI (Silicon on I) in which a single crystal Si layer is formed on SiO, u.
It is clear that the present invention can also be applied to substrates manufactured by JLT.
本発明によれば、分離溝による素子分離領域を二種類の
異なった領域、すなわち、二つの異なった導電型の拡散
層の境界、および、これらの拡散層のいずれか一方の任
意の領域の両方に同時に自己整合的に形成できる効果が
ある。According to the present invention, the element isolation region by the isolation trench is divided into two different regions, that is, the boundary between two diffusion layers of different conductivity types, and the arbitrary region of either of these diffusion layers. It has the effect that it can be formed in a self-consistent manner at the same time.
第１図（ａ）〜（Ｑ）は本発明を適用した一実施例の断
面構造図である。
：（ポＩＪシリコン膜、４ シリコン基板、５・熱酸化
膜、６．１８・・窒化シリコン膜、７・・・ＨＬＤ：１
情、８・・・フォトレジスト、９．１０，１３．１４溝
形成部、１Ｌ・・・リンイオン、１２・・・ｎ型拡散贋
、５′・・選択酸化膜、１３’ 、１４’・・・溝、１
５ ・フッ化ボロンイオン、１６・・Ｐ型拡散層、１．
７．２０・・ｐ３チャネルストッパー、１９・・・多も
１７FIGS. 1(a) to 1(Q) are cross-sectional structural views of an embodiment to which the present invention is applied. : (PoIJ silicon film, 4 silicon substrate, 5 thermal oxide film, 6.18...silicon nitride film, 7...HLD: 1
Information, 8... Photoresist, 9.10, 13.14 groove forming part, 1L... phosphorus ion, 12... n-type diffusion counterfeit, 5'... selective oxide film, 13', 14'...・Groove, 1
5 - Boron fluoride ion, 16... P-type diffusion layer, 1.
7.20...p3 channel stopper, 19...Tamo 17
Claims (1)
る工程と、前記第一の層上に第二の層さらに第三の層を
形成する工程と、前記第二の層と前記第三の層をホトリ
ソグラフィー法を用いて部分的にエッチングする工程と
、前記第三の層をホトレジストが除去されない状態でサ
イドエッチングして前記第三の層が前記第二の層上にな
い巾の狭い部分が前記第一の層が露出した領域にはさま
れている部分及び前記第一の層が露出した領域と前記ホ
トレジストの下に前記第三の層がある領域にはさまれて
いる部分の両者を共在せしめる工程と、前記ホトレジス
トを除去する工程と、前記第一の層をエッチングする工
程と、前記第一の層がエッチングされた部分に一種類の
導電型を示す不純物を導入する工程と、前記第一の層が
エッチングされた部分を選択酸化する工程と、表面に露
出した前記第二の層及び前記第一の層を除去する工程と
、表面に基板が露出した部分をエッチングして溝を形成
する工程と、前記一種類の導電型を示す不純物を導入し
た領域以外の部分に他種類の導電型を示す不純物を導入
する工程と、溝を絶縁物もしくは絶縁物を介した多結晶
シリコンで埋める工程からなることを特徴とする半導体
装置の製造方法。 ２、前記半導体基板と前記第一の層の間に酸化膜を介在
させる工程を設けたことを特徴とする特許請求の範囲第
１項記載の半導体装置の製造方法。 ３、前記第一の層として窒化シリコン、前記第二の層と
してポリシリコンまたはＨＬＤ膜のいずれか一方、前記
第三の層に前記第二の層に用いたものの中の他方を用い
ることを特徴とする特許請求の範囲第１項または第２項
記載の半導体装置の製造方法。[Claims] 1. A step of forming a first layer serving as an oxidation-resistant mask on a semiconductor substrate, a step of forming a second layer and further a third layer on the first layer, and a step of forming a second layer and a third layer on the first layer; partially etching the second layer and the third layer using a photolithography method, and side etching the third layer without removing the photoresist so that the third layer becomes the second layer. A narrow part that is not on the layer is sandwiched between the exposed area of the first layer, and an area where the third layer is below the exposed area of the first layer and the photoresist. a step of making both the sandwiched parts coexist; a step of removing the photoresist; a step of etching the first layer; a step of selectively oxidizing the etched portion of the first layer; a step of removing the second layer and the first layer exposed on the surface; a step of etching the exposed portion to form a groove; a step of introducing an impurity of a different conductivity type into a region other than the region into which the impurity of the one conductivity type has been introduced; and a step of etching the groove with an insulating material. Alternatively, a method for manufacturing a semiconductor device comprising a step of filling with polycrystalline silicon via an insulator. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of interposing an oxide film between the semiconductor substrate and the first layer. 3. The first layer is silicon nitride, the second layer is either polysilicon or an HLD film, and the third layer is the other one of those used for the second layer. A method for manufacturing a semiconductor device according to claim 1 or 2.
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59216251A JPS6195543A (en) | 1984-10-17 | 1984-10-17 | Manufacture of semiconductor device |
| EP85113127A EP0178649B1 (en) | 1984-10-17 | 1985-10-16 | Complementary semiconductor device |
| CN85108969.0A CN1004736B (en) | 1984-10-17 | 1985-10-16 | Complementary semiconductor device |
| KR1019850007623A KR900005124B1 (en) | 1984-10-17 | 1985-10-16 | Complementary semiconductor device |
| DE8585113127T DE3583575D1 (en) | 1984-10-17 | 1985-10-16 | COMPLEMENTAL SEMICONDUCTOR ARRANGEMENT. |
| US07/085,260 US4862240A (en) | 1984-10-17 | 1987-08-12 | Complementary semiconductor device |
| US07/744,514 USRE34158E (en) | 1984-10-17 | 1991-08-13 | Complementary semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59216251A JPS6195543A (en) | 1984-10-17 | 1984-10-17 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6195543A true JPS6195543A (en) | 1986-05-14 |
Family
ID=16685634
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59216251A Pending JPS6195543A (en) | 1984-10-17 | 1984-10-17 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6195543A (en) |
-
1984
- 1984-10-17 JP JP59216251A patent/JPS6195543A/en active Pending
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