JPS6194359A - Buried channel type charge coupler - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a channel structure for a charge-coupled device (CCD) with a buried channel that improves charge transfer efficiency at low temperatures, and in particular for an infrared CCD (R-CCD).
) This relates to a CCD channel structure useful for image sensors.
It is a transfer device (transfer state). Generally, this type of device is used for example ``4mlz-!'' The device comprises a body of a semiconductor material, such as 2-9, with channels in the body in the form of regions of opposite conductivity type extending along the surface of the body. A plurality of conductive gates extend across and insulated from the channel and are disposed along the channel. By applying appropriate potentials to these gates in turn, the charge in the channel is transferred along the channel. Such a ccD transfer device may include, for example, a plurality of radiation detectors arranged in a row, provided along each row of the radiation detectors, and connected to each other in the row. Another transfer CCD
It is used for image sensors equipped with resistors. The charge generated in the detector by the radiation received by the detector is transferred to O(D) connected to it, and then
The transfer 00D registers extend along one end and are connected to the output CCD registers.
It is transferred along the CCD. This output CCD register transfers the charge to the output circuit. -911 is an image sensor using a 7-way barrier detector for infrared detection.
SP Engineering E, Volume 344 “Infrared sensor engineering (Infr
ared 5ensor Techno, 1ogy)
J 1982, pages 66A-77,
A paper by W. F. Kozonotsky et al. [64 x 128 element Pt5i Schottky barrier infrared charge coupled device (IRC
CD) Design and performance of focal plane arrays
ana Performance of 64X 12
8Filement PtSi 5chottky
-Barrier
Coupled Device (RCCD)F
ocal PlaneArray) J.

One problem that arises in the use of CCD transfer devices is due to the device's inefficiency in charge transfer. The inefficiency of charge transfer is related to charge transfer losses, which in buried channel CCDs are proportional to the volume of the buried channel. Charge transfer inefficiencies in CCDs are particularly problematic in infrared CCD image sensors that require low operating temperatures in the range of 77 to 130", since in this case the charge transfer efficiency is low at low operating temperatures. This is particularly problematic when the image sensor is operated at low signal levels that produce a signal load that does not fill the channels of the OCD.

[Summary of the invention]

The buried channel torpedo coupling device according to the invention has a substrate of semiconductor material of one conductivity type, the substrate having at least one major surface. A first means for confining charge is provided in the substrate along said major surface.

Further, a second means is provided which confines an amount of charge within the substrate along the main surface, which is less than the amount confined by the first means, and further allows excess charge to flood into the first means. Two means are provided. A plurality of conductive cages are provided on the main surface of the substrate along the confinement means.

[Explanation of Examples]

Referring first to FIG. 1, there is shown a schematic block diagram of a typical R-CCD sensor array, indicated generally at 10. The sensor array 1o includes a plurality of R detectors 12 arranged in vertical rows parallel to each other. Along each column of detectors 12 extends a vertical column CCD register 14 to which an adjacent vertical column of detectors 12 is connected. Input OC
A D register 16 extends along one end of the vertical column CCD registers 14 and is connected to each of the vertical column CCD registers 14.

Additionally, an output CCD register 18 extends along the other end of the vertical column CCD register 14, with each column CCD register 18 extending along the other end of the vertical column CCD register 14.
It is connected to the register 14.

Figures 2 and 3 show the R-CCD of the engineer implementing this invention.
The structure of one pixel of one type of image sensor is shown in detail. This pixel includes one detector 12 and a portion of its associated vertical column 00D register 14. The sensor array 1° is formed in and on a P conductivity type single crystal silicon substrate having a pair of front and back main surfaces 22 and 24. Detector 12 includes a thin layer 26 of conductive material, such as palladium or platinum silicide.
and is formed in the substrate 20 along the surface 24. This conductive layer 26 forms a Schottky barrier junction with the substrate 20.

A guard ring 28 extends from surface 24 into substrate 20 in the form of a region of N conductivity type surrounding the edge of conductive layer 26 .

Surrounding the guard ring 28 is a channel stop 30, which is a region of medium conductivity type extending from the surface 24 into the substrate 20. At the edge of the conductive layer 26 adjacent to the vertical CCD register 14, a conductive layer 32 of N0 conductivity type is provided on the surface 24.
The conductive layer 26 extends into the substrate 20 and partially overlaps and contacts the conductive layer 26 .

Vertical CCD register 14 includes a physiological input channel 34 in the form of an N-type region extending within substrate 20 along surface 24 parallel to the rows of detectors 12 . Within this main buried channel 34 is an auxiliary buried channel 36, which is a more deeply doped N-type region extending along surface 24 within substrate 20. The auxiliary recessed channel is
The concentration of conductive transducer is higher than that of the main channel 34 so that it has a higher conductivity than the main channel 34 . Further, the auxiliary channel 36 has a volume smaller than that of the main channel 34 so that the auxiliary channel 36 is entirely contained within the main channel 34 . thin layer of silicon oxide 3
8 covers the entire surface 24 of the substrate 20. A plurality of gates 40 are disposed side by side on silicon oxide layer 38 and extend across channels 34 and 36. These gates 40 are layers of conductive material, for example conductive polycrystalline silicon. A layer of silicon oxide 42 is provided over the gate 40. Four metal bus lines 44, typically formed of aluminum, extend parallel to each other and spaced apart across the gate 40 over the silicon oxide layer 42. Each bus line 44 extends through an aperture in the silicon oxide layer 42 and contacts a different one of the gates 40. Each bus line 44 has every third gate 40
It is connected to the.

A transfer gate 46 overlies the silicon oxide layer 38 and extends between the detector 12 and the vertical CCD register 14. The transfer gate 46 is a layer of conductive material, such as doped polycrystalline silicon. Transfer gate 46 overlaps a portion of conductive region 32 and an edge of main buried channel 34 . A layer of silicon oxide extends over transfer gate 46. One of the gates 40 of the vertical CCD register 14 is aligned with the conductive region 32 of the detector 12. This allows charge to be transferred from the detector 12 to the vertical CCD register 14. A thin layer 5o of metal, such as aluminum, is provided on the silicon oxide layer 38 overlying each of the conductive layers 26 of the detector 12. This metal layer 50 acts as a mirror to reflect the radiation passing through the conductive layer 26 back to the conductive layer.

In operation of sensor array 10, from surface 22 to substrate 2
The radiation passing through 0 is converted into an electric charge by the detector 12. When a suitable potential is applied to transfer gate 46,
Charge in conductive layer 26 of detector 12 is transferred to channels 34 and 36 of vertical CCD register 14. Ge.

By sequentially applying appropriate potentials to ports 40, the charge in channels 34, 36 is transferred along vertical CCD registers 14 to the output CCD registers.

Applying a potential to gate 40 creates potential wells in channels 34 and 36. Because the auxiliary channel 36 has a higher doping level than the main channel 34, the auxiliary channel 36 has a higher doping level than the main channel 34, as shown in FIG.
The potential wells in 6 are deeper than the potential wells formed in the main channel. Therefore, when charge is transferred from detector 12 to channels 34 and 36, the charge flows first into the deeper well formed in auxiliary channel/channel 36. If the amount of charge is large enough, the charge will spill out of the deeper well and flow into the shallow well formed by channel 34. However, if the amount of charge is small, it will be confined only within the auxiliary channel 36.

As mentioned above, the transfer inefficiency is proportional to the volume of the buried channel. By retaining a small amount of charge in the small volume of the auxiliary channel 36, the efficiency of charge transfer along the auxiliary channel 36 is higher than if the same small amount of charge was transferred in the large volume of the main channel 34. . Therefore, small charges are transferred within the CCD register 14 with high efficiency.

On the other hand, large charges flow into the wells of the main channel fixture,
It is properly transferred through channel 34 with relatively high efficiency.

Thus, the CCD register according to the invention can transfer both small and large charges with relatively high efficiency.

5 to 7 show an IR-CCD implementing this invention.
Another embodiment of an image sensor is shown.

The image sensor 52 includes an array of detectors 54 arranged in columns and a vertical CCD register 56 provided between the columns of the detectors 54. Similarly, the opposing main surface 6
0 and 62 P conductivity type single crystal silicon substrate 58
formed inside.

Each of the detectors 54 includes a region 64 of conductive material along a surface 62 in the substrate 58 . This area 64 is
A Schottky barrier junction is formed between B and B. Detector region 64 is preferably formed of either platinum silicide or palladium silicide. A protective ring 66 is formed around the edge of the detector region 64 .

The N 1J ring is formed on the surface 62 within the substrate 58.
This is a conductive type region. Along the edge of the detector region 64 adjacent to the vertical CCD register 56, a conductive region 68 of type N+4 is provided on the surface 62 within the substrate 5. This conductive region 68 is perpendicular to the detector 54.
It serves to electrically couple charge to the channel of D resistor 56. However, if necessary, the entire protective ring 66 may be of the N+4 type so that the protective ring 66 also functions as a conductive region.

A layer of deposited silicon oxide 70 is provided on the surface 62 of the substrate 58 and extends over the detector region 64 .

Furthermore, a metal layer 72 is provided on the silicon oxide layer 70 and covering each detector region 64 . Metal layer 72 is comprised of a radiation-reflecting metal, such as aluminum, which acts as a mirror to reflect radiation that has passed through detector region 64 back to the detector region.

Vertical CCD register 56 includes a main channel 74 in the form of an N4 lightning-shaped region in substrate 58 and extending along surface 62 between rows of detectors 54. Main channel 74 is spaced apart from an adjacent edge of detector region 64 of detector 54 . Main channel 74
Therein is provided an auxiliary channel 75 consisting of a region of N conductivity type but with a higher concentration of conductive converter than the main channel 74 .

This auxiliary channel 75 has a volume equal to that of the main channel 75.
It is smaller than the main channel 74 and fits completely within the main channel 74. A layer of thermally grown silicon oxide 76 forms the channel 7.
4 and 75. On this silicon oxide layer 76, two sets of gates 7 are placed across the channels 74 and 75.
7 and 78 are provided. Gate foot 78 is formed of a conductive material such as doped polycrystalline silicon. The gate cost of the first set is all silicon oxide layer 76
each gate 77 extends along and across the space between two adjacent detectors 54. Adjacent edges of adjacent gates 77 are separated by a portion of channels 74 and 75 adjacent to the conductive region 6 of detector 54 adjacent thereto. Each of the first set of gateguars has an extension 77? L, and this extension 77a extends between the substrate surfaces 6 between adjacent detectors 54.
2 and separated from substrate surface 62 by a portion of silicon oxide layer 76 . Gate extension 7'
7a is a similar first register in all vertical CCD registers 14.
The sets of gates 77 are electrically connected and one of the gate extensions a extends to an edge contact at one end of the sensor array 10.

As shown in FIG. 7, each of the six gates of the second set of gates 78 is
It is located on the silicon oxide layer 76 between the mutually spaced edges of two mutually adjacent first gates 77 . The second gate 78 extends slightly above one of the adjacent first gates 77 and extends above the other gate 77 into the space between two mutually adjacent detectors 54 . Second
gate 78 is separated from first gate 77 by a layer 80 of silicon oxide. As shown in FIG. 6, each of the second gates 78 extends to the edge of the detector 54 on each side of the vertical CCD register 56. The second gate 78 thus extends beyond both sides of the main channel 74 and over the portion of the substrate surface 62 between the main channel 74 and each of the adjacent detectors 54 .

In the regions of the substrate surface 62 between the detector 54 and the main channel 74 that are not connected to the vertical CCD registers 56 of 'l, the silicon oxide layer 76 is thicker in parts 7 than in other parts.
I have 6a. The thick part of this silicon oxide layer'7
Above 6a is a portion of each of the second gates 78, so that a portion of this gate 78 is separated from the substrate surface by a distance greater than the distance between the remaining portion thereof and the substrate surface 62. Each of the second gates 78 is connected to the first gate 7
7 and separated therefrom by a silicon oxide layer. Each extension 78a electrically connects a corresponding second gate of vertical CCD register 56 to one of the extensions '78a extending to a terminal at one end of image sensor array 52.

In operation of the image sensor 52, the charge collected on the detector 54 is transferred to the vertical CCD register 56 when a positive potential is applied to the second gate 7.

Gate foot 78 is then clocked with a negative potential to move the charge along channels 74 and 75 to an output register at one end of vertical ccD register 56. The potential applied to gate foot 78 causes potential wells to form in channels 74 and 75. In this case, auxiliary channel '7
The well 5 is deeper than the well in the main channel 74. Thus, charge entering channels 74 and 75 from detector 54 first fills the deeper wells in auxiliary channel '75 and, if the charge is large enough, spills into the wells of main channel 74; When the charge from 54 is small, the charge remains within the auxiliary channel 75 and is therefore transferred along the vertical CCD register 56 with relatively high efficiency.

In the above description, it has been assumed that the CCD register 156 has one auxiliary channel 36 or 75 in the main channel 34 or 74, but it is also possible to provide 6 or more auxiliary channels in the main channel. . The CCD register 8o shown in FIG.
4. A main channel 82 extends along a surface 86 of 4. The first auxiliary channel 8 is located within the substrate 84 on the surface 8.
6, which is within the main channel 82. A second auxiliary channel 9o is located within the substrate 84 at the surface 86.
The first auxiliary channel extends within 8 days. Accordingly, the volume of the first auxiliary channel 88 is smaller than the volume of the main channel 82 and the volume of the second auxiliary channel 90 is smaller than the volume of the first auxiliary channel 88. The first auxiliary channel 8 has a higher concentration of conductive transducer than the main channel 82 and therefore has a higher conductivity than the main channel 82. The second auxiliary channel 90 has a higher concentration of conductive transducer than the first auxiliary channel 8 and therefore has a higher conductivity than the first auxiliary channel.

A layer 92 of silicon oxide is on the substrate surface 86 and extends over the channels 82, 88 and 90. A plurality of gates 94 (only two of which are shown) formed of a conductive material, such as conductive polycrystalline silicon, are provided on the silicon oxide layer 92. Gate 94 extends across channels 82.8B and 90, and
are arranged along these channels.

When a potential is applied to gate 94, channel 82
．． Potential wells are created at 88 and 90. The potential well formed during the first auxiliary channel 8 is the main channel 8
2, and also a second auxiliary channel 9
The potential wells formed in the first auxiliary channel 8 are deeper than the wells in the first auxiliary channel 8. Therefore, any charge that attempts to flow into these channels will first flow into the second auxiliary channel 90.
into the deepest potential well inside. As the charge increases, it flows out of the well in the second auxiliary channel 90 into the potential well in the first auxiliary channel 8 and then into the potential well in the main channel 82. Therefore, when the amount of charge is small, the charge is transferred to the second auxiliary channel 9
0 and when the amount of charge becomes intermediate, the first
is confined within the auxiliary channel 88, and furthermore, as the N load becomes larger, it enters the main channel 82. In this way, this CCD register 8o can efficiently transfer large charges, medium charges, and small charges.

In the OCD image seven sensor 1o of the type shown in Figure 1,
An auxiliary channel can be provided not only in the vertical CCD register 14 but also in the output CCD register 18.

However, if necessary, the auxiliary channel may be provided only in the output CCD register 18.

To demonstrate the improvements provided by this invention, an apparatus was constructed as shown below.

Example 1 An infrared charge-coupled device image sensor was fabricated in P-type nested crystalline silicon with a 32 x 63 array of detectors in which the conductive layer was formed of palladium silicide.

The output CCD register has a width of 110 μm and an N conductivity type (
The main channel region is 20 μm wide and of N conductivity type (implanted with arsenic of 15
An auxiliary channel area of 5XIO11 (amount of Il+ 2 implanted) at 0 KeV was provided. For very low signal levels, the transfer loss at 77°K is about 100% for a CCD without an auxiliary channel area. transfer loss of 10
It decreased from a value of ~10-2 to a value of about 2x10 per transfer.

Example ■ An infrared charge-coupled device image sensor was fabricated in a P-type single crystal silicon substrate with a 64×128 detector array. The output CCD register has a 15 μm wide N conductivity type (1
, 3Xlo12t: phosphorus implanted at a rate of m-2) and a main channel of N conductivity type (5X1011α-
The following table shows the transfer per transfer of this CCD output register compared to one similar to this register but with only the main channel area. Over losses, the present invention can be applied to an IR-IR detector in which the detectors are arranged in multiple columns, each column having a separate vertically embedded channel CCD register.
Although described as being implemented in a CCD image sensor, the invention can also be used in other types of OCD imagers. For example, the invention could be implemented in a line sensor imager where the detectors are arranged to form a line and only one CCD register is used. Such a line sensor imager is equipped with a transfer gate having the structure shown in FIGS. 2 and 3 between the detector line and the CCD register, but the CCD register has the structure shown in FIGS. There is no metal bus bar as shown in Figure 3, and the CCD
The gates of the CCD registers terminate along one edge of the CCD register.

Additionally, the invention can be used in recessed channels of visible CCD image sensors, especially large ones. in general,
'The C type image sensor includes a light sensing array called A register, a temporary storage array called B register and an output register called C register. For example, the A resistor includes a plurality of spaced apart parallel buried channel regions and a plurality of conductive gates arranged parallel to each other across and insulated from the channels. It is something. A 1B resistor has a plurality of spaced parallel buried channels that are an extension of the channels of the A resistor and a plurality of parallel conductive gates extending across the channels. In addition, the C register could be used to include a single buried channel extending along the edge of the channel of the B register. Upon entering the substrate portion, the photons are converted into electrons in the channels of the A register.

The electrons are transferred along the channel of the A register to the channel of the B register, and from there to the channel of the C register. The auxiliary channel according to the invention can be provided to the channel node of the C register or to all channels.

As described above, the present invention provides a CCD transfer device having a buried channel in which potential wells of different sizes are created such that the charge is confined in a channel volume of a size corresponding to the charge. It will be done. This allows charges to be transferred along the channel with high efficiency.

[Brief explanation of drawings]

Fig. 1 is a schematic diagram showing the structure of a typical R-OCD image sensor, and Fig. 2 is a schematic diagram showing the structure of a typical R-OCD image sensor.
Figure 3 is a plan view of one pixel of the image sensor, Figure 3 is a cross-sectional view along line 3-3 in Figure 2, Figure 4 is a diagram showing the potential profile of the channel of the CCD register in Figure 3, and Figure 5 is a diagram showing the potential profile of the channel of the CCD register in Figure 3. A plan view of one pixel of another type of R-CCD image sensor in which the invention is implemented, FIG. 6 is a line 5 of FIG.
7 is a cross-sectional view taken along line 7--7 of FIG. 5, and FIG. 8 is a cross-sectional view of yet another CCD register embodying the present invention. 12... Radiation detector, 14... Vertical CCD register, 18... Output register, 20... Board, 34...
・Main channel (first charge confinement means), 36...
- Auxiliary channel (second charge confinement means), B.・
... Gate.

Claims (2)

[Claims] (1) a substrate of a semiconductor material of a conductivity type having at least one major surface; a first means for confining charge extending along the major surface in the substrate; a second means extending along said first means and configured to confine a charge smaller than that which said first means can confine and to allow excess charge to spill into said first means; a plurality of conductive gates disposed on and insulated from the major surface of the substrate and along the first and second charge confinement means. (2) a substrate of a semiconductor material of one conductivity type, a plurality of radiation detectors arranged in a row along one surface of the substrate, and a CCD register extending along the row of the radiation detectors; a main channel region of a conductivity type opposite to that of the substrate extending along the one surface in the substrate; and a maximum charge confined in the main channel region by the main channel region; means for confining a charge smaller than the surface of the substrate; and means for transferring charge from the detector to the channel region, extending across the channel region and electrically insulated from the one surface of the substrate. A buried channel type CCD image sensor comprising: a CCD register including a gate;