GB2248341A - Infra-red radiation imaging device arrangements - Google Patents

Abstract

An imaging device arrangement comprises an array of infra-red radiation detector elements (10) and signal-processing circuitry including parallel charge-transfer lines (30). The detector elements (10) which may be photovoltaic diodes of cadmium mercury telluride are coupled to the charge-transfer lines (30) via input gates (61) at locations (2, 3) which are spaced along the lines (30) and which are associated with individual groups (a to z) of clocking electrodes (31 to 34) of the lines (30). A background-storage electrode (62) and a threshold gate (63) are present at each location (2, 3) to subtract a given background level (77) from the charge-signal and so to transfer only that portion (78) of the charge-signal remaining after subtraction. So as to minimize the pitch of the detector elements (10) and of the parallel lines (30) and maximize the charge-capacity of the parallel lines (30), the background-storage electrode (62) at each location (2, 3) is formed by at least part of at least one of the clocking electrodes (31 to 34) of the associated parallel line (30). The background storage well (72) below this clocking electrode or electrodes is coupled to the associated radiation detector element (10) by the input gate (61) and to a remaining-signal storage well (74) by the threshold gate (63). The threshold gate (63) and the remaining- signal storage electrode (64) may also be formed by at least part of at least one of the clocking electrodes (31 to 34). After collecting the remaining-signal charge (78) in the remaining-signal well (74) but before transferring it along the line (30), the subtracted charge (77) is drained away from the line (30), for example by draining along the line (30), or transverse to the lines (30), or via the detector elements (10). <IMAGE>

Description

"INFRA-RED RADIATION IP#AGING DEVICE ARRA!GElENTS" This invention relates to infra-red radiation imaging device arrangements comprising an array of infra-red radiation detector elements (for example, of cadmium mercury telluride) and signal processing circuitry (for example, in a silicon substrate) for providing an output signal representative of the radiation image incident on the array.

The paper entitled "Source-Coupled HgCdTe Staring llylzrid Focal Planes for Tactical Applications" by K. Chow, J. D. Blackwell, J. P. Rode, D. H. Seib and W. r. Lin in Volume 267, pages 12 to 17 of the Proceedings of the SPIE (Society of Photo-optical Instrumentation Engineers) Technical Symposium (1981), Los Angeles, describes an infra-red radiation imaging device arrangement comprising an array of infra-red radiation detector elements in which charge-signals are generated by incident infra-red radiation, and signal-processing circuitry for providing an output signal representative of the radiation image incident on the array.This circuitry includes parallel charge-transfer lines each comprising a row of clocking electrodes which are connected together in groups to permit charge-transfer along the line by the application of clock voltages to the clocking electrodes.

The radiation detector elements are coupled to the charge-transfer lines via input gates at locations which are spaced along the parallel charge-transfer lines and which are associated with individual groups of clocking electrodes. A background-storage electrode and a threshold gate are present at each of said locations for subtracting a given background level from the charge-signal at that location so as to transfer only that portion of the charge-signal which remains after said subtraction, the subtracted background charge being held in a background storage well below the background-storage electrode during the subtraction. The background subtraction is generally termed "charge-skimming".

This known device arrangement has an array of 32 x 32 photovoltaic detector elements formed in a layer of cadmium mercury telluride on a cadmium telluride substrate which is transparent to the infra-red radiation. The signal-processing circuitry is provided in a substrate of silicon, and has 32 parallel charge-coupled device (CCD) lines corresponding to the 32 rows of the detector element array.

These parallel CCD lines provide parallel inputs of the charge-signals derived from the 32 detector element rows into a further charge-coupled device which provides a serial output of each column in succession.

The detector elements are secured to the signal-processing substrate at the area of the parallel CCD lines and connected to the input gates by a corresponding array of input connections. The centre-tocentre pitch of the input connections (and also of the detector elements) is 68 micrometres.

The background-subtraction processing of the charge-signals in this device arrangement improves the effective dynamic range of the CCD. Thus, as is well-known, the charge representing useful information in the incident radiation image can be obscured by the accumulation of a high level of undesirable charge representing dark current leakage in the detector elements as well as high ambient radiation incident on the detector elements. The former results in charge being collected even in the absence of the incident radiation, while the latter occurs, especially in the 8 to 14 micrometre radiation waveband, when the ambient in a scene viewed by the imaging device contributes a high level of radiation so that the scene contrast is low and the amount of the signal which is of interest is only a very small part of the total radiation reaching the array.Both types of undesirable charge may be referred to as background charge. By means of the background storage electrode and threshold gate provided in known manner, at least a significant portion of this background charge is subtracted at the input connection and is not transferred into the parallel CCD lines. As illustrated in Figures 2 and 3 of the Chow et al paper this necessitates forming at each input location between the parallel CCD lines an input circuit comprising several electrodes and having an input gate, a background storage well, a threshold gate, a storage well for the remaining signal, and a background sink MOSFET to drain away the subtracted background charge from the background storage-well.

With such focal-plane imaging arrays it is desirable usually to collect and to integrate the charge from the detector elements for as long a time as is compatible with the read-out time for the CCD lines. This necessitates a large charge capacity for the background storage well and, to a lesser extent, for the remaining-signal storage well. however it is usually undesirable to increase this charge capacity by increasing the extent of the electrodes between the CCD lines, because this will increase the pitch of the detector elements and hence the area of the detector element array and/or restrict the area of the clocking electrodes of the CCD lines and hence the maximum signal charge capacity which can be clocked along these parallel CCD lines.In general, a smaller centre-to-centre pitch is desirable, for example a pitch of at most 50 micrometres, while also obtaining a large signal charge capacity for the CCD lines.

According to the present invention there is provided an infra-red radiation imaging device arrangement comprising an array of infra-red radiation detector elements in which charge-signals are generated by incident infra-red radiation, and signal-processing circuitry for providing an output signal representative of the radiation image incident on the array, said circuitry including parallel charge-transfer lines each comprising a row of clocking electrodes which are connected together in,groups to permit charge-transfer along the line by the application of clock voltages to the clocking electrodes, the radiation detector elements being coupled to the charge-transfer lines via input gates at locations which are spaced along said parallel charge-transfer lines and which are associated with individual groups of clocking electrodes, a background-storage electrode and a threshold gate being present at each of said locations for subtracting a given background level from the charge-signal at that location so as to transfer only that portion of the charge-signal remaining after said subtraction, the subtracted background charge being held in a background storage well below the background-storage electrode during the subtraction, characterized in that the background-storage electrode at each location is formed by at least part of at least one of the clocking electrodes of the associated parallel charge-transfer line, and in that the background-storage well below at least said one of the clocking electrodes is coupled to the associated radiation detector element by the input gate and to a remaining-signal storage well by the threshold gate, the subtracted background charge being drained away from the charge-transfer line after collecting the remaining-signal charge in the remaining-signal storage well but before transferring the remaining-signal charge along said charge-transfer line.

Such an imaging device arrangement in accordance with the present invention can have at each detector-element input location a high charge capacity for the background storage well formed below one or more of the clocking electrodes of the parallel charge-transfer lines while at the same time having a compact geometry not necessitating for background subtraction the provision of a large spacing between the parallel charge-transfer lines. Thus, the parallel charge-transfer lines can have a high charge-transfer capacity, and large packets of remaining-signal charge can be transferred along these parallel lines to a serial output charge-transfer line.Furthermore such an arrangement permits the background charge in the background storage well to be drained away from the charge-transfer line in a manner which is comparatively simple and which does not require any additional background sink MOSFET at the location of the input connections.

Thus, in a particularly advantageous arrangement in accordance with the present invention, the background charge is drained away transverse to the charge-transfer lines by providing transfer gates between the parallel charge-transfer lines for coupling together background storage wells of the adjacent charge-transfer lines.

Since such gates do not themselves serve as storage wells they can be provided in a very compact manner, requiring very little space between the adjacent charge-transfer lines.

In another form also in accordance with the invention, by means of the clock voltages applied to the clocking electrodes, the subtracted background charge is drained away along the charge-transfer lines before transferring the remaining-signal charge along said lines.

In this case the background charge may be drained in the same direction as the remaining-signal charge. Alternatively it may be drained in the opposite direction and towards the opposite end of the lines from the transport direction for the remaining-signal charge, and a gated-drain may be provided at this opposite end of each of the parallel chargetransfer lines.

It is also possible to drain the background charge via the radiation detector elements by switching the voltages applied to the radiation detector elements, and to electrodes providing the input gates.

Such an arrangement is described and claimed in our simultaneously-filed patent application (Our reference: PHB 32901) which is also entitled "Infra-red Radiation Imaging Device Arrangements" This particularly advantageous mode of draining does not require any additional circuit component integrated into the signal processing substrate at each input location while nonetheless draining away the background charge at each input location so that the background draining can be performed in a shorter time than by draining via the charge-transfer lines.

In order to obtain a large charge capacity for the background storage well it is preferable for the background storage electrode for each input connection to be formed by at least a part of at least two clocking electrodes. In this case it may be necessary to form the remaining-signal storage well either below a signal storage electrode which is located at one side of at least part of one clocking electrode or below a separately clockable part of one clocking electrode. Thus one of the clocking electrodes may be divided into three separately clockable parts of which (during the charge-skimming operation) the first forms part of the background storage electrode, the second provides the threshold gate, and the third provides a signal storage electrode below which the remaining-signal storage well can be formed.When the charge-skimming operation is complete, the three parts of the electrode can be clocked to the same voltage so as to behave as a single electrode during the charge transfer operation.

It is also possible to form the background storage well below one clocking electrode, the remaining-signal storage well below another clocking electrode and to use an intermediate clocking electrode of the charge-transfer line to provide the threshold gate. An advantage of such an arrangement is that a complicated clocking electrode structure can be avoided for the parallel charge-transfer lines.

The signal-processing circuitry including the parallel chargetransfer lines may be provided in a separate substrate (for example of silicon) to which the radiation detector elements (for example of cadmium mercury telluride) are secured at the area which includes said parallel charge-transfer lines, the substrate having an array of input connections which corresponds to the array of radiation detector elements and which connects the detector elements to the input gates at each of said locations. A particularly compact geometry can be obtained in this case, particularly when at each of the inputconnection locations one of the clocking electrodes has a recess at one side, and the input connection and the input gate are located in said recess.

Embodiments of the present invention will now be described, by way of example, with reference to the accompanying diagrammatic drawings, in which: Figure 1 is a partial cross-sectional view and partial perspective view of part of an infra-red radiation imaging device of an arrangement in accordance with the invention; Figure 2 is a schematic representation of such a device arrangement in accordance with the invention; Figure 3a is a simplified schematic cross-section through one of the parallel CCD lines of the device arrangement of Figure 2, additionally showing the potential well profile during charge integration and background subtraction; Figures 3b to 3e show potential well profiles in the cross-section of Figure 3a at subsequent stages in the operating sequence; ; Figure 4 is a plan view of part of one of the parallel CCD lines of such a device arrangement in accordance with the invention, having a side-located remaining-signal storage well, and additionally illustrates the signal-charge integration and background subtraction stage in its operation; Figure 5 is a plan view of part of one of the parallel CCD lines of another device arrangement in accordance with the invention, having a remaining-signal storage well provided by a separately clockable part of one of the clocking electrodes of the CCD line and additionally illustrates the signal-charge integration and background subtraction stage of its operation;; Figure 6 is a plan view of the part of Figure 5, but illustrating the clocking of charge along the CCD line, and Figure 7 is a plan view of part of two adjacent parallel CCD lines having intermediate transfer gates for draining away the background charge transverse to the parallel CCD lines.

It should be noted that all the Figures are only diagrammatic and not drawn to scale, and that dimensions of some parts have been strongly exaggerated both for clarity and convenience in the drawing.

The same reference designations as used in one embodiment are generally used to refer to corresponding or similar parts in the other embodiments.

The infra-red radiation imaging device arrangement of Figures 1 and 2 comprises an array of infra-red radiation detector elements 10 in which charge-signals are generated by incident infra-red radiation 25, and a substrate 1 comprising signal-processing circuitry which provides an output signal representative of the radiation image 25 incident on the array.This substrate circuitry includes parallel charge-transfer lines 30 each of which comprises a row of clocking electrodes 31 to 34 which are connected in groups a to z (in Figure 2) as a charge-coupled device (for example groups of four electrodes for a four-phase charge-coupled device) to permit charge-transfer along the line by the application of clock voltages (for example ~(l), #(2), #(3) and #(4) for a four-phase CCD) to these clocking electrodes. The cross-section of Figure 1 is taken across the width of two complete lines 30 and part of one line 30, which lines extend parallel to each other in the perspective direction of the drawing of Figure 1. In this cross-section across the lines 30, only two of the clocking electrodes are shown, namely electrodes 32 and 33.

In the case of the arrangement of Figure 7, only the clocking electrode 32 would be seen in Figure 1.

The radiation detector elements 10 are secured to the circuit substrate 1 at the area which includes these parallel charge-transfer lines 30. At locations which are associated with individual groups a to z of these clocking electrodes 31 to 34 and which are spaced along the length of the charge-transfer lines 30 (i.e. in the perspective direction of the drawing of Figure 1) there is an array of input connections 2,3 which corresponds to the array of detector elements 10.

The detector elements 10 are connected to the charge-transfer lines 30 via these input connections 2,3 and input gates 61. The cross-section of Figure 1 is taken through two such input connections 2,3 which as illustrated in the drawing comprise a metal electrode 3 contacting a highly doped (N+) semiconductor contact region 2.

Apart from its signal-processing circuitry of substrate 1 which as will be described later is constructed and organized to provide a device arrangement in accordance with the present invention, the particular device structure illustrated in Figure 1 is similar to that described in our co-pending U.K. Patent Application 8204158 (Our reference: PIIB 32767). Thus, the detector elements 10 are photovoltaic diodes formed in a common body 11 of infra-red sensitive material, for example cadmium mercury telluride. The bulk 14 of the body 11 is of one conductivity type, and each detector element 10 comprises a region 13 of opposite conductivity type which forms with the bulk 14 a p-n junction 12 for detecting charge-carriers generated in the infra-red sensitive material by the infra-red radiation 25.

The material composition may be chosen to respond to radiation 25 in, for example, the 8 to 14 micrometre waveband or the 3 to 5 micrometre waveband. These photovoltaic detector diodes 10 have electrode metallization 23 and 24 which respectively contact the regions 13 and the bulk 14. Passivating insulating layers 16 and 17 are present on the opposite major surfaces of the detector element body 11.

The detector element body 11 is secured to the circuit substrate 1 which is typically monocrystalline silicon by a layer of electrically insulating adhesive 18. An array of apertures 20 extends through the thickness of the body 11 and also through the adhesive layer to reach the input-connection electrodes 3 exposed at the upper major surface of the substrate 1. Each of the apertures 20 is associated with a detector diode 10, and the centre-to-centre spacing of these apertures 20 in the device of Figure 1 may be, for example, 50 micrometres.

The detector-diode regions 13 extend through the thickness of the body 11 at the side-walls of the apertures 20 and are electrically connected to the input-connection electrodes 3 of the parallel CCD lines 30 of the substrate 1 by the metallization 23 which is located in these apertures 20. The metallization 24 nay contact the bulk 14 around all of the outer side-walls of the body 11 and extend over these side-walls to contact a metallization track 4 exposed at the upper major surface of the substrate 1. The track 4 provides a common terminal for all the detector diodes 10 of the array and is connected to a constant voltage source 50, or it may instead be connected to a voltage pulse generator 50 the function of which will be described subsequently.For further details of the construction and the manufacturing process which may be employed for the device of Figure 1 reference is invited to said co-pending U.K. patent application 8204158.

As illustrated in Figure 2, the signal-processing circuitry in the substrate 1 comprises a parallel-to-serial charge-coupled device format in which the parallel CCD lines 30 correspond to rows of the detector-element array and provide parallel inputs of the charge-signals from these rows into a further charge-coupled device 40 which provides a serial output O/P of each column in succession.

In the case of an array of 32 x 32 detector diodes 10 there are 32 parallel CCD lines 30 and 32 groups a to z of the clocking electrodes 31 to 34 along each CCD line 30. Similarly there are 32 input connections 2,3 from the detector diodes 10, spaced along each line 30. For convenience ard clarity, Figure 2 shows only some of the detector diodes 10, groups a to z, and input connections 2,3, and it also does not show the full extent of the clocking electrodes 31 to 34 across the full width of the CCD lines 30.

Charge is clocked along the charge-transfer lines 30 by four-phase CCD action with clock voltages 0(l), #(2), #(3) and #(4) applied to the clocking electrodes 31 to 34 from a pulse generator 51. The charge transferred along the lines 30 is introduced into a potential well below one clocking electrode 42 of the serial output CCD line 40.

This CCD line 40 may also be of the four-phase type, and the charge is clocked along it by clocking voltages 0'(1), #'(2), #'(3) and 0'(4) applied to its clocking electrodes 41 to 44 from a pulse generator 52.

The output signal can be detected in known manner using an output insulated-gate field-effect transistor 48 separated from the final clocking electrode 44 by an output gate 45 connected to a pulse generator 53. After reading the output signal with the transistor 48 the output potential is reset in known manner via a further insulated-gate field-effect transistor 49 connected to a pulse generator 54. Charge may be transferred directly from below the last clocking electrode 34 of each line 30 to below the input clocking electrodes 42 of the line 40, or this charge transfer nay be controlled in known manner by clocking via an intermediate buffer with an input gate and an output gate.

All the pulse generators (50), 51, 52, 53 and 54 and the transistors 48 and 49 can be formed in the substrate 1 using known technology, the pulse generators being located in peripheral areas of the substrate 1 outside the area accommodating the charge-transfer lines 30 and 40.

The charge-transfer lines 30 and 40 may be constructed as a surface-channel CCD. However preferably the lines 30 and 40 are formed as a buried channel or so-called "bulk channel" CCD for greater charge transfer efficiency, speed and charge handling capacity. Figure 1 illustrates such a buried channel device in which the charge-transfer line comprises a fully-depleted n-type channel region 26 in which the potential wells are formed below the clocking electrodes 31 to 34.

The n-type channel region 26 is provided in a low-doped p-type silicon substrate. The configuration of the n-type channel region 26 in the substrate 1 corresponds to the parallel-to-series format of the lines 30 and 40. A more highly-doped p-type isolation region extends around the periphery of this n-type region 26 in the p-type substrate. The clocking electrodes 31 to 34 and 41 to 44 as well as other electrodes providing gates and storage electrodes are typically formed of doped polycrystalline-silicon and are insulated from the silicon substrate surface by an insulating dielectric layer, typically of silicon dioxide.

These electrodes are separated from each other and for the most part are also covered with electrically insulating material such as silicon dioxide. The electrically insulating material on the silicon substrate surface is designated by reference 5 in Figure 1. In general it is desirable to slightly overlap adjacent clocking electrodes of the charge-coupled device lines, and this can be achieved in a conventional manner by forming alternate adjacent electrodes (for example the electrodes 31,33 and 42,44) in a second depcsition step after forming an insulating layer on the previously-deposited other clocking electrodes (for example the electrodes 32,34 and 41,43). However, such an overlap is not illustrated in the drawings for the sake of clarity in the drawings.

In the device arrangement of Figures 1 and 2, not all the chargesignal developed at the input connections 2,3 by the detector diodes 10 is transferred along the parallel CCD lines 30. Thus, the charge-signal from the detector diodes 10 contains a high level of background charge as a result of both dark current leakage in the detector diodes and low thermal contrast in the scene being viewed. At least a significant portion of this background charge is subtracted at each input connection by using a background-subtraction scheme in accordance with the present invention.Specific examples of particular arrangements of an input gate 61, a background-storage electrode 62, a threshold gate 63, and a remaining-signal storage electrode 64 for implementing such background-subtraction in accordance with the invention are illustrated in Figure 4, Figures 5 and 6 and Figure 7.

However, the general principles and operating sequence for such background-subtraction will first be described with reference to Figures 3a to 3e. For the sake of clarity in the drawing the arrangement of the threshold gate 63 and remaining-signal storage electrode 64 at each input-connection location associated with the individual electrode groups a to z is not illustrated in Figure 2. Furthermore as will be described subsequently with reference to Figure 7, there does not need to be any separate gate 63, electrode 64 and pulse generator 57.

Figure 3a is a simplified schematic cross-section through one of the parallel CCD lines 30, showing an input connection 2,3 at one location along the line 30, and also showing a background-storage electrode 62, an input gate 61 between the input connection 2,3 and the background storage electrode 62, and a threshold gate 63 between the background storage electrode 62 and a signal storage electrode 64.

The arrow 75 illustrates the collection and integration of the charge-signal from the detector diode 10 at that location. During this stage the detector diode 10 is maintained in an overall zero bias condition by the voltages applied to the common connection 4and the input gate 61; in a typical example of the n-channel buried CCD arrangement of Figure 1, the detector-diode connection 4 may be maintained at about +5 volts by the constant voltage source 50 or the quiescent voltage level of the pulse generator 50, and a higher voltage level (for example about +8 volts) is applied to the input gate 61 from the generator 56 to allow for the threshold voltage of the gate 61. The radiation-generated photocurrent then flows via the input connection 2,3 into the storage wells as indicated by arrow 75.

The background-storage electrode 62 and threshold gate 63 serve for subtracting a given background level from the charge-signal at that input-connection 2,3 so as to transfer only that portion of the charge-signal remaining after said subtraction. Such substrtction is also known as charge-signal skimming. The subtracted background charge is held in a potential well 72 below the background storage electrode 62 during the skimming, whereas the remaining signal charge which is "skimmed" from the background is collected in a potential well 74 below the remaining-signal storage electrode 64. In Figure 3a the arrow 76 illustrates the charge skimming. The charge levels in the background storage well 72 and the remaining-signal storage well 74 are represented by lines 77 and 78 respectively.

In accordance with the present invention, the background-storage electrode 62 at each input-connection location along the parallel CCD lines 30 is formed by at least part of at least one of the clocking electrodes 32,33,34 of the associated charge-transfer line 30, as indicated in Figure 3a. The depth of the background storage well 72 below the at least one clocking electrode 32,33,34 is controlled by the clock voltage #(2), #(3), #(4) applied to that electrode by the pulse generator 51 so that when two or more clocking electrodes 32, 33,34 are used as the background-storage electrode their voltages #(2), ~(3), #(4) are clocked together during the background storage and skimming stage to form a common potential well 72 below these two or more electrodes 32,33,34. The background storage well 72 below the at least one clocking electrode 32,33,34 is coupled to the input connection 2,3 by the input gate 61 and to the remaining-signal storage well 74 by the threshold gate 63. Although not illustrated in Figure 3a, the threshold gate 63 and remaining-signal storage electrode 64 may also be formed by at least a separately-clockable part of at least one clocking electrode (32,33,34) of the CCD-line 30 as will be described in detail later.

During the charge-signal integration and skimming stage illustrated in Figure 3a, the potential applied to the input gate 61 by a pulse generator 56 (see Figure 2) permits charge carriers injected from the radiation detector diode 10 to flow to the background storage well 72 as indicated by the arrow 75. The amount of charge held in this well 72 (and hence the background level 77 which is subtracted from the charge-signal) is determined by the clock voltage #(2), #(3), #(4) applied to the clocking electrode(s) 32,33,34 forming the background storage electrode 62 and by the potential barrier which is formed between the wells 72 and 74 by the voltage applied to the threshold gate 63 from a pulse generator (57 in Figure 2).A voltage pulse is also applied to the electrode 64 to control the depth of the storage well 74 for the skimmed charge-signal 78. Adjacent backgroundstorage wells 72 along the CCD lines 30 are isolated from each other by potential barriers which are formed below at least one clocking electrode (31, in the example given) of each group by means of the voltage level 0(1) applied to that electrode 31 by the pulse generator 51 during this stage in the operating sequence.

At the end of the charge-signal integration period the voltage applied to the threshold gate 63 by its pulse generator (57) is reduced to increase the underlying potential barrier so as to isolate the charge 78 in the well 74 from the subtracted background charge 77 in the well 72, as illustrated in Figure 3b. The subtracted background charge 77 is then drained away from the CCD line 30 before the remaining-signal charge 78 is to be transferred along the CCD line 30. This may be effected by increasing the voltage level ~(1) applied to the clocking electrodes 31 so as to merge together the background storage wells 72 to form a single well along the length of each CCD line 30 along which the background charge can diffuse to a drain.Alternatively different clocked voltage levels 0(1) to #(4) may be applied. to the electrodes 31 to 34 to clock the subtracted background charge 77 along the lines 30 by CCD action. These modes of draining cannot be used when the isolated signal storage well 74 interrupts the transfer path along the line 30; such an interruption occurs when the whole of one of the clocking electrodes 31,33,34 forms the remaining-signal storage electrode 64, an example of which is given in Figure 7, in which a different mode of draining is used.

When the background charge is drained away along the lines 30, it may be transported to the serial output CCD line 40. However it may be drained in the opposite direction; for this purpose a highly-doped n-type drain region connected to a high positive bias voltage may be provided in the channel region 26 at the end of each line 30 remote from the line 40, an output gate connected to a pulse generator being present between this drain region and the first clocking electrode 31 of the CCD lines 30. However, the background charge 77 may be drained away from the CCD lines 30 in a different manner in the Figure 2 structure, for example transverse to the CCD lines 30 as in Figure 7.

Figure 3c illustrates a particularly advantageous mode of draining away the subtracted background charge 77 as described and claimed in said simultaneously-filed patent application. In this case draining is effected'by clocking the voltage level applied to the common electrical connection 4 of the radiation detector diodes 10 by means of the pulse generator 50. The voltage level applied to the input gate 61 is similarly clocked by means of the pulse generator 56. The connection 4 is clocked from its quiescent potential level to a high value of opposite sign from that of the charge 77 to be drained, so forward-biasing the diodes 10; thus, in a typical example of the buried-channel device of Figure 1 where the charge-carriers 77 are electrons, the connection 4 is switched to a high positive potential, for example +10 volts.

The input gate 61 is similarly clocked to a high potential. The result illustrated by arrow 79 in Figure 3c is that the subtracted charge 77 then flows from the background storage well 72 to the pulse generator 50 via the input connection 2,3, the associated forward-biased detector diode 10 and the common detector-diode connection 4. The voltage levels of the connection 4 and input gate 61 are then reduced, the connection 4 being clocked to its quiescent value (+5 volts in the example given above).

Having drained the background charge 77 from the CCD lines 30, the remaining signal-charge 78 can now be clocked along the CCD lines 30 to the serial output CCD line 40. For this purpose, the voltage applied to the input gate 61 by the generator 56 is such as to isolate the input-connection 2,3 from CCD line 30, and separate voltage levels are then applied to the clocking electrodes 31 to 34 by the pulse generator 51. Figure 3d illustrates the situation in which a potential well 71 is formed below one clocking electrode (for example, 34) of each group, these wells 71 being separated along the CCD lines 30 by potential barriers formed below the other clocking electrodes (for example, 31 to 33).The threshcld gate 63 is then opened and the potential well 74 below the electrode 64 is reduced by the voltages applied thereto (for example, from the pulse generator 57) so as to transfer the remaining signal-charge 78 into this well 71. By means of the clock voltages ~(1), #(2), ~(3), #(4) applied to the electrodes 31 to 34 this packet of charge 78 is then transferred to a well below the next clocking electrode (for example electrode 31) and so progressively transferred along the CCD line 30 to the serial output line 4C by normal four-phase CCD action.

Figure 4 illustrates one possible layout of electrodes 31 to 34 at each input-connection location. In this example the clocking electrodes 32, 33 and 34 are all used together to form the background storage electrode 62, and the input connection 2,3 and input gate 61 are located in a recess at one side of the clocking electrode 33. Also in this example the remaining-signal storage electrode 63 and threshold gate 64 are formed by electrodes which are located at one side of the clocking electrode 34. Although not shown in Figure 4 for the sake of clarity in the drawing there will generally be a slight overlap between the input connection region 2 and the input gate 61, between the input gate 61 and the clocking electrode 33, between the clocking electrodes 33 and 34, 34 and 31, 31 and 32, and 32 and 33 respectively, between the clocking electrode 34 and the threshold gate 64, and between the threshold gate 64 and the signal storage electrode 63.

During the charge integration and background subtraction, charge will be collected in potential wells below the hatched electrodes in Figure 4, namely the background charge 77 below the electrodes 32, 33 and 34 and the skimmed signal charge 78 below the electrode 64.

Figure 5 illustrates a modification of the Figure 4 arrangement, showing another possible layout of electrodes 31 to 34 at each input-connection location. In this example the clocking electrode 34 is divided into three separately clockable parts, of which the main part 34a forms part of the background storage electrode 62 (together with the electrodes 32 and 33), and the second part 34b provides the threshold gate 63, and the third part 34c provides the skimmed-signal storage electrode 64. During the charge integration and background subtraction stage which is illustrated in Figure 5, these three parts 34a, 34b and 34c have different voltage levels applied from the generators 51 and 57 in accordance with their background subtraction function.The background charge 77 is now collected below the hatched electrodes 32, 33 and 34a and the skimmed signal charge 78 is collected below the hatched electrode part 34c. In addition to the overlaps mentioned in connection with the Figure 4 layout there will also generally be an overlap between the electrode parts 34a and 34b, and the electrode parts 34b and 34c.

After draining the background charge 77 from the CCD lines 30, the skimmed signal charge 78 is clocked along the lines 30 by normal four-phase CCD action. Figure 6 illustrates the initial stage in which the skimmed signal charge 78 is held in a single potential well extending below the hatched electrode parts 34a, 34b and 34c.

When using the CCD lines for clocking this charge 78 to the output CCD 40 the same clocked voltage levels #(4) are applied to the electrode parts 34b and 34c by the pulse generator 57 as are applied to the electrode part 34a by the pulse generator 51. As a result of this increased area of the electrode 34, a higher charge can be transported along the lines 30.

For the arrangements of both Figure 4 and Figures 5 and 6 the background charge 77 may be drained either via the detector elements 1C or along the CCD lines 30. Figure 7 illustrates another possibility in which transfer gates 90 are located between the parallel CCD lines 30 for coupling together background storage wells 72 of adjacent CCD lines 30 to drain away the background charge transverse to the lines 30. The lines 30 of Figure 7 are still four-phase CCD lines, but in this example only the clocking electrode 32 is used as the background storage electrode 62. The clocking electrode 33 is used as the threshold gate 63, and the clocking electrode 34 is used as the skimmed-signal storage electrode 64, while the electrode 31 serves to isolate the background storage well under electrode 32 from the preceding skimmed-signal well under electrode 34.All these functions are performed by choosing appropriate clocked voltage levels ~(1), #(2), #(3) and #(4) applied by the pulse generator 51 during the charge integration and background subtraction stage. Thus there is no separate pulse generator 57.

In the Figure 7 layout, the background charge 77 is held in a potential well below the hatched electrode 32 while the skimmed signal charge 78 is collected below the hatched electrode 34. At this stage the background storage wells below adjacent electrodes 32 of adjacent parallel CCD lines 30 are isolated from each other by potential barriers formed by appropriately biasing the transfer electrodes 90 with a pulse generator 59. Below each transfer electrode 90 there is a gap in the channel isolation region 27 (illustrated by a broken outline) so that the channel region 26 extends between the adjacent lines 30 at this area below the electrodes 90.

At the end of the charge integration and background subtraction stage, the voltage applied to the transfer electrodes 90 by the generator 59 is increased so as to provide no potential barrier between the adjacent background storage wells of adjacent CCD lines 30.

The background charge 77 can then be drained away across the CCD lines along a single potential well below the electrodes 33 and 90, for example by diffusion to highly-doped n-type drain regions 91 which are biased to a high positive potential and which are located at the outside of the outermost parallel CCD line 30. Compared with Figures 4 and 5, the arrangement of Figure 7 has the advantage that because the clocking electrodes 32 to 34 are used to provide the charge-skimming and remaining-signal storage (as well as the background storage), no extra electrodes 63 and 64 are needed, nor any extra pulse generator 57. Only a small extra gate electrode 90 is provided in the Figure 7 arrangement for draining the background; thus a high proportion of the pixel area can be used to accommodate the signal storage and transfer electrodes 31 to 34.However in a modified form of the Figure 7 structure this extra gate electrode 90 and the associated gaps in channel isolation 27 are omitted, and the subtracted background charge 77 is drained away via the detectcr elements 10 as described with reference to Figure 3c. Such a modified form of the Figure 7 structure is described as Figure 5 in said simultaneously filed patent application.

It will be evident that many other modifications are possible within the scope of the present invention. Thus, instead of the cedmium mercury telluride photovoltaic infra-red detector diodes 10 being of the form shown in Figure 1, they may be formed in an epitaxial layer of cadmium mercury telluride on a cadmium telluride substrate with their individual electrode connections 23 formed by indium or other metal bump connections as in the device arrangement illustrated in Figure 1 of the previously-mentioned Chow et al paper.

It is also possible for each photovoltaic infra-red detector diode 10 to be formed in a separate body of cadmium mercury telluride mounted on the signal-processing circuit substrate 1. Such arrangements are illustrated 'in Figure 10 of the article "CCD Read-out of Infra-red Hybrid Focal-Plane Arrays" on pages 175 to 188 of I.E.E.E. Transactions on Electron Devices, Vol. ED-27, No. 1, January 1980 to which reference is made in our co-pending U.K. patent application 8204158 (Our reference PHB 32767). In both cases all the detector elements 10 of the array would be provided with a common connection which is connected to the constant voltage source 50 or pulse generator 50. Other infra-red sensitive materials, for example lead tin telluride and indium antimonide may be used for the detector elements 10.

It is also possible to form the detector elements 10 of silicon for operation in the near infra-red radiation wavebands, and the detector elements 10 may even be formed by dopant diffusion or implantation in the signal-processing substrate 1 at the location of the regions 2.

However such a construction has the disadvantage of using separate fractions of the pixel area for radiation detection and charge storage and transfer, and is not so practical for long wavelergth infra-red detectors, for example in the 8 to 14 micrometre band.

Instead of charge-coupled devices, bucket brigade devices may be used for the charge-transfer lines.

Claims (10)

CLAIMS:

1. An infra-red radiation imaging device arrangement comprising an array of infra-red radiation detector elements in which chargesignals are generated by incident infra-red radiation, and signalprocessing circuitry for providing an output signal representative of the radiation image incident on the array, said circuitry including parallel charge-transfer lines each comprising a row of clocking electrodes which are connected together in groups to permit charge-transfer along the line by the application of clock voltages to the clocking electrodes, the radiation detector elements being coupled to the charge-transfer lines via input gates at locations which are spaced along said parallel charge-transfer lines and which are associated with individual groups of clocking electrodes, a background-storage electrode and a threshold gate being present at each of said locations for subtracting a given background level from the charge-signal at that location so as to transfer only that portion of the charge-signal remaining after said subtraction, the subtracted background charge being held in a background storage well below the background-storage electrode during the subtraction, characterized in that the background-storage electrode at each location is formed by at least part of at least one of the clocking electrodes of the associated parallel charge-transfer line, and in that the backgroundstorage well below at least said one of the clocking electrodes is coupled to the associated radiation detector element by the input gate and to a remainingsignal storage well by the threshold gate, the subtracted background charge being drained away from the charge-transfer line after collecting the remaining-signal charge in the remaining-signal storage well but before transferring the remaining-signal charge along said charge-transfer line.

2. An imaging device arrangement as claimed in Claim 1, further characterized in that transfer gates are located between the parallel charge-transfer lines for coupling together background storage wells of the adjacent charge-transfer lines to drain away the background charge transverse to the charge-transfer lines.

3. An imaging device arrangement as claimed in Claim 1, further characterized in that by means of the clock voltages applied to the clocking electrodes, the subtracted background charge is drained away along the charge-transfer lines before transferring the remaining-signal charge along said lines.

4. An imaging device arrangement as claimed in anyone of the preceding claims, further characterized in that the background storage electrode for each detector element is formed by at least a part of at least two clocking electrodes below which the background storage well is formed by the clock voltages.

5. An imaging device arrangement as claimed in Claim 4, further characterized in that one of the clocking electrodes is divided into three separately clockable parts of which the first forms part of the background storage electrode, the second provides the threshold gate, and the third provides a signal storage electrode below which the remaining-signal storage well is formed.

6. An imaging device arrangement as claimed in anyone of Claims 1 to 4, further characterized in that the remaining-signal storage well is present below a signal storage electrode which is located at one side of at least part of one of the clocking electrodes.

7. An imaging device arrangement as claimed in anyone of the preceding Claims, further characterized in that the signal-processing circuitry including the parallel charge-transfer lines is provided in a substrate to which the radiation detector elements are secured at the area which includes said parallel charge-transfer lines, the substrate having an array of input connections which corresponds to the array of radiation detector elements and which connects the detector elements to the input gates at each of said locations.

8. An imaging device arrangement as claimed in Claim 7, further characterized in that at each of said locations one of the clocking electrodes has a recess at one side, and the input connection and the input gate are located in said recess.

9. An imaging device arrangement as claimed in Claim 7 or Claim 8, further characterized in that the radiation detector elements are photovoltaic diodes of cadmium mercury telluride.

10. An infra-red radiation imaging device arrangement substantially as described with reference to Figure 1, Figure 2, Figures 3a, 3b, 3d and 3e, Figure 4, Figures 5 and 6, or Figure 7 of the accompanying drawings.