JPH0622249B2 - Embedded channel charge coupled device - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a channel structure of a buried channel type charge-coupled device (CCD) with improved charge transfer efficiency at low temperature, and more particularly to an infrared CCD (IR-CCD). The present invention relates to a CCD channel structure useful for an image sensor.

[Background of the Invention]

An embedded channel CCD is a solid state transfer device for charge transfer. Generally, this type of device comprises a body of semiconductor material, for example single crystal silicon,
The body has a channel in the body in the form of a region of opposite conductivity type to the body and extending along the surface of the body. A plurality of conductive gates extend insulated from and extend across the channel and are located along the channel. By sequentially applying an appropriate potential to these gates, the charge in the channel is transferred along the channel. Such a CCD transfer device is provided, for example, with a plurality of radiation detectors arranged to form an example and along each row of the radiation detectors, and each detector of the row is connected. It is used in an image sensor with another transfer CCD register. The charge produced in the detector by the radiation received by the detector is transferred to the CCD connected to it, which then extends along one end of this transfer CCD register and is connected to these registers. It is transferred along this transfer CCD toward the output CCD register that is present. This output CCD register transfers the charge to the output circuit. An example of an image sensor using a shutter barrier detector for infrared detection is SPIE, Volume 344, "Infrared Sensor Technology," 1982.
, Page 66-77, W. F. Kozonotsky et al. “Design and Performance of 64 × 128 Element PtSi Sc (IRCCD) Focal Plane Array”
hottky-Barrier Infrared Charge-Coupled Device (IRCC
D) Focal Plane Array) ".

One problem that arises with the use of CCD transfer devices is the poor charge transfer efficiency of the device. The inefficiency of charge transfer is related to the charge transfer loss, which is proportional to the volume of the embedded channel in the embedded channel type CCD. The charge transfer inefficiency of CCDs is particularly problematic for infrared CCD image sensors that require low operating temperatures in the 77-130 ° K range. This is because in this case, the charge transfer efficiency is further reduced at the low operating temperature. This is a particular problem when operating the image sensor at low signal levels that produce signal charges that do not meet the CCD channels.

[Outline of Invention]

The buried channel charge-coupled device according to the invention comprises a substrate of semiconductor material having one conductivity type, the substrate having at least one major surface. First means for confining charges are provided along the main surface in the substrate. Further, in the substrate, along the main surface, a smaller amount of charges than those confined by the first means is confined, and the excess charges are
A second means is provided which allows it to overflow into the means. A plurality of conductive gates are provided on the main surface of the substrate along the confinement means.

[Explanation of Examples]

Referring first to FIG. 1, there is shown a schematic block diagram of a typical IR-CCD sensor array, generally designated 10. The sensor array 10 comprises a plurality of IR detectors 12 arranged so as to form vertical rows parallel to each other. Vertical column CCD register 1 along each column of detector 12
4 extends to which the detectors 12 in adjacent vertical columns are connected. Input CCD register 16 is vertical column
Each vertical column CCD extends along one end of the CCD register 14.
Each of the registers 14 is connected to it. Further, an output CCD register 18 extends along the other end of the vertical column CCD register 14 and is connected to each column CCD register 14.

2 and 3 show in detail the structure of one pixel of one type of IR-CCD image sensor embodying the present invention. This pixel contains one detector 12 and a portion of its associated vertical column CCD register 14. The sensor array 10 is formed in and on a P-conductivity-type single crystal silicon substrate having a pair of front and back main surfaces 22 and 24. The detector 12 is a thin layer 26 of a conductive material, such as a silicide of palladium or platinum, with a surface 24 within the substrate 20.
It is formed along with. This conductive layer 26 forms a shutter barrier junction with the substrate 20. A protective ring 28 extends from the surface 24 into the substrate 20 in the form of a region of N conductivity type, surrounding the edge of the conductive layer 26. Surrounding the guard ring 28 is a channel stop 30, which is a region of P conductivity type extending from the surface 24 into the substrate 20. At the edge of the conductive layer 26 adjacent to the vertical CCD register 14, a conductive layer 32 of N + conductivity type is surfaced.
Extending from 24 into the substrate 20 and partially overlapping the conductive layer 26,
I'm in contact with this.

The vertical CCD register 14 comprises a main buried channel 34 in the form of an N-type region of predetermined width consisting of an elongated portion extending in the substrate 20 along the surface 24 parallel to the rows of detectors 12. Within this primary buried channel 34 is a secondary buried channel 36, which is a more highly doped N-type region extending along surface 24 within substrate 20. The auxiliary embedded channel has a higher concentration of conductive converter than the main channel 34 so that it has higher conductivity than the main channel 34. Further, the auxiliary channel 36 is separated from both sides of the main channel and substantially in the center thereof, and has a width smaller than the width of the main channel, so that the entire auxiliary channel 34 is accommodated in the main channel 34. Has a smaller volume than. A thin layer 38 of silicon oxide covers the entire surface 24 of the substrate 20. A plurality of gates 40 are provided side by side on the silicon oxide layer 38 and extend across channels 34 and 36. These gates 40
For example, a layer of conductive material such as conductive polycrystalline silicon. A layer 42 of silicon oxide is provided on the gate 40. Four metal bus lines 44, typically formed of aluminum, extend over the silicon oxide layer 42 in a direction transverse to the gate 40 and parallel to one another. Each bus wire 44 extends through an opening in the silicon oxide layer 42 to form a gate
In contact with each of the 40 different ones. Each bus line 44 is connected to every third gate 40.

A transfer gate 46 is placed on the silicon oxide layer 38 and the detector 12
And the vertical CCD register 14 extends. The transfer gate 46 is a layer of conductive material, such as doped polycrystalline silicon. Transfer gate 46 overlaps a portion of conductive region 32 and an edge of main buried channel 34. A layer 48 of silicon oxide extends over the transfer gate 46. One of the gates 40 of the vertical CCD register 14 is aligned with the conductive region 32 of the detector 12. This makes it possible to transfer charges from the detector 12 to the vertical CCD register 14. A thin layer 50 of metal, such as aluminum, overlies each of the conductive layers 26 of the detector 12 and a silicon oxide layer 38.
It is provided above. The metal layer 50 acts as a mirror that reflects the radiation passing through the conductive layer 26 back to the conductive layer.

In operation of the sensor array 10, radiation coming from the surface 22 through the substrate 20 is converted by the detector 12 into electric charge.
When an appropriate potential is applied to transfer gate 46, the charge in conductive layer 26 of detector 12 will channel 34 of vertical CCD register 14.
And transferred to 36. When an appropriate potential is sequentially applied to the great 40, the charges in the channels 34 and 36 are transferred to the output CCD register along the vertical CCD register 14.

Applying a potential to gate 40 creates a potential well in channels 34 and 36. Auxiliary channel 36 is the main channel 34
The potential well in the auxiliary channel 36 is deeper than the potential well formed in the main channel, as shown in FIG. 4, due to its higher doping level. Therefore, when charge is transferred from detector 12 to channels 34 and 36, the charge first flows into the deeper well formed in auxiliary channel 36. If the charge is large enough, the charge will overflow the deeper well and
It flows into the shallower well formed by 34. However, if the amount of charge is small, it will be confined only within the auxiliary channel 36.

As mentioned above, the transfer inefficiency is proportional to the volume of the embedded channel. A small amount of charge for a small volume of auxiliary channel
By holding it in 36, the auxiliary channel
The charge transfer efficiency along 36 is higher than when transferring the same small charge in the large volume main channel 34. Therefore,
A small charge will be transferred in CCD register 14 with high efficiency. On the other hand, a large charge flows into the well of the main channel 34 and is appropriately transferred in the channel 34 with relatively high efficiency. Thus, the CCD register according to the present invention can transfer both small charges and large charges with relatively high efficiency.

FIGS. 5 to 7 show another embodiment of the IR-CCD image sensor embodying the present invention. The image sensor 52 includes an array of detectors 54 arranged in rows and a vertical CCD register 56 provided between the rows of the detectors 54.
It has and. The image sensor 52 is an image sensor
Similar to 10, it is formed in a base 58 of P-conductivity type single crystal silicon having opposed major surfaces 60 and 62.

Each of the detectors 54 includes a region 64 of conductive material along a surface 62 in the substrate 58. A shutter barrier junction is formed between the region 64 and the substrate 58. The detector region 64 is preferably formed of either platinum silicide or palladium silicide. A guard ring 66 is formed around the edge of the detector area 64. The guard ring is an N-conductivity type region formed on the surface 62 in the substrate 58. Along the edge of the detector region 64 adjacent to the vertical CCD register 56, a conductive region 68 of N + conductivity type is provided on the surface 62 inside the substrate 58. This conductive region 68 serves to electrically couple charge from the detector 54 to the channel of the vertical CCD register 56. But,
If necessary, set the entire protection ring 66 to N + conductivity type,
This protection ring 66 may also serve as a conductive region. A layer 70 of deposited silicon oxide is deposited on the surface 62 of the substrate 58.
Are provided and extend over the detector area 64. Further, a metal layer 72 is provided on the silicon oxide layer 70 so as to cover each detector region 64. The metal layer 72 is composed of a radiation-reflecting metal, such as aluminum, which acts as a mirror to reflect the radiation that has passed through the detector region 64 back to the detector region.

The vertical CCD register 56 occupies an elongated portion in the substrate 58 that extends along the surface 62 between the rows of detectors 54.
A main channel 74 in the form of a conductivity type area is provided. The main channel 74 is located at a distance from adjacent edges of the detector area 64 of the detector 54. Lord Channel 74
Within it is an auxiliary channel 75 which is of the N-copper conductivity type but which is made up of a region having a higher conductive converter concentration than the main channel 74. This auxiliary channel 75 is provided in the center of the main channel 74, separated from both sides of the main channel 74, is narrower than the main channel, has a smaller volume than the main channel 74, and completely fits into the main channel 74. ing. Thermally grown silicon oxide layer 76 Channel 74
And extends over 75. Two sets of gates 77 and 78 are provided on the silicon oxide layer 76 across the channels 74 and 75. Gates 77 and 78 are formed of a conductive material such as doped polycrystalline silicon. The first set of gates 77 are all on the silicon oxide layer 76 and each gate 77
Extend along the portion of the two adjacent detectors 54 and across the space therebetween. Adjacent edges of adjacent gates 77 are separated at the portions of channels 74 and 75 adjacent to conductive region 68 of detector 54 adjacent thereto. Each of the first set of gates 77 has an extension 77a, which is on the substrate surface 62 between adjacent detectors 54 and by a portion of the silicon oxide layer 76. Separated from 62. Gate extension 77a
Electrically connect the gates of a similar first set 77 in all vertical CCD registers 14 and one of the gate extensions 77a extends to an edge contact at one end of the sensor array 10.

As shown in FIG. 7, each of the second set of gates 78 is on the silicon oxide layer 76 between the spaced edges of two adjacent first gates 77. The second gate 78 extends slightly into one of the adjacent first gates 77 and above the other gate 77 into the space between two adjacent detectors 54. The second gate 78 is separated from the first gate 77 by a layer 80 of silicon oxide. As shown in FIG. 6, each of the second gates 78 extends to the edge of the detector 54 on each side of the vertical CCD register 56. Thus, the second gate 78 extends beyond both sides of the main channel 74 and over the portion of the substrate surface 62 between the main channel 74 and each of the adjacent detectors 54.

Detector 54 not connected to a particular vertical CCD register 56
In the region of the substrate surface 62 between the main channel 74 and the main channel 74, the silicon oxide layer 76 has a thicker portion 76a than the other portions. There is a portion of each of the second gates 78 on the thick portion 76a of the silicon oxide layer, and thus a portion of the gates 78 is a distance greater than the distance between the rest of the gates 78 and the substrate surface 62. Separated from the surface. Second gate
Each of the 78 is on an extension 77a of the first gate 77, and then an extension 78 separated by a silicon oxide layer.
equipped with a. Each extension 78a electrically connects a corresponding second gate 78 of the vertical CCD register 56 to one of the extensions 78a extending to a terminal at one end of the image sensor array 52.

In the operation of the image sensor 52, the charge collected on the detector 54 is changed by applying a positive potential to the second gate 78,
Transferred to the vertical CCD register 56. Then gates 77 and 78
Is clocked at a negative potential and the charge travels along channels 74 and 75 to an output register at one end of vertical CCD register 56. The potential applied to gates 77 and 78 causes potential wells in channels 74 and 75 to form. In this case, the well in the auxiliary channel 75 is deeper than the well in the main channel 74. Therefore, the charge entering the channels 74 and 75 from the detector 54 first fills the deeper well in the auxiliary channel 75 and, if the charge is large enough, overflows into the well of the main channel 74. However, when the charge from the detector 54 is small, the charge remains in the auxiliary channel 75 and is therefore transferred relatively efficiently along the vertical CCD register 56.

In the above description, CCD registers 14 and 56 are the main channels 3
Although it is assumed that one auxiliary channel 36 or 75 is provided in 4 or 74, one or more auxiliary channels may be provided in the main channel. The CCD register 80 shown in FIG.
Within the substrate 84, there is a main channel 82 extending along a surface 86 of the substrate 84. The main channel 82 is of similar construction to the main buried channel 34 of FIGS. The first auxiliary channel 88 is a surface 86 within the substrate 84.
Extending along and extending into the main channel 82, is similar in construction to the auxiliary channel 36 of FIGS. The second auxiliary channel 90 extends along the surface 86 in the substrate 84 and is located within the first auxiliary channel 88, that is, at a substantially central position apart from both sides of the auxiliary channel 88. And is narrower than the first auxiliary channel. Therefore, the volume of the first auxiliary channel 88 is smaller than that of the main channel 82, and the volume of the second auxiliary channel 90 is smaller than that of the first auxiliary channel 88. The first auxiliary channel 88 has a higher conductivity converter concentration than the main channel 82, and thus a higher conductivity than the main channel 82. Second auxiliary channel
In 90, the concentration of the conductive converter is higher than that of the first auxiliary channel 88, and therefore, the conductivity is higher than that of the first auxiliary channel. A layer of silicon oxide 92 is on substrate surface 86 and extends over channels 82, 88 and 90. A plurality of gates 94 (only one of which is shown) formed of a conductive material such as conductive polycrystalline silicon is provided on the silicon oxide layer 92. Gate 94 is a channel
It extends across 82, 88 and 90 and is located along these channels.

When a potential is applied to gate 94, channels 82, 88
Potential wells are created at 90 and 90. First auxiliary channel
The potential well formed in 88 is deeper than the well in the main channel 82, and the potential well formed in the second auxiliary channel 90 is deeper than the well in the first auxiliary channel 88. Accordingly, the charges that try to flow into these channels first flow into the deepest potential well in the second auxiliary channel 90. As the charge increases, it overflows the well in the second auxiliary channel 90 into the potential well in the first auxiliary channel 88 and then into the potential well in the main channel 82. Therefore, when the amount of electric charge is small, the electric charge is confined in the second auxiliary channel 90, and when the amount of electric charge is medium, it is confined in the first auxiliary channel 88, and the electric charge is large. Then, Lord Channel
Enter 82. In this way, the CCD register 80 can efficiently transfer large charges, medium charges and small charges.

In the CCD image sensor 10 of the type shown in FIG. 1, a vertical C
An auxiliary channel can be provided not only in the CD register 14 but also in the output CCD register 18. However, if necessary, the auxiliary channel may be provided only in the output CCD register 18.

To demonstrate the improvements obtained with this invention, the following device was constructed.

Example I An infrared charge coupled device image sensor was fabricated in P-type single crystal silicon with a 32x63 array of detectors whose conductive layer was formed of palladium silicide. The output CCD register has a main channel region of 110 μm width and N conductivity type (injected with a dose of 1.3 × 10 ¹² cm ^-2 of phosphorus) and a width of 20 μm N conductivity type (5 × 10 ¹¹ cm at 150 KeV). ^-2 arsenic implanted) auxiliary channel region was provided. The transfer loss at 77 ° K for very low signal level is about 2 × 10 ^-4 per transfer from the transfer loss of 10 ^-3 to 10 ^-2 per time of CCD without auxiliary channel area. It decreased to the value.

Example II An infrared charge coupled device image sensor was fabricated in a P-type single crystal silicon substrate with a 64 × 128 detector array.
15 μm wide N conductivity type (1.3 × 10 ¹² cm) for output CCD register
A main channel of the implanting phosphorus) at a rate of ^-2 is provided an auxiliary channel of the N conductivity type with a width of 5 [mu] m (injected with arsenic at a rate of 5 × 10 ¹¹ cm ^-2). The following table shows the transfer loss per transfer (ε) for this CCD output register compared to one similar to this register but with only the main channel region.
Indicates.

As described above, according to the present invention, the detectors are arranged in a plurality of rows, and each row is a vertical buried channel type CCD which is different from each other.
The case where the present invention is applied to an IR-CCD image sensor equipped with a register has been described.
It can also be used as an imager. For example, the present invention can be implemented in a line sensor imager in which the detectors are arranged to form a single line and use only one CCD register. Such a licensor imager is provided with a transfer gate having a structure as shown in FIGS. 2 and 3 between the detector line and the CCD register, but the CCD register has the transfer gate shown in FIGS. There is no metal bus bar as shown in
The CCD gate terminates along one edge of the CCD register.

Further, the present invention can be used in a visible CCD image sensor, especially in an embedded channel of a large size. Generally, this type of image sensor includes a light-sensitive array called A register, a temporary storage array called B register, and an output register called C register. For example,
An A-resistor comprises a plurality of spaced-apart, parallel buried channel regions and a plurality of conductive gates transverse to and isolated from and parallel to each other. is there.
The B register includes a plurality of buried channels which are extensions of the channel of the A register and which are arranged in parallel with each other at intervals, and a plurality of parallel conductive gates which extend across the channel. I could use it. Further, the C register could be used with a single buried channel extending along the end of the B register channel. Light from the detected image is incident on the portion of the substrate on which the A register is formed and photons are converted to electrons in the channel of the A register. This electron is transferred along the channel of the A register, reaches the channel of the B register, and from there, is transferred to the channel of the C register. The auxiliary channel according to the present invention can be provided in the C register channel or in all channels.

As described above, according to the present invention, a CCD transfer device having a buried channel in which potential wells of different sizes are created so that charges are confined in a channel volume of a size corresponding to the size is obtained. To be This makes it possible to transfer charges along the channel with high efficiency.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing the structure of a typical IR-CCD image mentor, FIG. 2 is a plan view of one pixel of an IR-CCD image sensor embodying the present invention, and FIG. -
3 is a sectional view taken along line 3, FIG. 4 is a view showing the potential profile of the channel of the CCD register of FIG. 3, and FIG. 5 is a plan view of one pixel of another type of IR-CCD image sensor embodying the present invention. FIG. 6 is a sectional view taken along line 5-5 in FIG. 5, FIG. 7 is a sectional view taken along line 7-7 in FIG. 5, and FIG. 8 is a further CCD register embodying the present invention. FIG. 12 ... Radiation detector, 14 ... Vertical CCD register, 18 ... Output register, 20 ... Substrate, 34 ... Main channel (first charge confinement means), 36 ... Auxiliary channel (second charge confinement) Means), 40 ... gate.

Claims (2)

[Claims] 1. A substrate of semiconductor material having at least one major surface, and an elongated portion of said substrate extending adjacent said major surface, said portion having a conductivity opposite to the conductivity type of the adjacent substrate. Channel means occupying an elongated portion containing a dopant having a mold-like characteristic and forming a channel of a predetermined width for confining charges; and insulating from this main surface on said main surface of said substrate,
And a plurality of conductive gates, which are provided so as to occupy a series of positions along the length direction of the elongated portion and transfer charges along the length direction of the elongated portion. A region located substantially in the center of the elongated portion and adjacent to the surface, the region having a width smaller than the predetermined width and separated from both sides of the elongated portion is a region adjacent to the elongated portion. A buried channel charge-coupled device, characterized in that it has a higher concentration of the above-mentioned doping agent and continuously extends below the plurality of conductive gates. 2. An area adjacent to the surface located substantially in the center of a region adjacent to the surface located in the approximate center and having a width smaller than the small width and located in the approximate center. And a region separated from both sides of the region adjacent to the surface has a higher concentration of the dopant than the adjacent region of the region adjacent to the surface and adjacent to the surface. The buried channel charge-coupled device according to claim (1), characterized in that the lower side of the conductive gate is continuously extended.