JP4490075B2 - Solid-state imaging device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a solid-state imaging device having a plurality of photoelectric conversion elements (photodiodes) having different characteristics in each pixel of a light receiving unit, and a method for manufacturing the same.

  Known solid-state imaging devices include CCD solid-state imaging devices that transfer signal charges using a charge-coupled device (CCD), MOS-type solid-state imaging devices that amplify an image signal from a photosensitive device, and output the amplified signal. . A photodiode is mainly used as the photosensitive element, and a large number of pixels are arranged in a matrix in the light receiving region. The photosensitive elements are arranged in a square matrix at a constant pitch in the row direction and the column direction, or every other position in the row direction and the column direction (for example, shifted by 1/2 pitch). There is a honeycomb arrangement.

  A solid-state imaging device has been proposed that includes a high-sensitivity light-receiving part (high-sensitivity photodiode) that receives light with different sensitivities in the light-receiving part and a low-sensitivity light-receiving part (low-sensitivity photodiode). (For example, refer to Patent Document 1.) By combining signals obtained from photodiodes having different sensitivities, an image signal having a wide dynamic range can be realized.

Japanese Patent Application No. 2002-016835

  An object of the present invention is a solid-state imaging element having a honeycomb structure including two photodiodes having different sensitivities in the same pixel, and the two photodiodes have a similar impurity distribution profile for each readout electrode. An imaging device and a manufacturing method thereof are provided.

According to one aspect of the present invention, (a) a second conductivity type well is formed by adding an impurity of a second conductivity type opposite to the first conductivity type from the main surface of the first conductivity type semiconductor substrate. And (b) forming a plurality of first conductivity type vertical CCD channels meandering in the column direction so as to leave a rhomboid pixel region in a honeycomb shape in the well; and (c) a plurality of Forming a plurality of vertical transfer electrodes so as to cover the vertical CCD channel; and (d) a first conductivity type impurity in the pixel region in the well using the vertical transfer electrodes as a part of a mask. Forming a first impurity layer and a second impurity layer in each pixel region by ion implantation from a first direction intersecting a normal direction of the main surface; and (e) the first and second layers. Forming a second conductivity type separation impurity layer between the two impurity layers; ) By implanting ions of a second conductivity type into the well from a second direction intersecting with the normal direction of the main surface, the first, second and isolation impurity layers are formed above the first impurity layer. Forming a two-conductivity type buried impurity layer, wherein the first and second impurity layers constitute two photoelectric conversion elements having different sensitivities in each pixel region, and And the signal charges accumulated in the second impurity layer are respectively read out to the first vertical transfer electrode of the plurality of vertical transfer electrodes and the vertical CCD channel below the second vertical transfer electrode, In the step (d), when the direction of the orthogonal projection of the first direction onto the main surface is referred to as a third direction, an edge facing the pixel region of the first vertical transfer electrode and the third direction and the angle between the direction, the surface in the pixel region of the second vertical transfer electrodes Edges and equal the angle between the third direction, in the step (f), when calling orthogonal projection direction to said principal surface in a second direction and the fourth direction, the first An angle formed by an edge of the first vertical transfer electrode facing the pixel region and the fourth direction, and an angle formed by an edge of the second vertical transfer electrode facing the pixel region and the fourth direction. A method for manufacturing an equalized solid-state imaging device is provided.

  According to the above manufacturing method, it is possible to manufacture a solid-state imaging device having a honeycomb structure in which two photodiodes having different sensitivities in one pixel have the same impurity distribution profile for each readout electrode.

Further, according to another aspect of the present invention, a plurality of rhomboid pixel regions arranged in a honeycomb direction in a row direction and a column direction, a plurality of vertical transfer channels arranged along the pixel region in a column direction, and the A semiconductor substrate including a horizontal transfer channel provided at an end of the plurality of vertical transfer channels; a plurality of vertical transfer electrodes formed above the plurality of vertical transfer channels; and a plurality formed above the horizontal transfer channel. The pixel region includes a first impurity layer of a first conductivity type constituting a first photoelectric conversion element having a relatively high sensitivity, and a second pixel having a relatively low sensitivity. A first conductivity type second impurity layer constituting a photoelectric conversion element, and a second conductivity type embedding impurity opposite to the first conductivity type, formed above the first and second impurity layers. And the first impurity layer includes a front layer Of the plurality of vertical transfer electrodes, the second impurity layer is formed in a region including a region below the first electrode which is a readout electrode of the first photoelectric conversion element, and the second impurity layer is formed of the plurality of vertical transfer electrodes. The buried impurity layer is formed in a region including a region below the second electrode which is a readout electrode of the second photoelectric conversion element, and the burying impurity layer does not include a region below the first and second electrodes. The first and second impurity layers are formed by ion-implanting the first conductivity type impurity from a first direction intersecting a normal direction of the main surface of the semiconductor substrate. , When the direction of orthogonal projection of the first direction onto the main surface is the third direction, the angle formed by the edge of the first electrode facing the pixel region and the third direction, An angle formed by an edge of the second electrode facing the pixel region and the third direction; The buried impurity layer is formed by ion-implanting the second conductivity type impurity from a second direction intersecting a normal direction of the main surface of the semiconductor substrate. When the direction of the orthogonal projection of the second direction onto the main surface is the fourth direction, the angle formed by the edge of the first electrode facing the pixel region and the fourth direction, Formed by equalizing the angle formed between the edge of the two electrodes facing the pixel region and the fourth direction, and the first and second photoelectric conversion elements are similar to each readout electrode. A solid-state imaging device having an impurity distribution profile and having a read voltage of the first photoelectric conversion element equal to a read voltage of the second photoelectric conversion element is provided.

Furthermore, according to another aspect of the present invention, a plurality of rhombic pixel regions arranged in a honeycomb direction in a row direction and a column direction, a plurality of vertical transfer channels arranged along the pixel region in a column direction, and the A semiconductor substrate including a horizontal transfer channel provided at an end of the plurality of vertical transfer channels; a plurality of vertical transfer electrodes formed above the plurality of vertical transfer channels; and a plurality formed above the horizontal transfer channel. The pixel region includes a first impurity layer of a first conductivity type constituting a first photoelectric conversion element having a relatively high sensitivity, and a second pixel having a relatively low sensitivity. A first conductivity type second impurity layer constituting a photoelectric conversion element, and a second conductivity type embedding impurity opposite to the first conductivity type, formed above the first and second impurity layers. And the first impurity layer includes a front layer Of the plurality of vertical transfer electrodes, the second impurity layer is formed in a region not including a region below the first electrode which is a readout electrode of the first photoelectric conversion element, and the second impurity layer is formed of the plurality of vertical transfer electrodes. Of these, the buried impurity layer is formed in a region not including a region below the second electrode which is a readout electrode of the second photoelectric conversion element, and the burying impurity layer includes the region below the first electrode and the second electrode. The first and second impurity layers are formed in a region including a region below the electrode, and the first conductivity type impurity is introduced from a first direction intersecting a normal direction of the main surface of the semiconductor substrate. In the ion implantation, when the direction of orthogonal projection onto the main surface in the first direction is the third direction, the edge facing the pixel region of the first electrode and the third electrode An angle formed by a direction and an edge facing the pixel region of the second electrode; The burying impurity layer is formed by making the angle formed with the third direction equal to each other, and the burying impurity layer causes the second conductivity type impurity to cross the normal direction of the main surface of the semiconductor substrate. In the ion implantation, when the direction of orthogonal projection onto the main surface in the second direction is the fourth direction, the edge facing the pixel region of the first electrode and the first 4 and the angle formed between the edge of the second electrode facing the pixel region and the fourth direction, the first and second photoelectric conversion elements. Provides a solid-state imaging device having a similar impurity distribution profile for each readout electrode, and capable of suppressing blooming during charge readout of the first and second photoelectric conversion elements.

  These solid-state imaging devices are honeycomb-structured solid-state imaging devices in which two photodiodes having different sensitivities in one pixel have the same impurity distribution profile for each readout electrode.

  According to the present invention, a solid-state imaging device having a honeycomb structure including two photodiodes having different sensitivities in the same pixel, the two photodiodes having a similar impurity distribution profile with respect to each readout electrode. An imaging device and a manufacturing method thereof can be provided.

  1A and 1B are a schematic plan view and a cross-sectional view, respectively, for explaining a part of a structure of a solid-state imaging device and a manufacturing method thereof.

  Reference is made to FIG. Each pixel 30 is formed including a photodiode 42 that generates and accumulates signal charges corresponding to the amount of light incident through the opening 8 of the light shielding film. A vertical CCD channel 2 is disposed on the right side of the pixel 30. Vertical transfer electrodes 40 and 41 are formed above the vertical CCD channel 2. The signal charges generated and accumulated by the photodiode 42 are arranged in the column direction (vertical direction, downward direction in the figure) in the vertical CCD channel 2 as a whole by a drive signal (transfer voltage) applied to the vertical transfer electrodes 40 and 41. ). The element isolation region 1 is provided along a plurality of pixels 30 existing in the column direction (vertical direction) and a vertical CCD channel 2 extending in the column direction (vertical direction). To separate. The directions of arrows X and Y in the drawing will be described later.

FIG. 1B is a cross-sectional view taken along line 1B-1B in FIG. For example, a p-type well 17 is formed on one surface of an n-type semiconductor substrate 18 which is a silicon substrate. An n-type impurity layer 42 a is formed in the vicinity of the surface of the p-type well 17 to constitute the photodiode 42. The p ⁺ -type impurity layer 12 is a buried region in which the photodiode 42 (n-type impurity layer 42a) is embedded away from the substrate surface.

  In the vicinity of the n-type impurity layer 42a, the vertical CCD channel 2 which is a region to which an n-type impurity is added is disposed.

  A gate insulating film 11 is formed on the surface of the semiconductor substrate 18, and vertical transfer electrodes 40 and 41 made of, for example, polysilicon are formed thereon. The vertical transfer electrodes 40 and 41 are arranged so as to cover the vertical CCD channel 2. The n-type impurity layer 42a and the vertical CCD channel 2 below the vertical transfer electrode 41 and the p-type well 17 between them in the left part of the figure constitute a readout transistor from the photodiode 42 to the vertical CCD channel 2.

  A light shielding film 9 is formed above the vertical transfer electrodes 40 and 41 via an insulating film. The light shielding film 9 has an opening 8 above the photodiode 42 in the pixel 30, and light incident on the light receiving portion enters the photodiode 42 from the opening 8.

The n-type impurity layer 42a and the p ⁺ -type impurity layer 12 are formed by ion implantation of n-type and p-type impurities, respectively. The ion implantation is performed in a self-aligned manner using the vertical transfer electrodes 40 and 41 as masks after the vertical transfer electrodes 40 and 41 are formed.

The ion implantation for forming the impurity concentration profiles of the n-type impurity layer 42a and the p ⁺ -type impurity layer 12 aims at preventing channeling of the silicon crystal and controls the position where the both are formed. It is performed from a predetermined direction inclined several degrees from the normal direction of the (silicon substrate). For example in forming the n-type impurity layer 42a is tilted from the normal direction of the semiconductor substrate 18 (vertically upward direction from the sheet surface) by ion implantation from the direction of the arrow X in FIG. 1 (A), the p ⁺ -type impurity layer 12 When forming, ion implantation is performed from the direction of arrow Y inclined in the opposite direction.

By performing ion implantation of n-type impurities from the arrow X direction, an n-type impurity layer 42a is formed so as to enter the lower region of the vertical transfer electrode 41 as shown in FIG. On the other hand, the p ⁺ -type impurity layer 12 is formed at a position away from the end of the vertical transfer electrode 41 by performing ion implantation of the p-type impurity from the arrow Y direction. In FIG. 1B, these states are indicated by arrows.

Thus, by controlling the formation positions of the n-type impurity layer 42 a and the p ⁺ -type impurity layer 12, the voltage (depletion voltage) for reading out the signal charge accumulated in the photodiode 42 to the vertical CCD channel 2 is reduced. In addition, it is possible to suppress a blooming phenomenon in which charges overflow into the vertical CCD channel 2 when a large amount of light is incident.

In the ion implantation of impurities when forming the n-type impurity layer 42 a and the p ⁺ -type impurity layer 12, the implantation direction with respect to the vertical transfer electrode 41, which is a signal charge readout electrode generated by the photodiode 42. Is stipulated.

  FIGS. 2A and 2B are schematic plan views of a solid-state imaging device in which a high-sensitivity light-receiving part (high-sensitivity photodiode) and a low-sensitivity light-receiving part (low-sensitivity photodiode) are formed in the same pixel, respectively. It is a figure and sectional drawing.

  FIG. 2A schematically shows a part of the light receiving portion of the solid-state imaging device. FIG. 2A shows a plurality of pixels 30. Each pixel 30 has a light-receiving region with a different area, and is a high-sensitivity photodiode 6 and a low-sensitivity photodiode 5 that are two photodiodes with different sensitivities, and an inter-photodiode element isolation region provided between the two photodiodes. 7 is formed. The high-sensitivity photodiode 6 has a relatively large area and constitutes a main photosensitive portion. The low-sensitivity photodiode 5 has a relatively small area and constitutes a corresponding photosensitive portion. As will be described later, the aperture ratio of the light shielding film above the high sensitivity photodiode 6 is larger than that above the low sensitivity photodiode 5. The high sensitivity photodiode 6 and the low sensitivity photodiode 5 accumulate signal charges according to the amount of incident light. The inter-photodiode element isolation region 7 electrically isolates two photodiodes (a high sensitivity photodiode 6 and a low sensitivity photodiode 5) in one pixel.

  A vertical CCD channel 2 is disposed on the right side of the pixel 30. A vertical transfer electrode (high sensitivity photodiode read gate electrode) 4 and a vertical transfer electrode (low sensitivity photodiode read gate electrode) 3 are formed above the vertical CCD channel 2.

  The vertical transfer electrode (high-sensitivity photodiode read gate electrode) 4 controls charge read from the high-sensitivity photodiode 6 to the vertical CCD channel 2. The vertical transfer electrode (low sensitivity photodiode readout gate electrode) 3 controls charge readout from the low sensitivity photodiode 5 to the vertical CCD channel 2. A drive signal (transfer voltage) is applied to both the vertical transfer electrodes 3 and 4, and the signal charge read from each pixel 30 to the vertical CCD channel 2 is reduced in the vertical direction as a whole (in FIG. Direction). However, the signal charge read from the high sensitivity photodiode 6 and the signal charge read from the low sensitivity photodiode 5 are transferred separately.

  The element isolation region 1 is provided along a plurality of pixels 30 existing in the column direction (vertical direction) and a vertical CCD channel 2 extending in the column direction (vertical direction). To separate.

  In the light receiving portion, the upper portions of the two vertical transfer electrodes 3 and 4 are covered with a light shielding film 9 having an opening 8. The light shielding film 9 prevents light from entering a region other than the pixel 30 in the light receiving unit. The opening 8 of the light shielding film 9 is formed above each pixel 30. Further, the aperture ratio above the high-sensitivity photodiode 6 is high, and the aperture ratio above the low-sensitivity photodiode 5 is low. The light that has entered the light receiving part enters each pixel 30 through the opening 8.

  Note that the illustrated configuration is a pixel structure having a honeycomb structure, and the plurality of illustrated pixels 30 are arranged at positions shifted by a half pitch in the vertical and horizontal directions.

FIG. 2B is a cross-sectional view taken along line 2B-2B in FIG. For example, a p-type well 17 is formed on one surface of an n-type semiconductor substrate 18. Near the surface of the p-type well 17, two n-type impurity layers 5a and 6a are formed to constitute a photodiode. The relatively large (high-sensitivity photodiode) n-type impurity layer 6 a constitutes the high-sensitivity photodiode 6, and the relatively small (low-sensitivity photodiode) n-type impurity layer 5 a constitutes the low-sensitivity photodiode 5. To do. The inter-photodiode element isolation region 7 is formed by adding a p-type impurity. As described above, the (high-sensitivity photodiode) n-type impurity layer 6a and the (low-sensitivity photodiode) n-type impurity layer 5a are formed. Separate electrically. The p ⁺ -type impurity layer 12 is a buried region in which the two photodiodes 5 and 6 are embedded away from the substrate surface.

  In the vicinity of the n-type impurity layers 5a and 6a constituting the photodiode, a vertical CCD channel 2 which is a region to which an n-type impurity is added is disposed.

  On the surface of the semiconductor substrate 18, for example, a silicon oxide film by thermal oxidation, and a silicon nitride film by CVD, for example, a silicon oxide film obtained by thermally oxidizing the silicon nitride film surface, for example, are stacked in this order from the bottom. A gate insulating film 11 made of an ONO film is formed, and a vertical transfer electrode (high sensitivity photodiode read gate electrode) 4 and a vertical transfer electrode (low sensitivity photodiode read gate electrode) made of, for example, polysilicon are formed thereon. ) 3 is formed. Each vertical transfer electrode 3, 4 is arranged so as to cover the vertical CCD channel 2. (High-sensitivity photodiode) The vertical CCD channel 2 below the n-type impurity layer 6a and the vertical transfer electrode (high-sensitivity photodiode read gate electrode) 4 and the p-type well 17 between them are perpendicular to the high-sensitivity photodiode 6. A readout transistor for the CCD channel 2 is formed. Further, the (low sensitivity photodiode) n-type impurity layer 5a, the vertical CCD channel 2 below the vertical transfer electrode (low sensitivity photodiode read gate electrode) 3, and the p-type well 17 between them are provided with the low sensitivity photodiode 5. To the vertical CCD channel 2 is constituted. Therefore, the signal charges from the two photodiodes 5 and 6 (n-type impurity layers 5a and 6a) are read out in different directions.

  A light shielding film 9 is formed above each vertical transfer electrode 3 and 4 with an insulating film, for example, with tungsten. The light shielding film 9 has an opening 8 above the two photodiodes 5 and 6 in the pixel 30, and the light 19 incident on the light receiving unit enters the two photodiodes 5 and 6 from the opening 8. By forming the inter-photodiode element isolation region 7, it is possible to prevent the charges once accumulated in each of the two photodiodes 5 and 6 from being mixed thereafter.

  3A is a schematic plan view showing the configuration of the solid-state imaging device having the light receiving section shown in FIG. 2A, and FIG. 3B is a diagram of a solid-state imaging device including the solid-state imaging device. It is a schematic block diagram which shows the principal part.

  Reference is made to FIG. The solid-state imaging device is, for example, a honeycomb array, a vertical CCD unit including a plurality of pixels 30 each including two photodiodes, a vertical CCD channel 2 (and vertical transfer electrodes 3 and 4 thereabove), and a vertical CCD. The horizontal CCD unit 66 electrically coupled to the unit, the driving unit 65 having wiring for driving the CCD, and the end of the horizontal CCD unit 66 amplifies the output charge signal from the horizontal CCD unit 66. An amplifier circuit unit 67 is included.

  In the pixel 30, signal charges generated and accumulated in accordance with the amount of light incident on either the high-sensitivity or low-sensitivity photodiode are read out to the vertical CCD channel 2, and the horizontal CCD as a whole in the vertical CCD channel 2. It is transferred in the direction toward the unit 66 (vertical direction). The signal charge is transferred in the vertical CCD channel 2 by a drive signal (transfer voltage) supplied from the drive unit 65. The signal charges transferred to the end of the vertical CCD channel 2 pass through the horizontal CCD channel in the horizontal CCD unit 66 (the horizontal CCD unit 66 includes a horizontal CCD channel and a horizontal transfer electrode above it). It is transferred in the horizontal direction, amplified by the amplifier circuit section 67, and taken out to the outside.

  Reference is made to FIG. A semiconductor chip, which includes a light receiving portion and a peripheral circuit region, generates signal charges according to the amount of light incident on each of two types of photodiodes in a pixel, and separately generates image signals based on the generated signal charges. The solid-state imaging device 51 that is transferred to and supplied to the solid-state imaging device, and a drive signal (transfer voltage or the like) for driving the solid-state imaging device 51 is generated and supplied from the solid-state imaging device 51. Output signal processing device 53 and output signal processing device 53 that perform processing such as noise reduction, white balance, and data compression on the two types of image signals (image signals derived from high-sensitivity photodiode 6 and low-sensitivity photodiode 5) A storage device 54 that stores image signals, for example, a storage card, and a display device that displays image signals, for example, a liquid crystal display device. 55, the transmission device 56 is an interface for transmitting an image signal to the outside, include a television 57 for displaying the image signals as required, the solid-state imaging device is configured.

  Signals supplied from the drive signal generator 52 to the solid-state imaging device 51 are a horizontal CCD drive signal, a vertical CCD drive signal, an output amplifier drive signal, a substrate bias signal, and the like. Further, a signal for reading out the accumulated charge of the high sensitivity photodiode 6 and a signal for reading out the accumulated charge of the low sensitivity photodiode 5 are supplied.

  The storage device 54 has two areas for receiving and storing image signals from the output signal processing device 53. One area stores an image signal based on the high sensitivity photodiode 6, and the other area stores an image signal based on the low sensitivity photodiode 5.

  By using the high-sensitivity photodiode 6 and the low-sensitivity photodiode 5 in the light receiving portion, an image with a wide dynamic range can be obtained.

  However, as described above with reference to FIGS. 2A and 2B, in the case of the solid-state imaging device having the honeycomb structure in which the high-sensitivity photodiode 6 and the low-sensitivity photodiode 5 are provided in the same pixel 30, The signal charge from the low-sensitivity photodiode 5 is read by the vertical transfer electrode 3, and the signal charge from the high-sensitivity photodiode 6 is read by the other vertical transfer electrode 4. For this reason, two readout electrodes are required.

  Above the p-type well 17 where the low-sensitivity photodiode 5 and the high-sensitivity photodiode 6 are formed, the edges of these two readout electrodes (vertical transfer electrodes 3 and 4) are viewed from the normal direction of the semiconductor substrate 18. In this case, the p-type well 17 is formed so as to be exposed in a diamond shape. Accordingly, when ion implantation of impurities is performed to form the high-sensitivity photodiode 6 (n-type impurity layer 6a) and the low-sensitivity photodiode 5 (n-type impurity layer 5a), for example, either one of the readout electrodes is used. The direction of impurity ion implantation is determined to perform ion implantation, and two photodiodes having different sensitivities (high sensitivity photodiode 6 and low sensitivity photodiode 5) are formed. A difference occurs in the impurity distribution profile. For this reason, there may be a large difference between the voltage read out to the vertical CCD channel 2 and the suppression of blooming.

Therefore, the inventors of the present application first formed two photodiodes in the solid-state imaging device having two photodiodes having different sensitivities in the same pixel, and formed p ⁺ above the photodiodes in order to prevent display white spots. It was considered that the two photodiodes were separated from the surface of the semiconductor substrate by embedding a type impurity layer. In order to prevent an increase in the read voltage of the signal charges of the photodiode according to the p ⁺ -type impurity layer was considered to form a p ⁺ -type impurity layer in a region other than the region below the respective readout electrodes. Furthermore, it was considered to form two photodiodes so that the read voltages of the two photodiodes having different sensitivities are approximately equal.

  4A to 4D are a schematic plan view and a cross-sectional view for explaining the method for manufacturing the solid-state imaging device according to the first embodiment.

  Reference is made to FIG. For example, a semiconductor substrate 18 which is an n-type silicon substrate is prepared, and a p-type impurity having a reverse conductivity type, such as boron, is ion-implanted from the surface thereof to form a p-type well 17.

An n-type impurity such as phosphorus, arsenic or antimony is ion-implanted in the vicinity of the surface of the p-type well 17 to form a vertical CCD channel 2 meandering in the column direction so as to leave a substantially rhombic pixel region in a honeycomb shape. The ion implantation is performed, for example, at an acceleration energy of 10 keV to 200 keV and a dose amount of 5.0 × 10 ^{11 to} 1.0 × 10 ¹⁴ cm ⁻² .

In addition, an element isolation region (the element isolation region 1 appears in FIG. 4B) is formed by ion implantation of a p-type impurity such as boron, gallium, or indium. The ion implantation is performed, for example, at an acceleration energy of 50 keV to 1000 keV and a dose of 1.0 × 10 ^{11 to} 1.0 × 10 ¹³ cm ⁻² .

  A gate insulating film 11 is formed on the surface of the semiconductor substrate 18. The gate insulating film 11 is, for example, a silicon oxide film by thermal oxidation (thickness is, for example, 50 to 300 mm), and a silicon nitride film (thickness is, for example, 100 to 1000 mm) formed thereon by CVD, for example, this silicon nitride film A silicon oxide film (thickness is, for example, 10 to 200 mm) obtained by thermally oxidizing the surface is formed by an ONO film laminated in this order from the bottom.

  Further, a vertical transfer electrode (low-sensitivity photodiode readout gate electrode) 3 and a vertical transfer electrode (high-sensitivity photodiode readout gate electrode) 4 are formed of polysilicon, for example, so as to cover the vertical CCD channel 2. The two vertical transfer electrodes 3 and 4 are produced, for example, by depositing polysilicon on the gate insulating film 11 to a thickness of 1000 to 10,000 by CVD and patterning the polysilicon by photolithography and etching.

  Reference is made to FIGS. 4B and 4C. FIG. 4B is a plan view for explaining the manufacturing process of the solid-state imaging device following FIG. 4A, and FIG. 4C is taken along line 4C-4C in FIG. 4B. It is sectional drawing.

An n-type impurity layer 6a (high sensitivity photodiode 6) and an n-type impurity layer 5a (low sensitivity photodiode 5) are formed in the pixel region in the p-type well 17 by ion implantation. An n-type impurity such as phosphorus, arsenic, or antimony is implanted into the pixel region from a direction intersecting the normal direction of the semiconductor substrate 18 using the vertical transfer electrodes 3 and 4 as a part of the mask. At this time, the implantation is performed so that the orthogonal projection direction on the semiconductor substrate 18 is substantially equal to the edges of the two vertical transfer electrodes 3 and 4 at the ion implantation position. For example, the orthogonal projection direction is the direction of the arrow U shown in FIG. 4B (the vertical transfer electrodes 3 and 4 extend as a whole, that is, along the horizontal direction and enter the lower side of the vertical transfer electrodes 3 and 4. Ion implantation is performed so that the direction is from left to right in the figure. The ion implantation is performed, for example, at an acceleration energy of 250 keV to 2000 keV, a dose amount of 1.0 × 10 ^{11 to} 2.0 × 10 ¹³ cm ⁻² , and a tilt angle (an angle inclined from the normal direction of the semiconductor substrate 18) of 7 °. A resist mask is formed on the inter-photodiode element isolation region described later to prevent ion implantation.

  Here, “substantially equal” means that they are equal within a range of errors based on the performance of the device, and two signal charges stored in the high-sensitivity photodiode 6 and the low-sensitivity photodiode 5 are read out. The relationship between the two angles so that the read voltages are substantially equal. For example, the n-type impurity layer 5a (low sensitivity photodiode 5) is formed so as to penetrate deeper into the readout electrode than the n-type impurity layer 6a (high sensitivity impurity layer 6), and the n-type impurity layer 5a (low sensitivity photodiode). In consideration of the narrow channel effect generated in 5), the intention is to perform ion implantation at an angle that makes both read voltages substantially equal.

Subsequently, an inter-photodiode element isolation region 7 is formed. In forming the inter-photodiode element isolation region 7, a p-type impurity such as boron, gallium, or indium is used, for example, an acceleration energy of 50 keV to 1000 keV and a dose of 1.0 × 10 ^{11 to} 1.0 × 10 ¹³ cm ^−2. Ion implantation.

A p ⁺ -type impurity layer 12 for burying n-type impurity layers 5a and 6a is formed by ion implantation. A p-type impurity such as boron, gallium, or indium is implanted from a direction intersecting the normal direction of the semiconductor substrate 18. At this time, the implantation is performed so that the orthogonal projection direction on the semiconductor substrate 18 is substantially equal to the edges of the two vertical transfer electrodes 3 and 4 at the ion implantation position. For example, the orthogonal projection direction is the direction indicated by the arrow V shown in FIG. 4B (the vertical transfer electrodes 3 and 4 extend as a whole, that is, along the horizontal direction and do not enter below the vertical transfer electrodes 3 and 4. The ion implantation is performed so that the direction is from the right to the left in the figure. The ion implantation is performed, for example, at an acceleration energy of 1 keV to 100 keV, a dose amount of 1.0 × 10 ^{12 to} 1.0 × 10 ¹⁶ cm ⁻² , and a tilt angle of 7 °.

  The orthogonal projection direction of the n-type impurity layer 6a (high sensitivity photodiode 6) and the n-type impurity layer 5a (low sensitivity photodiode 5) onto the semiconductor substrate 18 in the n-type impurity implantation direction is 2 at the ion implantation position. The n-type impurity layer 6a (high-sensitivity photodiode 6) is a vertical transfer that is a read electrode of the n-type impurity layer 6a by being adjusted so as to have substantially the same angle with respect to the edges of the two vertical transfer electrodes 3 and 4. The n-type impurity layer 5a (low-sensitivity photodiode 5) is formed so as to enter under the vertical transfer electrode 3 serving as its readout electrode.

Further, by adjusting the orthogonal projection direction of the p-type impurity implantation direction onto the semiconductor substrate 18 to be substantially equal to the edges of the two vertical transfer electrodes 3 and 4 at the ion implantation position, ions are adjusted. By the implantation, the p ⁺ -type impurity layer 12 is formed at a position away from both ends of the two vertical transfer electrodes 3 and 4. In FIG. 4C, this state is indicated by an arrow.

  Reference is made to FIG. The surfaces of the vertical transfer electrodes 3 and 4 are thermally oxidized, and a silicon oxide film 15 having a thickness of, for example, 100 to 1000 mm is formed thereon.

  A light shielding film 9 is formed on the vertical transfer electrodes 3 and 4 with, for example, tungsten via a silicon oxide film 15. The thickness of the light shielding film 9 is, for example, 500 to 5000 mm. The opening 8 of the light shielding film 9 is formed by patterning.

  The honeycomb structured solid-state imaging device according to the first embodiment is manufactured including the steps as described above.

The two n-type impurity layers 5a and 6a are formed so as to enter under the respective readout electrodes (vertical transfer electrodes 3 and 4), or the p ⁺ -type impurity layer 12 is provided with the two vertical transfer electrodes 3 and 4 In the solid-state imaging device schematically shown in FIG. 4 (D), it is formed at a position away from both ends of (a region not including the vertical transfer electrodes 3 and 4). The depletion voltage can be reduced for both of the two readout electrodes (vertical transfer electrodes 3 and 4).

It is desirable that the tilt angle of ion implantation when forming n-type impurity layers 5a and 6a or p ⁺ -type impurity layer 12 is 3 ° to 28 °.

  In addition to the steps described above, a horizontal CCD unit 66, a driving unit 65, an amplifier circuit unit 67, and the like as shown in FIG.

FIGS. 5A and 5B are a schematic plan view and a cross-sectional view, respectively, for explaining the method of manufacturing the solid-state imaging device according to the second embodiment. A solid-state imaging device effective for preventing blooming is manufactured by the manufacturing method according to the second embodiment. The manufacturing method of the solid-state imaging device according to the second embodiment is different from that according to the first embodiment in that the semiconductor substrate 18 in the ion implantation direction when forming the n-type impurity layers 5a and 6a and the p ⁺ -type impurity layer 12 is used. This is the point in which the upward orthogonal projection direction is reversed. The other points are the same as the manufacturing method of the solid-state imaging device according to the first embodiment.

FIG. 5A is a plan view for explaining a process corresponding to the process described with reference to FIG. 4B of the first embodiment. In the first embodiment, n-type impurities are ion-implanted from the direction in which the orthogonal projection direction onto the semiconductor substrate 18 is the arrow U direction to form the n-type impurity layers 5a and 6a, and the arrow V direction is obtained. A p ⁺ -type impurity layer 12 was formed by ion implantation of p-type impurities from the direction. In the second embodiment, n-type impurities are ion-implanted from the direction in which the orthogonal projection direction onto the semiconductor substrate 18 is the arrow V direction to form the n-type impurity layers 5a and 6a and the arrow U direction. A p ⁺ -type impurity layer 12 is formed by ion implantation of p-type impurities from the direction.

In both the formation of the n-type impurity layers 5a and 6a and the formation of the p ⁺ -type impurity layer 12, the orthogonal projection direction on the semiconductor substrate 18 in the ion implantation direction is the two vertical transfer electrodes 3 and 4 at the ion implantation position. The ion implantation is performed so that the angles are substantially equal to the edges of the film. Here, “substantially equal” means that the error ranges are equal based on the performance of the apparatus and the relationship between the two angles so that blooming is suppressed to approximately the same extent.

  FIG. 5B shows a solid-state imaging device manufactured from the formation of the impurity layer by the above-described ion implantation to the formation of the light shielding film 9 and its opening 8 in the same manner as in the first embodiment. FIG. 5 is a schematic cross-sectional view taken along line 5B-5B.

N-type impurity layers 5 a and 6 a are not formed in a region below vertical transfer electrodes 3 and 4. (It is formed in a region other than the lower region.) The p ⁺ -type impurity layer 12 includes a lower region of the vertical transfer electrode (low-sensitivity photodiode read gate electrode) 3 and a vertical transfer electrode (high-sensitivity photodiode read gate). Electrode) 4 is formed in a region including a lower region.

  The solid-state imaging device according to the second embodiment is a solid-state imaging device in which the separation between the photodiode and the vertical CCD channel 2 is enhanced. With the above-described structure, signal charges generated in the photodiode are less likely to overflow into the vertical CCD channel even when a large amount of light is incident, and in the solid-state imaging device having a honeycomb structure, the sensitivity formed in the same pixel is different. The blooming phenomenon of the two photodiodes can be prevented and adjusted.

  Note that all the conductivity types of the respective regions in the embodiments may be reversed.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

  The solid-state imaging device and the manufacturing method thereof described above can be used for all honeycomb structured digital cameras and the manufacturing method thereof.

(A) And (B) is the schematic plan view and sectional drawing for demonstrating the structure of a solid-state image sensor, and a part of manufacturing method, respectively. (A) and (B) are a schematic plan view of a solid-state imaging device in which a high-sensitivity light-receiving part (high-sensitivity photodiode) and a low-sensitivity light-receiving part (low-sensitivity photodiode) are formed in the same pixel, respectively. It is sectional drawing. (A) is a schematic plan view showing a configuration of a solid-state imaging device having the light receiving section shown in FIG. 2 (A), and (B) shows a main part of the solid-state imaging device including the solid-state imaging device. It is a schematic block diagram. (A)-(D) are the schematic plan views and sectional drawings for demonstrating the manufacturing method of the solid-state image sensor by 1st Example. (A) And (B) is the schematic plan view and sectional drawing for demonstrating the manufacturing method of the solid-state image sensor by 2nd Example, respectively.

Explanation of symbols

1 Element isolation region 2 Vertical CCD channel 3 Vertical transfer electrode (low sensitivity photodiode readout gate electrode)
4 Vertical transfer electrode (high sensitivity photodiode readout gate electrode)
5 Low-sensitivity photodiode 5a (low-sensitivity photodiode) n-type impurity layer 6 High-sensitivity photodiode 6a (high-sensitivity photodiode) n-type impurity layer 7 Inter-photodiode element isolation region 8 Opening 9 Light-shielding film 11 Gate insulating film 12 p ⁺ -type impurity layer 15 silicon oxide film 17 p-type well 18 semiconductor substrate 19 light 30 pixel 40, 41 vertical transfer electrode 42 photodiode 42a n-type impurity layer 51 solid-state imaging device 52 drive signal generator 53 output signal processor 54 storage Device 55 Display device 56 Transmission device 57 Television 65 Drive unit 66 Horizontal CCD unit 67 Amplifier circuit unit

Claims (13)

(A) adding a second conductivity type impurity opposite to the first conductivity type from the main surface of the first conductivity type semiconductor substrate to form a second conductivity type well;
(B) forming a plurality of first conductivity type vertical CCD channels meandering in the column direction so as to leave a rhomboid pixel region in a honeycomb shape in the well;
(C) forming a plurality of vertical transfer electrodes so as to cover above the plurality of vertical CCD channels;
(D) using the vertical transfer electrode as a part of a mask and implanting ions of a first conductivity type into a pixel region in the well from a first direction intersecting a normal direction of the main surface; Forming first and second impurity layers in each pixel region;
(E) forming a second conductivity type separation impurity layer between the first and second impurity layers;
(F) Ions of a second conductivity type are implanted into the well from a second direction intersecting with the normal direction of the main surface, so that the first, second and isolation impurity layers are formed above the well. And a step of forming an impurity layer for embedding of the second conductivity type,
The first and second impurity layers constitute two photoelectric conversion elements having different sensitivities in each pixel region,
The signal charges accumulated in the first and second impurity layers are respectively read into the first vertical transfer electrode of the plurality of vertical transfer electrodes and the vertical CCD channel below the second vertical transfer electrode. Issued,
In the step (d), when the direction of the orthogonal projection of the first direction onto the main surface is referred to as a third direction, an edge facing the pixel region of the first vertical transfer electrode and the third direction and the angle between the direction and a angle between said the edge facing the pixel area of the second vertical transfer electrodes third direction equal,
In the step (f), when an orthogonal projection direction of the second direction onto the main surface is referred to as a fourth direction, an edge facing the pixel region of the first vertical transfer electrode and the fourth direction A method of manufacturing a solid-state imaging device, wherein an angle formed by a direction is equal to an angle formed by an edge of the second vertical transfer electrode facing the pixel region and the fourth direction. In the step (d), ion implantation is performed so that the first and second impurity layers enter below the first and second vertical transfer electrodes, respectively. Ion implantation is performed so that the impurity layer does not enter below the first and second vertical transfer electrodes, and the two read voltages for reading the signal charges accumulated in the first and second impurity layers are made equal. The manufacturing method of the solid-state image sensor of Claim 1.   In the step (d), ion implantation is performed so that the first and second impurity layers do not enter below the first and second vertical transfer electrodes, respectively. In the step (f), the implantation is performed. Ion implantation is performed so that the impurity layer for use enters the lower part of the first and second vertical transfer electrodes, and blooming at the time of reading the signal charges accumulated in the first and second impurity layers is suppressed. Item 2. A method for manufacturing a solid-state imaging device according to Item 1.   4. The method of manufacturing a solid-state imaging device according to claim 1, wherein a direction in which the first and second vertical transfer electrodes extend as a whole and the third direction are parallel. 5.   5. The method for manufacturing a solid-state imaging device according to claim 1, wherein a direction in which the first and second vertical transfer electrodes extend as a whole and the fourth direction are parallel to each other.   The method for manufacturing a solid-state imaging element according to claim 1, wherein the third direction and the fourth direction are opposite to each other.   The method for manufacturing a solid-state imaging device according to claim 1, wherein an angle formed by the first direction and a normal direction of the semiconductor substrate is 3 ° to 28 °.   The method for manufacturing a solid-state imaging device according to claim 1, wherein an angle formed between the second direction and a normal direction of the semiconductor substrate is 3 ° to 28 °.   The method for manufacturing a solid-state imaging device according to claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type. Provided at a plurality of rhombus-shaped pixel regions arranged in a honeycomb direction in the row direction and the column direction, a plurality of vertical transfer channels arranged along the pixel region in the column direction, and ends of the plurality of vertical transfer channels A semiconductor substrate comprising a horizontal transfer channel;
A plurality of vertical transfer electrodes formed above the plurality of vertical transfer channels;
A plurality of horizontal transfer electrodes formed above the horizontal transfer channel ;
The pixel region has a first impurity layer of a first conductivity type constituting a first photoelectric conversion element having a relatively high sensitivity and a first conductivity constituting a second photoelectric conversion element having a relatively low sensitivity. A second impurity layer of a type, and a buried impurity layer of a second conductivity type opposite to the first conductivity type, formed above the first and second impurity layers,
The first impurity layer is formed in a region including a region below the first electrode that is a readout electrode of the first photoelectric conversion element among the plurality of vertical transfer electrodes,
The second impurity layer is formed in a region including a region below the second electrode that is a readout electrode of the second photoelectric conversion element among the plurality of vertical transfer electrodes,
The burying impurity layer is formed in a region not including a region below the first and second electrodes,
In the first and second impurity layers, the first conductivity type impurity is ion-implanted from a first direction intersecting a normal direction of a main surface of the semiconductor substrate. When the direction of the orthogonal projection onto the main surface in the direction of the third direction is the third direction, the angle formed by the edge of the first electrode facing the pixel region and the third direction, and the second electrode Are formed by equalizing the angle formed between the edge facing the pixel region and the third direction,
The burying impurity layer ion-implants the second conductivity type impurity from a second direction intersecting a normal direction of the main surface of the semiconductor substrate. In the ion implantation, the impurity layer in the second direction is implanted. When the direction of the orthogonal projection onto the main surface is the fourth direction, the angle formed between the edge facing the pixel region of the first electrode and the fourth direction, and the pixel region of the second electrode Formed by equalizing the angle between the facing edge and the fourth direction;
The first and second photoelectric conversion elements have a similar impurity distribution profile for each readout electrode,
A solid-state imaging device in which a read voltage of the first photoelectric conversion element is equal to a read voltage of the second photoelectric conversion element.   The solid-state imaging device according to claim 10, wherein the first conductivity type is n-type and the second conductivity type is p-type. Provided at a plurality of rhombus-shaped pixel regions arranged in a honeycomb direction in the row direction and the column direction, a plurality of vertical transfer channels arranged along the pixel region in the column direction, and ends of the plurality of vertical transfer channels A semiconductor substrate comprising a horizontal transfer channel;
A plurality of vertical transfer electrodes formed above the plurality of vertical transfer channels;
A plurality of horizontal transfer electrodes formed above the horizontal transfer channel ;
The pixel region has a first impurity layer of a first conductivity type constituting a first photoelectric conversion element having a relatively high sensitivity and a first conductivity constituting a second photoelectric conversion element having a relatively low sensitivity. A second impurity layer of a type, and a buried impurity layer of a second conductivity type opposite to the first conductivity type, formed above the first and second impurity layers,
The first impurity layer is formed in a region not including a region below the first electrode that is a readout electrode of the first photoelectric conversion element among the plurality of vertical transfer electrodes.
The second impurity layer is formed in a region not including a region below the second electrode which is a readout electrode of the second photoelectric conversion element among the plurality of vertical transfer electrodes.
The burying impurity layer is formed in a region including a region below the first electrode and a region below the second electrode,
In the first and second impurity layers, the first conductivity type impurity is ion-implanted from a first direction intersecting a normal direction of a main surface of the semiconductor substrate. When the direction of the orthogonal projection onto the main surface in the direction of the third direction is the third direction, the angle formed by the edge of the first electrode facing the pixel region and the third direction, and the second electrode Are formed by equalizing the angle formed between the edge facing the pixel region and the third direction,
The burying impurity layer ion-implants the second conductivity type impurity from a second direction intersecting a normal direction of the main surface of the semiconductor substrate. In the ion implantation, the impurity layer in the second direction is implanted. When the direction of the orthogonal projection onto the main surface is the fourth direction, the angle formed between the edge facing the pixel region of the first electrode and the fourth direction, and the pixel region of the second electrode Formed by equalizing the angle between the facing edge and the fourth direction;
The first and second photoelectric conversion elements have a similar impurity distribution profile for each readout electrode,
A solid-state imaging device capable of suppressing blooming during charge reading of the first and second photoelectric conversion elements.   The solid-state imaging device according to claim 12, wherein the first conductivity type is n-type and the second conductivity type is p-type.

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