JPS6190255U - - Google Patents
Info
- Publication number
- JPS6190255U JPS6190255U JP17601084U JP17601084U JPS6190255U JP S6190255 U JPS6190255 U JP S6190255U JP 17601084 U JP17601084 U JP 17601084U JP 17601084 U JP17601084 U JP 17601084U JP S6190255 U JPS6190255 U JP S6190255U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- sealed
- external lead
- ceramic substrate
- ceramic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 10
- 239000000919 ceramic Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 5
- 239000011521 glass Substances 0.000 claims description 2
- 238000002844 melting Methods 0.000 claims description 2
- 238000005452 bending Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第１図はＬＣＣ型半導体装置とコンパチな従来
のガラス封止型半導体装置の側面図、第２図は同
じく斜視図を示す。第３図、第４図は本考案の実
施例のＬＣＣ型半導体装置とコンパチなど本考案
に基づく、セラミツク基板底面に凹部を設けたガ
ラス封止型半導体装置の実施例を示す断面図、第
５図は同じく斜視図を示す。第６図は、本考案の
実施例のＬＣＣ型半導体装置とコンパチな本考案
に基づくセラミツク基体１、コーナ部に鈍角部の
凹部を設けたガラス封止型半導体装置の実施例を
示す断面図、第７図は同じく斜視図を示す。 なお図において、１…セラミツク基体、２…低
融点ガラス、３…外部リード、４…セラミツクキ
ヤツプ、５，１５…リード曲がり防止用凹部、６
…半導体素子。
のガラス封止型半導体装置の側面図、第２図は同
じく斜視図を示す。第３図、第４図は本考案の実
施例のＬＣＣ型半導体装置とコンパチなど本考案
に基づく、セラミツク基板底面に凹部を設けたガ
ラス封止型半導体装置の実施例を示す断面図、第
５図は同じく斜視図を示す。第６図は、本考案の
実施例のＬＣＣ型半導体装置とコンパチな本考案
に基づくセラミツク基体１、コーナ部に鈍角部の
凹部を設けたガラス封止型半導体装置の実施例を
示す断面図、第７図は同じく斜視図を示す。 なお図において、１…セラミツク基体、２…低
融点ガラス、３…外部リード、４…セラミツクキ
ヤツプ、５，１５…リード曲がり防止用凹部、６
…半導体素子。
Claims (1)
- セラミツク基板に低融点ガラスを介して外部リ
ードならびにセラミツクキヤツプが封着され、か
つ前記外部リードが前記セラミツク基体の側面か
ら底面に折り曲げられた形状のガラス封止型半導
体装置において、前記セラミツク基体底面に凹部
を有し、前記外部リードの一部が前記凹部に収納
されていることを特徴とするガラン封止型半導体
装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17601084U JPS6190255U (ja) | 1984-11-20 | 1984-11-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17601084U JPS6190255U (ja) | 1984-11-20 | 1984-11-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6190255U true JPS6190255U (ja) | 1986-06-12 |
Family
ID=30733608
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17601084U Pending JPS6190255U (ja) | 1984-11-20 | 1984-11-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6190255U (ja) |
-
1984
- 1984-11-20 JP JP17601084U patent/JPS6190255U/ja active Pending