JPS6189641A - Manufacture of hybrid integrated circuit - Google Patents
Manufacture of hybrid integrated circuitInfo
- Publication number
- JPS6189641A JPS6189641A JP59211622A JP21162284A JPS6189641A JP S6189641 A JPS6189641 A JP S6189641A JP 59211622 A JP59211622 A JP 59211622A JP 21162284 A JP21162284 A JP 21162284A JP S6189641 A JPS6189641 A JP S6189641A
- Authority
- JP
- Japan
- Prior art keywords
- wire
- bonding
- hybrid integrated
- integrated circuit
- thick film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
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- H01L2224/48505—Material at the bonding interface
- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
- H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
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- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/85444—Gold (Au) as principal constituent
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
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- H01L2924/14—Integrated circuits
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
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- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、混成集積回路の製造方法に係り、特に、ボン
ディングワイヤの転倒を防止し、信頼性の高い混成集積
回路を製造する方法に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a hybrid integrated circuit, and particularly to a method for manufacturing a highly reliable hybrid integrated circuit by preventing falling of bonding wires. It is.
〔従来技術〕、。[Prior art].
近年、半導体装置の分野では、高集積化、高密度化の傾
向にあシ、その進歩には目ざましいものがある。In recent years, there has been a trend toward higher integration and higher density in the field of semiconductor devices, and the progress has been remarkable.
例えば、厚膜混成集積回路は、第13図及び第14図(
第13図は第14図のbl + bl断面図)K示す如
く、基板1上に厚膜導体パターン22よび半導体チップ
3を配設し、これらの間をワイヤビンディング法によシ
ミ気的に接続したものであるが、メンディングツ4ツド
4は、仙の配線部と同様に、厚膜導体パターンとして平
面的に形成されていた。しかしながら、装置の高密度化
が進むにつれて、厚膜導体・ぐターンが微細化すると共
に、ワイヤダンディングを必要とする箇所も増大する一
方であり、チップ1個当り、50〜150ピン程度のワ
イヤダンディングが必要となってきている。For example, thick film hybrid integrated circuits are shown in FIGS. 13 and 14 (
FIG. 13 is a cross-sectional view of bl + bl in FIG. 14) As shown in FIG. However, the mending portion 4 was formed in a planar manner as a thick film conductor pattern, similar to the wiring portion at the back. However, as devices become more densely packed, thick film conductors and wires become finer, and the number of locations that require wire dangling also increases. Danding is becoming necessary.
このように、ノ臂ターンの微細化が進むにつれて当然の
ことながら、?ンディングノクツドの間隔も狭くなり、
デンディングツーイヤ間の間隔も小さくなることから、
ワイヤ間の接触あるいは、第15図に示す如く、ワイヤ
5と他の配線層6とのWj Qシてよるショート不良の
発生が大きな間1追となっている。In this way, as the no-arm turn becomes finer, it is natural that ? The spacing between the landing holes is also narrower,
Since the spacing between the dending and ear is also smaller,
Occurrence of short-circuit defects due to contact between wires or Wj Q-shape between the wire 5 and another wiring layer 6 as shown in FIG. 15 is a major problem.
不発明は、前記実情に沼みてなされたもので、ボンディ
ングワイヤによるショート不良の発生を防さ゛、信穣性
の冒い温成集、積回路を提供することを目的とする。The present invention was made in consideration of the above-mentioned circumstances, and aims to prevent the occurrence of short-circuit defects caused by bonding wires and to provide a thermally integrated circuit with reduced reliability.
そこで、本発明では、基板上に形成されたワイヤゼンデ
ィングノjンドの近傍にワイヤの+2 tll 全防止
するためのガードとして絶縁性の突起を形成するように
している。Therefore, in the present invention, an insulating protrusion is formed near the wire ending node formed on the substrate as a guard to completely prevent the wire from flowing.
この突起は、ワイヤ間の接触防止用としてはボンディン
グエリア(テンプイングツ9ノド上)の両サイドに形t
jkされる。These protrusions are designed to prevent contact between wires.
Being jked.
また、チップと基板上のビンディング・ぐラドとのIH
jを通る他の配線層(基板上の導体・ぞターン)に、ボ
ンディングワイヤが接触するのを防ぐだめノ用途には、
ボンディングエリアから半導体チップ請i:τ寄った部
分に突起が形成される。In addition, IH between the chip and the binding/glad on the board
In order to prevent the bonding wire from coming into contact with other wiring layers (conductors on the board, etc.) that pass through the wire,
A protrusion is formed at a portion of the semiconductor chip that is a distance away from the bonding area.
このように、力゛−1・゛としての突起の存在にエリ・
ボンディングワイヤが転倒した場合も、両サイドのガー
ドに支えられて耐接するワイヤに接・ユニすることはな
い。In this way, the existence of the protrusion as force ゛-1.
Even if the bonding wire falls over, it is supported by the guards on both sides and will not come into contact with the contact-resistant wire.
マタ、ボンディングエリアから半導体チップ91.jに
寄った部分に形成された突起は、ボンディングワイヤの
転倒を下から支え、基板上の他の配線ル)とワイヤが接
触するのを防ぐ。From the bonding area to the semiconductor chip 91. The protrusion formed on the portion closer to j supports the bonding wire from falling from below and prevents the wire from coming into contact with other wires on the board.
以下、本発明の実施例について、図面を参1)べしつつ
詳細に説明する。Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
これは、厚膜混成集積回路の一部を示すもので、第1図
および第2図(第1図は第2図のA −A Ib’f面
図)に示す叩く、絶縁性のセラミック基板11上に形成
された厚膜導体/lターン12のゴンデイングパッドB
P上に2つのワイヤ転倒防止用ガード13を配設し、ボ
ンディングワイヤ15の両サイドを、囲むようにしたも
のである。This shows a part of a thick film hybrid integrated circuit, and is made of an insulating ceramic substrate shown in Figures 1 and 2 (Figure 1 is a view from A-A Ib'f in Figure 2). Thick film conductor formed on 11/gonding pad B of l-turn 12
Two wire fall prevention guards 13 are disposed on P to surround both sides of the bonding wire 15.
この厚膜混成集積回路の製造に際しては、1ず、第3図
に示す如く、通常の方法で、厚さ1,61のセラミック
基板11上に、ボンディング・ンット’BPを含む膜厚
約4〜5μmの厚膜導体・9ターン12を形成する。In manufacturing this thick film hybrid integrated circuit, first, as shown in FIG. A 5 μm thick film conductor with 9 turns 12 is formed.
次いで、スクリーン印、制により、第4図に示す如く、
スクリーン印刷法により、ワイヤ転倒防止用ガード13
として、厚さ約10〜20μ?nの・、色縁住の突起を
形成する。(7はスクリーン、8はスキージ、9はエポ
キシ(至)l旨悶−ストである。)この後、所定の半導
体チップ14を該セラミック基板l上・1こダイデンデ
ィングし、更に、前記ゴンディングパノドBP上のワイ
ヤー耘倒防止用ガード130間にボンディングワイヤ1
5の先艶がくるように、第5図および第6図(第50は
第6(2)のB−B:j、’j7面図)に示す如く、ワ
イヤデ/ディング?行ない、直径25μh1の金ワイヤ
を結線する。Next, as shown in Figure 4, by screen marking,
Wire fall prevention guard 13 made by screen printing method
The thickness is approximately 10-20μ? n., forming protrusions with colored edges. (7 is a screen, 8 is a squeegee, and 9 is an epoxy paste.) After that, a predetermined semiconductor chip 14 is die-dended once on the ceramic substrate, and then the Bonding wire 1 between wire fall prevention guard 130 on panod BP
As shown in Fig. 5 and Fig. 6 (Fig. 50 is the 7th view of B-B:j,'j of Fig. 6 (2)), wire ending/ding is applied so that the tip of No. 5 is glossy. Then, a gold wire with a diameter of 25 μh1 was connected.
このようにして、第1図2よび第2[凶に示した厚6S
混成集積回路が形成される。なお、第3図乃至第6図は
第1図および第2図の要部拡大図である。壕だ、これら
の図においては、1個のポンプイングツfソドBP の
みしか示していないが、実際はセンターピッチ200μ
m1パツドサイズ100 AmDで、1チ:/f当91
50個のd?7デイング・ぐラドが配設されている。In this way, the thickness shown in FIG.
A hybrid integrated circuit is formed. Note that FIGS. 3 to 6 are enlarged views of the main parts of FIGS. 1 and 2. In these diagrams, only one pumping unit is shown, but in reality it has a center pitch of 200μ.
m1 pad size 100 AmD, 1ch:/f 91
50 d's? There are 7 Deing Grads installed.
このようにワイヤ転倒防止用ガードが配設されているた
め、本発明実施例の厚膜混成集積回路;・ま、ワイヤ間
のショート不良が防止され、極めて信顕性が高い。Since the wire fall prevention guard is provided in this manner, the thick film hybrid integrated circuit according to the embodiment of the present invention prevents short-circuit defects between the wires and has extremely high reliability.
また、本発明の他の実施例としては、第7図2よび第8
図(第7図は第8図のa−a断面図)を示す如く、ワイ
ヤのタレ防止用ガード23として、ポンプイングツ卆ツ
ドBP’上のチップ側の娼部に絶縁性の突起を設けた厚
膜混成集積回路かある。これは、半導体チップ24とゲ
ンディングノヤノドBP’との間に他の配線層26が通
っている場合に、ワイヤ25が該配線層26に接触する
のを防止するのに効果的である。Further, as other embodiments of the present invention, FIGS.
As shown in FIG. 7 (FIG. 7 is a sectional view taken along line a-a in FIG. 8), as a guard 23 for preventing wire sag, an insulating protrusion is provided on the chip-side protrusion on the pumping tube BP'. There are membrane hybrid integrated circuits. This is effective in preventing the wires 25 from coming into contact with another wiring layer 26 when it passes between the semiconductor chip 24 and the wiring node BP'.
このワイヤのタレ防止用ガード23は、第9囚および第
10図に要部拡大図(第9図は第10区のb−b断面図
)を示す如く、絶縁性のセラミノり基板21上に形成さ
れた厚膜導体パターン22の一部であるボンディングノ
クツドBP’上へのワイヤのボンディング位置すなわち
ワイヤの先端位置かられずかに半導体チップ24側へ離
間した位置に厚さ10〜20μmの突起として設けられ
る。This wire sagging prevention guard 23 is mounted on an insulating ceramino substrate 21, as shown in enlarged views of main parts in Figures 9 and 10 (Figure 9 is a bb-b sectional view of section 10). A protrusion with a thickness of 10 to 20 μm is formed on the bonding node BP′, which is a part of the formed thick film conductor pattern 22, at a position slightly away from the bonding position of the wire, that is, the tip position of the wire, toward the semiconductor chip 24 side. It is established as
この厚膜混成集積回路の形成にあたっては、前述のワイ
ヤの転倒防止用ガードを設ける場合と同様に半導体チッ
プを載置する工程すなわちダイデンディング工程に先立
ち、スクリーン印刷法等によって、タレ防止用が−ド2
3を形成する工程を付加すればよく、他は、通常の方法
によればよい。In forming this thick film hybrid integrated circuit, prior to the step of mounting the semiconductor chip, that is, the die-dending step, similar to the case of providing a guard to prevent wires from falling over, a guard to prevent sagging is applied using a screen printing method or the like. Do 2
3 may be added, and the other steps may be carried out by ordinary methods.
この厚膜混成集積回路によれば、ワイヤと他の配faE
とのショート不良を防止することができる。According to this thick film hybrid integrated circuit, wires and other
It is possible to prevent short-circuit defects.
なお、これら2つの実施例においては、ワイヤの転倒防
止用ガードとタレ防止用ガードとを別々に設けたが、第
11図および第12図に示す如く、(第11図は第12
図のA’−A’断面図)コの字状の突起31を形成し、
両方の機能を付与することにより、更に信頼性の高い厚
膜混成集積回路を得ることが可能となる。In these two embodiments, the guard for preventing the wire from falling over and the guard for preventing the wire from sagging were provided separately, but as shown in FIGS. 11 and 12 (FIG.
A′-A′ cross-sectional view of the figure) A U-shaped protrusion 31 is formed,
By providing both functions, it becomes possible to obtain a thick film hybrid integrated circuit with even higher reliability.
また、突起の形状としては、適宜変形可能であり1、方
形のみならず円形、三角膝等でも良いことは言うまでも
ない。Further, the shape of the protrusion can be modified as appropriate1, and it goes without saying that it may be not only square but also circular, triangular, etc.
更にまた、これらガードとしてのη色P、!住の栄起を
形成するに際し、実施例においては、回路・をターン形
成後に別工程として行なったが、多層基板の場合は層間
絶縁膜の形成時に同一工程で行なうことも可能である。Furthermore, these η colors P as guards,! In the embodiment, the circuit was formed as a separate process after the turn formation, but in the case of a multilayer substrate, it can be performed in the same process when forming the interlayer insulating film.
該突起の位置についても、必ずしもボンディング・(ラ
ド上でなくてもよく、基板上にはみ出した状態でもよい
。The position of the protrusion does not necessarily have to be on the bonding pad, but may be in a state where it protrudes onto the substrate.
更に、実施例では回路・母ターンを厚膜法だよって形成
したが、薄膜法によって形成した場合にも適用可能であ
る。Further, in the embodiment, the circuit/mother turn is formed by a thick film method, but it is also applicable to a case where it is formed by a thin film method.
加えて、本発明は、フリップチップ、チップキャリア等
の電極)やターンにも適用可能であシ、接続用半田の流
出防止等□にも有効である。In addition, the present invention can be applied to electrodes of flip chips, chip carriers, etc. and turns, and is also effective in preventing leakage of connection solder.
以上、説明してきたように、本発明fよれば、ボンデイ
ンワイヤの先端近傍にワイヤの転倒を防止するためのガ
ードを設けているため、位(脂封止工程でl脂の圧力を
受けた場合等にも隣接ワイヤ間あるいはワイヤと他の配
線層とのショート不良を防ぐことができ、信頼性の高い
混成集積回路を侍ることが可能となる。As explained above, according to the present invention, since a guard is provided near the tip of the bonding wire to prevent the wire from falling over, In such cases, short-circuit defects between adjacent wires or between wires and other wiring layers can be prevented, and a highly reliable hybrid integrated circuit can be provided.
第1図および第2図は、本究明実施例の厚膜混成集積回
路を示す図、第3図乃至第6図は、同厚膜混成集積回路
の製造工程を示す図、第7図および第8図は不発明の他
の実施例の混成集積口1洛を示す図、第9図および第1
0図は、同混成集積回路の一部拡大図、第11図および
第12図は、更に他の実施例の混成集積回路を示す図、
第13図乃至第15図は従来例の混成集積回路を示す図
である。
l・・・基板、2・・・厚膜導体パターン、3・・・半
導体チップ、4・・・ビンディング/母ツド、5・・・
ワイヤ、6・・・21層、11・・・セラミック基板、
12・・・厚膜導体・やターン、13・・・ワイヤ転倒
防止用ガード、14・・・半導体チップ、15・・・ワ
イヤ、BP、BP’・・・ボンディングパッド、21・
・・セラミック基板、22・・・厚膜導体・母ターン、
23・・・タレ防止用ガード、241.・半導体チップ
、31・・・コの字状突起。
1(二1−
第1図 第2図
第3図 L・
P
第4図
第7図 第8図
第9図 第10図
二。
第11図 第12図
二八1 and 2 are diagrams showing a thick film hybrid integrated circuit according to an example of this research, FIGS. 3 to 6 are diagrams showing the manufacturing process of the same thick film hybrid integrated circuit, and FIGS. Fig. 8 is a diagram showing a hybrid accumulation port 1 of another embodiment of the invention, Fig. 9 and Fig. 1
FIG. 0 is a partially enlarged view of the same hybrid integrated circuit, FIGS. 11 and 12 are diagrams showing hybrid integrated circuits of still other embodiments,
13 to 15 are diagrams showing conventional hybrid integrated circuits. l...Substrate, 2...Thick film conductor pattern, 3...Semiconductor chip, 4...Binding/mother board, 5...
Wire, 6...21 layers, 11...ceramic substrate,
12... Thick film conductor/turn, 13... Wire fall prevention guard, 14... Semiconductor chip, 15... Wire, BP, BP'... Bonding pad, 21...
...Ceramic substrate, 22...Thick film conductor/mother turn,
23... Guard for preventing dripping, 241. - Semiconductor chip, 31... U-shaped projection. 1 (21- Figure 1 Figure 2 Figure 3 L/P Figure 4 Figure 7 Figure 8 Figure 9 Figure 10 Figure 2. Figure 11 Figure 12 Figure 28
Claims (1)
、これらの間をワイヤボンディング法によって接続する
ようにした混成集積回路の製造方法において、実装工程
に先立ち、配線パターン上のボンディングパッドの近傍
に、ボンディングワイヤの転倒を防止するための突起を
形成する工程を付加したことを特徴とする混成集積回路
の製造方法。In a method for manufacturing a hybrid integrated circuit in which a semiconductor chip and a wiring pattern are arranged on a substrate and these are connected by a wire bonding method, prior to the mounting process, in the vicinity of the bonding pad on the wiring pattern, A method for manufacturing a hybrid integrated circuit, comprising the additional step of forming a protrusion to prevent a bonding wire from tipping over.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59211622A JPS6189641A (en) | 1984-10-09 | 1984-10-09 | Manufacture of hybrid integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59211622A JPS6189641A (en) | 1984-10-09 | 1984-10-09 | Manufacture of hybrid integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6189641A true JPS6189641A (en) | 1986-05-07 |
Family
ID=16608815
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59211622A Pending JPS6189641A (en) | 1984-10-09 | 1984-10-09 | Manufacture of hybrid integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6189641A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02251154A (en) * | 1989-03-24 | 1990-10-08 | Ibiden Co Ltd | Electronic component mounting board |
-
1984
- 1984-10-09 JP JP59211622A patent/JPS6189641A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02251154A (en) * | 1989-03-24 | 1990-10-08 | Ibiden Co Ltd | Electronic component mounting board |
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