JPS6187425A - Time division count circuit for incremental type encoder - Google Patents

Abstract

PURPOSE:To improve the reliability and cost-down by applying time division by means of a single processing circuit to a counter processing of plural encoders to reduce the number of components. CONSTITUTION:A multiplexer MPX1 switches an address when a CPU loads a counted value of optional incremental type encoders E1-En and an address for count processing a sequence controller CT3 and accesses an RAM4. The CT3 controls the timing of each circuit, a register 5 holds once the counted value of an optional encoder and an MPX6 switches sequentially A, B and Z phase signals of the encoders E1-En. A counter processing circuit 7 discriminates whether the count is up, down or non-count based on an output value of preceding phases A, B from an RAM2 storing the output value of the phases A, B sampled by the MPX6, and the output value of the encoders E1-En, uses a counter 4 to count a value from the RAM2, and writes the value to the RAM2.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a counting circuit for an incremental encoder incorporated in industrial robots, NG machine tools, etc. The present invention relates to a time-division counting circuit for an incremental encoder, in which counting processing for each encoder is time-divided and performed by a single processing circuit, if provided.

<Background of the Invention> Conventionally, a count circuit for an incremental encoder requires one count processing circuit for each incremental encoder. For this reason, devices that use multiple encoders of this type, such as industrial robots, require a corresponding number of counting processing circuits, which increases the number of circuits, making them more complex and larger, and also reduces the number of parts. There were many inconveniences, such as a decrease in reliability and an increase in costs due to the increase in

<Object of the Invention> In order to solve the above-mentioned problems, the present invention improves reliability by time-divisionally processing the count processing circuit, which was required for each encoder, using a single processing circuit. It is an object of the present invention to provide a time-division counting circuit for an incremental encoder that can achieve miniaturization and cost reduction of the circuit.

<Configuration and Effects of the Invention> In order to achieve the above object, the time division counting circuit for an incremental encoder of the present invention samples the output values of a plurality of incremental encoders using a sampling means and stores them in a storage means. Every time the output value of the encoder is sampled, the count value of the counter is counted based on the sampled output value of the encoder and the output value of the corresponding encoder recalled from the storage means for the previous sampling. After determining whether to process up, countdown, or no count, based on the determination result, the count value for the corresponding encoder is called from the storage means to the counter and counted, and the count value after processing is is configured to be stored in the storage means.

According to the present invention, counting processing of a plurality of encoders is performed by
Since the process can be carried out in a time-sharing manner using a single processing circuit, the purpose of the invention can be achieved, such as improving reliability by reducing the number of parts, reducing costs, and further downsizing the circuit.

<Description of Embodiments> FIG. 1 shows a time division counting circuit which is an embodiment of the present invention. In the figure, multiplexer 1 is connected to CPU (Cen
tral Processing Unit;
(not shown) switches between an address at which a count value for an arbitrary incremental encoder is loaded and an address at which the sequence controller 3 performs counting processing. RAM (Random Access
ss Memory) 2 stores the output values of each of the incremental encoders E1 to En (n is an integer of 2 or more) and the count value of the up/down counter 4.

A sequence controller 3 controls the timing of each circuit. The register 5 temporarily holds the count value for an arbitrary encoder, and the multiplexer 6 sequentially switches the A-phase, B-phase, and Z-phase signals of each encoder E to En. The counter processing circuit 7 is based on the A-phase and B-phase output values of the encoder sampled by the multiplexer 6 and the A-phase and B-phase output values related to the previous sampling of the corresponding encoder called out from the RAM 2. and a determination function that determines whether the count value should be processed as count up, count down, or no count, and based on the determination result, the count value for the corresponding encoder is called from RAM 2 to counter 4 and counted and processed. It has a count processing function that writes the subsequent count value to RAM 2.

Figure 2 shows the A phase and B phase of an incremental encoder.
Each phase output is shown, and the discrimination function of the counter processing circuit 7 will be explained with reference to this figure.

In FIG. 2, arrows A and 2 indicate the rotation direction of the encoder, and 3 to f indicate time points, respectively.

Incremental encoders count up or count down at points where the human face or B phase output changes (for example, points S, d, e, and f), and if the encoder rotates in the direction of arrow A, point B When the count goes up, the count goes down at the same point b when rotating in the direction of the arrow exit. The distinction between count-up and count-down at point b can be determined by the A-phase and B-phase output values of points a and six points before and after the point b. That is, when the encoder rotates in the direction of arrow A, the A-phase output changes from logic "H" to logic rLJ, and the B-phase output changes to logic r
When maintaining HJ, the count increases, and on the other hand, when rotating in the direction of the arrow, the output of A phase changes from logic "L" to logic "I", and the output of phase B changes from logic "I". A countdown will occur if you maintain this. Similarly, d other than point b
A count up or count down is also performed for points, zero points, and one point. Although the above description has been made regarding the so-called 4-rotation processing of an encoder, the principle is exactly the same for 1x and 2x processing.

In this way, it is possible to detect whether each output value of the A phase and B phase at two time points should be processed as a countdown or a countup, and furthermore, in this case, it is possible to detect whether the output values of the A phase and B phase are both changing. If there is no count, it can also be detected that the process is a no-count process. Regarding these two time points, hereinafter, each phase output value at the previous time point will be referred to as a past value, and each phase output value at the next time point will be referred to as a current value.

In the encoder having the output characteristics shown in FIG. 2, the past values and current values of the physiognomy and B phase at the time of count up, count down, and no count are as shown in the table below.

FIG. 3 shows a specific circuit configuration of a discrimination circuit for discriminating countdown, countup, and no count. The illustrated circuit consists of three exclusive OR circuits 8, 9.1.
0 and two AND circuits 11 and 12. When counting up, the count-up output in the figure is logic 1'-[I J, and the count-down output is logic rL.
J, when counting down, the count up output or the logic rLJ, the countdown output becomes the logic "HJ", and when there is no count, both the count up output and the countdown output become the logic rLJ.This discrimination circuit is the counter processing circuit 7 in FIG. It is incorporated within.

As mentioned above, in order to perform encoder counting processing, it is not necessary to continuously monitor the A-phase and B-phase outputs, but by checking each output data at two distant points.
It is possible to determine whether the process is countdown, force 1 kund abut, or no count. In this case, the time interval between two distant points has the following limitations.

In Figure 1, it is assumed that the encoder rotates in the direction of the arrow, and if point a is a past point and f is assumed, then if the current point is point b, then the output changes of A phase and B phase are It can be understood correctly, but if it is the current point or 6 points,
Since the output change cannot be detected correctly, the discrimination circuit shown in FIG. 3 malfunctions. Therefore, the time from the past point to the current point, that is, the sampling frequency, needs to be four times or more the highest frequency of the encoder in the case of four-step processing. In addition, in the second heating process and the first heating process, the maximum frequency of the encoder is twice or more than 1 time, respectively. Therefore, when counting multiple encoders using the discrimination circuit shown in Figure 3, it is necessary to sample the A-phase and B-phase outputs of all encoders at a cycle that is four times the frequency of the encoder that rotates at the highest speed. For example, time-sharing counting processing becomes possible.

FIG. 5(a)(t)) shows the operation flow of the time-division counting circuit shown in FIG. 1. First, in step 1 of FIG. The counting process for the @th encoder El or the counting process for the second encoder Ez is sequentially executed in step 2, and the counting process for the third and subsequent encoders is sequentially executed in the same manner. In the final step 3, counting processing of the final encoder En is executed. In this case, the sampling frequency of the output signals of the encoders E1 to En is set to four times or more that of the fastest encoder. When the counting process of the encoder En of the final JF''J is completed, the process returns to step 1 again, and the counting process of the encoders E4-En is repeatedly executed in the same manner as described above.

Figure 5 (1)) shows one encoder (for example, El)
The counting processing operation for . In this case, RAM
2, each encoder E
The A-phase and B-phase output values of 1xEn and count values for each encoder are stored, respectively.

First, in step 4, the A phase and B phase of encoder El
The phase and Z phase output signals are sampled by the multiplexer 6 and input to the count processing circuit 7. In step 5, the past values of the A phase and B phase of the encoder E are loaded from the RAM 2 to the count processing circuit 7, and in step 6, the count value of the encoder El is loaded from the memory 2 to the counter 4. Ru. In the following step 7, the count processing circuit 7 calculates the A phase, B phase
Based on the current value and past value of the phase, the encoder E1 during sampling counts up, counts down,
It is determined whether there is a no count, and based on the determination result, in step 8, the count value loaded into the counter 4 is incremented, decremented, or no count processed. Then, in step 9, the current values of the physiognomy and B phase of the encoder E1 are stored in the RAM 2 as past values for the next sampling, and in the final step 10, the result of the count value by the counter 4 is stored in the RAM 2. Store.

In this way, the counting process of encoder El or the end thread,
Next, counting processing corresponding to steps 4 to 10 is also performed for encoder E2, and hereafter encoder E
Similar counting processing is performed sequentially for encoders 3 to En.

The strobes and clocks that control the operations shown in FIG. 5 in a hardware manner are managed by the sequence controller 3 shown in FIG. 1.
Do everything. Further, the multiplexer 1 and register 5 shown in FIG. 1 are for loading the count value being processed by the counter processing circuit 7 into the CPU.

In this way, the counting process of each of the encoders E1 to En can be time-divisionally processed using one processing circuit, so that reliability can be improved by reducing the number of parts, and miniaturization and cost reduction can be achieved. Also, even if the number of encoders increases, the RA
This can be easily handled by simply increasing the capacity of ~12 and the number of channels of the multiplexer 6, and operating the entire circuit at high speed.

4゜ Simplified explanation of Figure 1 (11) Figure 1 is a block diagram of a counting circuit which is an embodiment of the present invention, Figure 2 is a diagram showing the A-phase and B-phase outputs of an incremental encoder, and Figure 3. is a circuit diagram showing an example of a discrimination circuit, and Fig. 4 is a circuit diagram showing an example of a discrimination circuit.
FIG. 5 is a flowchart showing the operation of the circuit of FIG. 1, which shows phase and B-phase outputs.

2...RAM 3...Sequence controller 4...Counter 6.
...Multiplexer 7... Counter processing circuit patent applicant Tateishi Electric Co., Ltd. Figure square 2: Coee: --- Min.

Claims (1)

[Claims] A single counter, sampling means for time-divisionally sampling the output values of a plurality of incremental encoders, and storing the sampled output values of each encoder and the count value of the counter for each encoder. a count value of a counter for the corresponding encoder based on the output value of the encoder sampled by the sampling means and the output value of the corresponding encoder from the previous sampling called from the storage means; A determining means for determining whether to process count up, count down, or no count; and based on the determination result, the count value for the corresponding encoder is called from the storage means to the counter for counting processing, and the counted value after the processing is A time division counting circuit for an incremental encoder, comprising a counter processing means for storing data in a storage means.