JPH04205512A - Timer device for microcomputer - Google Patents

Abstract

PURPOSE:To reduce the circuit scale and to reduce the number of comparators down to a single counter underflow detector circuit by transferring previously the time data on a ROM to plural reload registers by a control circuit and then loading the time data to a counter every time the counter produces an underflow signal or an overflow signal. CONSTITUTION:Plural set times are recorded in a memory M and then transferred successively to the reload registers L1 and L2 with detection of an underflow or overflow state of a counter Al. Then the registers L1 and L2 transfers the set times to the counter A1 in the setting order. Thus the time data recorded to a ROM(M) are successively transferred to the counter A1. As a result, a function equivalent to a comparison register is attained with the ROM(M) of a smaller circuit constitution. At the same time, many comparators can be reduced down to a single underflow detector circuit and the freedom degree is increased for the settable comparison time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a timer device for a microcomputer, and particularly to a device capable of measuring time between a plurality of events.

[Conventional technology]

When performing speed control and phase control of a three-pole motor, etc. using a digital servo system using a microcomputer, pulse width modulation (Pulse Width M
oduration (hereinafter referred to as PWM) is performed to switch the voltage supplied to the motor. When switching voltages using this PWM method, it is necessary to generate switching signals corresponding to the rising and falling timings of the voltage.

FIG. 3 shows a conventional circuit system that uses a plurality of comparison registers, comparators, and counters to switch between three types of outputs supplied to a three-pole motor. In the figure, A is a counter that generates a reference time, X is a count clock to counter A, R1-R6 are different comparison registers, and C
1-C6 is a comparator that compares the value of counter A and the value of comparison registers R1-R6, respectively; 5t-36 is a match signal U, V obtained by the comparison of comparators Cl-C6, respectively;

W is the output signal for each terminal of the three-pole motor,
B is U based on the signal from comparator Cl-C6.

The motor control signal generation circuit for switching the outputs of v and W, data 1 to data 6 are values stored in comparison registers R1 to R6, respectively.

When the values preset in the respective comparison registers R1-R6 match the count value of the counter A, match signals 51-S6 are generated from the comparators C1-C6 corresponding to the comparison registers R1-R6, respectively. These matching signals 81~
S6 is detected as control circuit B, and these coincidence signals 81 to S
Output signals U, V, and W are generated based on 6.

FIG. 4 shows an example of an output signal for a three-pole motor.

In the figure, U, V, and W are output signals for each type of three-pole motor, t is a reference time, 5l-36 is a coincidence signal, Tl-T6 is a time for switching outputs with respect to the reference time, and each is a comparison register R1. Corresponds to *data l -data6, which is the content of -R6.

m is set, and the count value of counter A, which is counting in synchronization with count clock X, is compared with register R1-.
The count value set in R6 is connected to each comparator 01~
They are compared independently at C6, and when they match, respective match signals 5l-36 are generated from comparators C1-C6.

Based on these coincidence signals 81 to S6, motor control signal generation circuit B generates output signals U, V, and W as shown in FIG.

In this conventional example, the counter A is reset every cycle of the motor control signal, that is, at the timing of S6.

[Problem to be solved by the invention]

Since the conventional timer device for a microcomputer is configured as described above, the number of comparison times is limited by the number of comparison registers and comparators. That is, since the same number of comparison registers and comparators as the number of comparison times are required, there is a problem in that as the number of comparison times increases, the circuit size increases accordingly.

This invention was made to solve the above-mentioned problems, and its purpose is to provide a timer device for a microcomputer that can increase the degree of freedom in the number of comparison times that can be set and reduce the circuit size. do.

[Means to solve the problem]

A timer device for a microcomputer according to the present invention includes:
The control circuit transfers the time data in the ROM to multiple reload registers, and the input/output control circuit selects the value of one of these reload registers and loads it into the counter. Each time the reload register is operated and an underflow signal (or overflow signal) is generated, the values of other reload registers are selected and counted clocked alternately.

Further, as the ROM, a ROM that can be stored by the user is used.

[Effect]

A timer device for a microcomputer according to the present invention includes:
A plurality of set times are recorded in a storage device, and when a counter underflow or overflow is detected, the set times are sequentially transferred to multiple reload registers.
Furthermore, by transferring data from this reload register to the counter in the set time order, the time data recorded in the ROM is transferred to the counter sequentially.
A function equivalent to a conventional comparison register can be realized with a ROM having a smaller circuit scale, and a large number of comparators can be reduced to one counter underflow detection circuit. Also ROM
Since we have decided to use a user programmable one, the degree of freedom in the time data that can be set increases.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block configuration of a timer device for a microcomputer according to an embodiment of the present invention. In the figure, Ll
, B2 are different reload registers, A1 is a counter, SA is an underflow signal of counter At, B2
is reload register LL, L2 input/output control circuit, B
2 is a control signal for selecting reload registers Ll and L2 and loading time data stored in ROM M from reload register L1 or B2 to counter A1 immediately before counter A1 starts counting, and M stores time data that can record set time. ROM, dataA-d for
ataF is a control circuit that generates output signals U, V, and W based on the time data SA stored in ROM M, and transfers time data dataA to data F stored in ROM M to reload register Ll or B2. It is.

FIG. 2 shows a timing chart of the operation of the embodiment shown in FIG. In the figure, U, V, W are output signals,
t is the reference time, T1 to T6 are the generation points of the switching time necessary to obtain the target output waveform, SA is the underflow signal of the counter A1, and N is the count value of the counter Al. At this time, time data dataA-dataF are T2-Tl, T3-T2 . T4-T3. T5-T
4. Set a count value corresponding to the time T6-T5.

Next, the operation will be explained. In FIG. 1, first, the control circuit Bl inputs time data dat stored in the ROM.
Transfer aA and dataB to reload registers Ll and L2 in advance, respectively. Next, immediately before the counter At starts counting, the input/output control circuit B2 loads dataA from the reload register L1 to the counter A1.

The counter Al counts down in synchronization with the count clock X, generates an underflow signal SA when the counter Al underflows, and generates output signals U, V, and W by the control circuit Bl.

After the input/output control circuit B2 loads dataA from the reload register Ll to the counter At, the control circuit Bl transfers aataC stored in the ROM M to the reload register Ll using the output signal U,
This is done in parallel with the V and W generation work.

Next, at the same time that the counter A1 underflows, the input/output control circuit B2 loads the next time data dataB, which is waiting in the reload register L2, to the counter A1, and the control circuit B1 loads the next time data dataB to the reload register L2.
Transfer dataD from OM M. Counter A1 is counted down and the next time it underflows,
The input/output control circuit B2 outputs dat from the reload register Ll.
Load aC into counter Al. Similarly, at the next underflow, the input/output control circuit B2 loads the value of the reload register L2 into the counter A1.

In this way, in this embodiment, the control circuit B1 controls the ROM
M time data reload register Ll.

The input/output control circuit B2 selects the value of one of the reload registers L1 or B2 and loads it into the counter Al.

Next, the counter A1 is operated, and each time an underflow signal (or overflow signal) is generated, the value of the other reload register L1 or B2 is selected and alternately loaded into the counter A1. This allows the next setting time to be quickly set on the counter A1. It is also possible to introduce new time data from the storage device into the vacant reload register. Therefore, the function equivalent to the conventional comparison register can be realized using a ROM with a smaller circuit size.
Furthermore, the number of comparators can be reduced to one underflow detection circuit of a counter, and since the ROM setting time can be recorded, the degree of freedom in setting time data can be increased.

Incidentally, in the above embodiment, the data may be set so as to generate a fag when a downcurrant overflow occurs, and the same effect as in the above embodiment can be obtained.

〔Effect of the invention〕

As described above, according to the timer device for a microcomputer according to the present invention, the control circuit transfers the time data of the ROM to a plurality of reload registers, and the input/output control circuit transfers the time data of the ROM to a plurality of reload registers. Select one value and load it into the counter, then operate the counter, and every time an underflow or overflow signal is generated, select the value of the other reload register and load it into the counter alternately. Therefore, the function equivalent to a conventional comparison register can be realized with a smaller ROM circuit, and the number of comparators can be reduced to one underflow detection circuit of a counter. Furthermore, since the ROM setting time can be recorded, there is an effect that the degree of freedom in setting time data can be increased.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a timer device for a microcomputer according to an embodiment of the present invention. FIG. 2 shows an example of the output signals output to each terminal of the three-pole motor of the microcomputer timer device according to the embodiment of FIG. 1, and shows timings for switching output signals and time data between the timings. It is a timing chart figure. FIG. 3 is a block diagram showing the configuration of a conventional microcomputer timer device, and FIG. 4 shows an example of the output to each terminal of the three-pole motor of the conventional microcomputer timer device shown in FIG. FIG. 4 is a timing chart showing the timing for switching the output. In the figure, A and AI are counters, R1-R6 are comparison registers, C1-C6 are comparators, 51-36, SA are match signals from comparators Cl-C6, and U. v, W are output signals for the three-pole motor, B, B1
, B2 is a control circuit, Ll, L2 is a reload register, M
is a ROM that stores time data, data l −
data 6 and dataA-dataF are time data, t is a reference time, TI-T6 is a time for switching the output with respect to the reference time, and N is a count value of the counter A1. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A timer device that measures the time between multiple events includes a reload register that can set at least two sets of initial values for the timer, and one of the at least two sets of initial values set in the reload register. , a timer circuit that counts down or counts up this value in synchronization with a timer clock and outputs a flag when the count value reaches a specific fixed value, and a plurality of timer circuits that record in a storage device when the flag is detected. a first control means for sequentially transferring one of the timer initial value groups to the reload register;
a second control means for selecting the reload register and sequentially loading the one transferred from the storage device among the at least two sets of initial values in the reload register to the timer; A timer device for a microcomputer, characterized by comprising: