JPS6184954U - - Google Patents
Info
- Publication number
- JPS6184954U JPS6184954U JP7339485U JP7339485U JPS6184954U JP S6184954 U JPS6184954 U JP S6184954U JP 7339485 U JP7339485 U JP 7339485U JP 7339485 U JP7339485 U JP 7339485U JP S6184954 U JPS6184954 U JP S6184954U
- Authority
- JP
- Japan
- Prior art keywords
- request signal
- output
- processor
- bus line
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 4
- 125000004122 cyclic group Chemical group 0.000 description 1
Landscapes
- Bus Control (AREA)
- Multi Processors (AREA)
Description
第１図はこの考案の一実施例のシステム構成図
、第２図はコントローラ４の詳細な構成図、第３
図はプロセツサ１〜３のサイクリツクな優先順位
を示す図、第４図はこの実施例の各種事例を説明
する図である。
１〜３…プロセツサ、４…コントローラ、５…
コモンＲＡＭ、６〜８…シーケンス制御回路、６
Ａ〜８Ａ…ネクストシーケンス制御ゲート、６Ｂ
〜８Ｂ…ネクストシーケンス制御フリツプフロツ
プ、１２〜１４…トリガバスバツフアゲート回路
、ＡＢ，ＤＢ…共通バスライン。
Fig. 1 is a system configuration diagram of an embodiment of this invention, Fig. 2 is a detailed configuration diagram of the controller 4, and Fig. 3 is a detailed configuration diagram of the controller 4.
This figure shows the cyclic priority order of processors 1 to 3, and FIG. 4 is a diagram explaining various examples of this embodiment. 1 to 3...Processor, 4...Controller, 5...
Common RAM, 6 to 8...Sequence control circuit, 6
A~8A...Next sequence control gate, 6B
~8B...Next sequence control flip-flop, 12-14...Trigger bus buffer gate circuit, AB, DB...Common bus line.
Claims (1)
ンを介して共用装置と接続され、上記各プロセツ
サからのリクエスト信号を所定の優先順位に従つ
て択一的に選択して上共用装置をアクセスするた
めの第１、第２、第３のシーケンス制御回路から
成る共通バスライン占有制御装置であつて、 夫々のシーケンス制御回路はバスライン占有状
態をラツチしシステムクロツクにより駆動される
Ｊ−Ｋフリツプフロツプを有し、 ｍ−１番目（ｍ＝１，２，３；ただしｍ＝１の
ときは３番目）のシーケンス制御回路は、 ｍ番目のシーケンス制御回路のＪ−Ｋフリツプ
フロツプからの出力とｍ＋１番目（ただしｍ＝
３のときは１番目）のプロセツサからのリクエス
ト信号が入力され、出力が“０”でリクエスト
信号が“１”のときに“１”を出力する第１のゲ
ートと、 この第１のゲートの出力とｍ−１番号（ただし
ｍ＝１のときは３番目）のプロセツサからのリク
エスト信号が入力され、第１のゲート出力が“０
”でｍ−１番目のリクエスト信号が“１”のとき
に“１”を出力する第２のゲートと、 ｍ＋１番目（ただしｍ＝３のときは１番目）の
プロセツサからのリクエスト信号とｍ番目のプロ
セツサからのリクエスト信号が入力され、少なく
ともどちらか一方が“１”のとき“１”が出力さ
れる第３のゲートと を備え、上記第２のゲートの出力を上記Ｊ−Ｋフ
リツプフロツプのＪ端子へ、上記第３のゲートの
出力をＫ端子に入力し、且つこのＪ−Ｋフリツプ
フロツプのＱ出力をｍ−１番目のプロセツサのバ
スライン占有要求信号とすることを特徴とする共
通バスライン占有制御装置。[Claims for Utility Model Registration] First, second, and third processors are connected to a shared device via a common bus line, and request signals from each of the processors are selectively received in accordance with a predetermined priority order. A common bus line occupancy control device consisting of first, second, and third sequence control circuits for selectively accessing the upper shared device, each sequence control circuit latching the bus line occupancy state and controlling the system clock. The m-1st (m=1, 2, 3; however, when m=1, the 3rd) sequence control circuit has a J-K flip-flop driven by the J of the m-th sequence control circuit. -The output from the K flip-flop and the m+1st (where m=
3, the request signal from the first processor is input, and the first gate outputs "1" when the output is "0" and the request signal is "1"; The output and the request signal from the processor numbered m-1 (however, the third when m=1) are input, and the first gate output becomes “0”.
”, the second gate outputs “1” when the m-1st request signal is “1”, the request signal from the m+1st (however, the first when m=3) processor, and the mth a third gate into which a request signal from the processor is input and which outputs "1" when at least one of the two gates is "1"; A common bus line occupancy system characterized in that the output of the third gate is input to the K terminal, and the Q output of the JK flip-flop is used as a bus line occupancy request signal for the m-1th processor. Control device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7339485U JPS6137084Y2 (en) | 1985-05-17 | 1985-05-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7339485U JPS6137084Y2 (en) | 1985-05-17 | 1985-05-17 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6184954U true JPS6184954U (en) | 1986-06-04 |
| JPS6137084Y2 JPS6137084Y2 (en) | 1986-10-27 |
Family
ID=30612716
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7339485U Expired JPS6137084Y2 (en) | 1985-05-17 | 1985-05-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6137084Y2 (en) |
-
1985
- 1985-05-17 JP JP7339485U patent/JPS6137084Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6137084Y2 (en) | 1986-10-27 |
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