JPS6184070A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6184070A JPS6184070A JP59206081A JP20608184A JPS6184070A JP S6184070 A JPS6184070 A JP S6184070A JP 59206081 A JP59206081 A JP 59206081A JP 20608184 A JP20608184 A JP 20608184A JP S6184070 A JPS6184070 A JP S6184070A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- layer
- type
- single crystal
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 63
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 14
- 239000013078 crystal Substances 0.000 claims abstract description 12
- UIUXUFNYAYAMOE-UHFFFAOYSA-N methylsilane Chemical compound [SiH3]C UIUXUFNYAYAMOE-UHFFFAOYSA-N 0.000 claims abstract description 12
- 238000006243 chemical reaction Methods 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 6
- 229910000077 silane Inorganic materials 0.000 claims description 6
- 238000010574 gas phase reaction Methods 0.000 claims description 3
- 230000001747 exhibiting effect Effects 0.000 claims 1
- 229910021332 silicide Inorganic materials 0.000 claims 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 11
- 239000002131 composite material Substances 0.000 abstract description 10
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 8
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 abstract description 5
- 239000011521 glass Substances 0.000 abstract description 3
- 239000003513 alkali Substances 0.000 abstract description 2
- 239000002648 laminated material Substances 0.000 abstract 2
- 230000004888 barrier function Effects 0.000 description 13
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 6
- 229910052739 hydrogen Inorganic materials 0.000 description 6
- 239000001257 hydrogen Substances 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 4
- 229910052804 chromium Inorganic materials 0.000 description 4
- 239000011651 chromium Substances 0.000 description 4
- 229910052736 halogen Inorganic materials 0.000 description 4
- 150000002367 halogens Chemical class 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- UBHZUDXTHNMNLD-UHFFFAOYSA-N dimethylsilane Chemical compound C[SiH2]C UBHZUDXTHNMNLD-UHFFFAOYSA-N 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 239000012808 vapor phase Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 239000012071 phase Substances 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 239000004215 Carbon black (E152) Substances 0.000 description 1
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 125000000217 alkyl group Chemical group 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000002585 base Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229930195733 hydrocarbon Natural products 0.000 description 1
- 150000002430 hydrocarbons Chemical class 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000002294 plasma sputter deposition Methods 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1365—Active matrix addressed cells in which the switching element is a two-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Ceramic Engineering (AREA)
- Optics & Photonics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
Abstract
Description
【発明の詳細な説明】
「発明の利用分野」
この発明は、表示素子好ましくは液晶表示パネルを設け
ることにより、マイクロコンビニーり、ワードプロセッ
サまたはテレビ等の表示部の固体化を図る固体表示装置
、イメージセンサまたは液晶プリンタに応用する非線型
特性を有する半導体装置の作製方法に関するものである
。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a solid-state display device, which aims to solidify the display part of a micro convenience store, a word processor, a television, etc. by providing a display element, preferably a liquid crystal display panel; The present invention relates to a method for manufacturing a semiconductor device having nonlinear characteristics that is applied to an image sensor or a liquid crystal printer.
「従来の技術」
固体表示パネルは各絵素を独立に制御する方式が大面積
用として有効である。このようなアクティブ素子を用い
たパネルとして、すべての画素と1=1に連結して用い
るアモルファスシリコンのみよりなるNrN接合構造の
非線型素子が知られている。しかし、この旧N接合を用
いんとしても、そのNIまたはIN接合界面がどのよう
になっているか不明であり、十分な非線型特性を得るに
至っていない。``Prior Art'' For solid-state display panels, a system in which each picture element is controlled independently is effective for large-area displays. As a panel using such an active element, a non-linear element having an NrN junction structure made of only amorphous silicon and used in 1=1 connection with all pixels is known. However, even if this old N junction is used, it is unclear what the NI or IN junction interface looks like, and sufficient nonlinear characteristics have not yet been obtained.
「発明が解決しようとする問題点」
しかし非線型素子を用いんとして、基板上にN層I層N
層をプラズマCVD法により漸次積層していっても、こ
のNT界面ではN型不純物であるリンがI型半導体層内
に混入する。またIN界面ではI型半導体とN型層との
混合N一層が界面領域にできてしまう。このような界面
での不純物および構成成分のおたがいの混合が存在する
ならば、そのV−■特性において対称性を有せしめるこ
とはまったく不可能であった。``Problems to be solved by the invention'' However, when trying to use a nonlinear element, it is necessary to
Even if the layers are gradually laminated by plasma CVD, phosphorus, which is an N-type impurity, is mixed into the I-type semiconductor layer at this NT interface. Further, at the IN interface, a mixed N layer of an I-type semiconductor and an N-type layer is formed in the interface region. If such impurities and mixing of constituent components exist at the interface, it is completely impossible to achieve symmetry in the V-■ characteristics.
「問題を解決するための手段」
本発明はかかる問題を解決するため、水素またはハロゲ
ン元素が添加された非単結晶半導体よりなる非線形素子
を用い、かつそのI型半導体中には炭素を添加したSi
−3ixC+−x(0<X4) −’Si構造を有せ
しめたことを主としている。"Means for solving the problem" In order to solve the problem, the present invention uses a nonlinear element made of a non-single crystal semiconductor to which hydrogen or a halogen element is added, and carbon is added to the I-type semiconductor. Si
-3ixC+-x (0<X4) -' The main feature is that it has a Si structure.
かかる本発明に用いる非線形素子は、1つのPIN接合
とその上下にコンタクトををする電極より構成されるダ
イオードを用いるのではなく、一対の電極とはそれぞれ
オーム接触性を有するが、逆向整流特性を構成する複合
ダイオードを有する素子よりなるもので、その代表例は
N型半導体−■型(以下真性または実質的に真性という
)半導体−N型半導体を積層して設けたNIN構造、即
ちNl接合とIN接合とが電気的に逆向きに連結され、
かつ半導体として一体化したNIN接合を有する半導体
をはじめ、その変形であるNN−N、NP−N、PIP
、PP哩またはPN−P構造を有せしめた複合ダイオー
ドである。The nonlinear element used in the present invention does not use a diode composed of a single PIN junction and electrodes that make contact above and below it, but instead uses a diode that has ohmic contact with each of the pair of electrodes but has reverse rectification characteristics. A typical example is an NIN structure in which an N-type semiconductor, a ■-type (hereinafter referred to as intrinsic or substantially intrinsic) semiconductor, and an N-type semiconductor are stacked, that is, an Nl junction. The IN junction is electrically connected in the opposite direction,
In addition to semiconductors with integrated NIN junctions, their variations such as NN-N, NP-N, and PIP
, a composite diode having a PP structure or a PN-P structure.
かかる複合ダイオードのスレッシュホールド電圧は、ダ
イオード特性を互いに逆向きに相対せしめ、そのビルド
イン(立ち上がり)電圧(しきい値)はNl接合のN型
半導体とI型半導体またはNr界面近傍での導電型を決
める微量のリン等の不純物と、エネルギバンド巾を決め
る炭素等の添加物の濃度で決めることができる。このた
め、製造プロセスを制御することにより、所望の素子の
しきい値電圧の値およびしきい値以下での電流の流れに
くさおよびしきい値以上での電流の流やすさを制御し得
る。さらに絶縁膜−半導体の界面物性を用いず、半導体
−半導体接合方式であるため、温度処理、B−T処理(
バイアス一温度)処理に対し不安定性がないという特長
を有する。The threshold voltage of such a composite diode makes the diode characteristics opposite to each other, and the build-in (rise) voltage (threshold) changes the conductivity type near the N-type semiconductor and I-type semiconductor of the Nl junction or the Nr interface. It can be determined by the concentration of impurities such as trace amounts of phosphorus, and the concentration of additives such as carbon, which determines the energy band width. Therefore, by controlling the manufacturing process, it is possible to control the value of the threshold voltage of a desired element, the difficulty of current flow below the threshold value, and the ease of current flow above the threshold value. Furthermore, since it is a semiconductor-semiconductor junction method without using the physical properties of the insulating film-semiconductor interface, temperature treatment, B-T treatment (
It has the feature that there is no instability due to processing (bias - temperature).
このため、固体表示素子である例えば液晶に対し、交流
バイアスを液晶の他方の電極リードのレベルを制御する
ことにより制御し得、階調制御も可能であるという特徴
を有する。Therefore, for a solid state display element, for example, a liquid crystal, the AC bias can be controlled by controlling the level of the other electrode lead of the liquid crystal, and gradation control is also possible.
「作用」
かかる■型半導体を5ixC+−x(0<X<1)とす
るとともに、この炭素をメタン等の炭化水素とシラン等
の珪素化合物を用いるのではなく、メチルシラン(Si
(CH:+)nlia−n n = 1〜3等で示され
るC−Si結合を分子内部に有するアルキル分子)とす
ることにより、プラズマ放電の出力を低出力化し得る。"Function" This ■-type semiconductor is made into 5ixC+-x (0<X<1), and instead of using a hydrocarbon such as methane and a silicon compound such as silane, methylsilane (Si
By using an alkyl molecule having a C--Si bond inside the molecule, such as (CH:+)nlia-n n = 1 to 3), the output of plasma discharge can be lowered.
かくすると、被膜形成時に被膜形成をプラズマでスパッ
タすることを極力少なくし得、[またはIN界面での混
合層を実質的に除去し得る。In this way, it is possible to minimize the amount of plasma sputtering during film formation, [or to substantially eliminate the mixed layer at the IN interface].
さらにメチルシランに対し、紫外光を照射した光CVD
法を用いることにより、この界面でのスパッタを完全に
除去できるため混合層を完全に除去し得る。その結果、
スレッシュホールド電圧のロット間の再現性を向上させ
得る。Furthermore, methylsilane was subjected to photo-CVD, which was irradiated with ultraviolet light.
By using this method, sputtering at this interface can be completely removed, so the mixed layer can be completely removed. the result,
Lot-to-lot reproducibility of threshold voltage can be improved.
以下に実施例に従って本発明を説明する。The present invention will be explained below according to examples.
「実施例1」 この第1図を以下に略記する。"Example 1" This FIG. 1 will be abbreviated below.
第1図(A)は実際の素子構造の縦断面図を示している
。FIG. 1(A) shows a longitudinal cross-sectional view of an actual device structure.
第1図(A)において、透光性絶縁基板として無アルカ
リガラス(20)を用いた。この上面にスバ。In FIG. 1(A), non-alkali glass (20) was used as the light-transmitting insulating substrate. Suba on this top surface.
り法または電子ビーム蒸着法により導電膜であるITO
または酸化スズ膜を0.1〜0.5 μの厚さに、さら
にこの上面に遮光用クロム(11)を300〜2500
人の厚さに同様に積層形成した。この後、透光性導電膜
(17)および遮光電極(11)よりなる第1の電極(
21)を第1のマスク■により行い、不要部を除去して
電極を形成した。ITO, which is a conductive film, is formed by a method or an electron beam evaporation method.
Alternatively, apply a tin oxide film to a thickness of 0.1 to 0.5 μm, and then apply a light-shielding chromium (11) to a thickness of 300 to 2500 μm on the top surface.
Laminated layers were similarly formed to the thickness of a person. After this, the first electrode (
Step 21) was performed using the first mask (2) to remove unnecessary portions and form electrodes.
この後、これらの全面に第2図に示す如きプラズマ気相
反応装置を用いてプラズマ気相法を行い、NIN構造を
有する水素またはハロゲン元素が添加された非単結晶半
導体よりなる複合ダイオードを形成した。即ち、図面に
おいて、ロード、アンロード(4) 、 N型半導体形
成用第1の反応系(5)、I型半導体形成用第2の反応
系(6)を有している。それぞれはドーピング系(50
)、反応炉(30)、排気系(40)を有する。Thereafter, a plasma vapor phase method is applied to these entire surfaces using a plasma vapor phase reactor as shown in Figure 2 to form a composite diode made of a non-single crystal semiconductor doped with hydrogen or halogen elements having an NIN structure. did. That is, in the drawing, it has a loading/unloading system (4), a first reaction system for forming an N-type semiconductor (5), and a second reaction system for forming an I-type semiconductor (6). Each is a doping system (50
), a reactor (30), and an exhaust system (40).
基板(20)はホルダ(IS)により予備室より第1の
反応室(1)にゲート弁(17)を開き双方を1O−b
torr以下に十分真空引きをして移設する。ここでフ
ォスヒンが添加(0,5χ)されたシランを(56)よ
り導入し、13.56MHzの高周波グロー放電を行う
ことにより、200〜350°Cに保持された基板上の
被形成面上にアモルファス構造を有する非単結晶半導体
を作る。その電気伝導度は10−5〜10− ’ (0
cm) −”c有し、50〜500 人の厚さとした。The substrate (20) opens the gate valve (17) from the preliminary chamber to the first reaction chamber (1) by the holder (IS), and both sides are connected to 1O-b.
Vacuum it sufficiently to below torr and relocate it. Here, silane to which phosphin is added (0.5χ) is introduced from (56), and by performing high-frequency glow discharge at 13.56 MHz, it is formed on the surface to be formed on the substrate maintained at 200 to 350°C. Create a non-single crystal semiconductor with an amorphous structure. Its electrical conductivity is 10-5~10-' (0
cm) -"c, with a thickness of 50 to 500 people.
さらに第1、第2の反応炉(1) 、 (3)を10−
6〜10−’torrまで、十分真空引きをした後、ゲ
ート弁(18)を開とし、基板(20)、ホルダを第2
の反応室に移設した。次に、シラン(S+mHzm+z
例えばm=Iの5iH4)を(58)より、またメチル
シラン(Silln(CHz)a−n n 〜1〜3)
を(59)より導入し、混入させた。即ちn 〜2では
HzSi (CH3) z/5il14= 175〜1
/200例えば1150(流量cc)とした。この混合
反応性気体をプラズマ反応炉(3)内に導入し、基板を
ハロゲンヒータ(63L(64)により加熱し、一対の
電極(68) 、 (68’ )に高周波電気エネルギ
を加えてプラズマ反応をさせ、■型の水素またはハロゲ
ン元素が添加された5ixC,−x(0<に<1)で示
される非単結晶半導体(第1図(A)の(13))
を0.1〜1μの厚さに、例えば0.4 μの厚さにN
型半導体上に積層して形成した。さらにこの後、第2、
第1の反応炉(3) 、 (1)を排気系(40)のタ
ーボポンプにて10−6〜10−’torrまで十分真
空引きをした。再び、基板(20)およびホルダ(IS
)を第1の反応室にゲート弁(18)を開き移設し、こ
の後再びこのゲート弁を閉じて、同様のN型半導体(1
4)をI型半導体上にアモルファス構造として50〜5
00 人の厚さに積層してNIN接合とした。Furthermore, the first and second reactors (1) and (3) are
After sufficiently evacuation to 6 to 10 torr, open the gate valve (18) and move the substrate (20) and holder to the second
was moved to the reaction chamber. Next, silane (S+mHzm+z
For example, 5iH4) with m=I from (58), and methylsilane (Silln(CHz)a-n n ~1-3)
was introduced from (59) and mixed. That is, for n ~2, HzSi (CH3) z/5il14=175~1
/200, for example, 1150 (flow rate cc). This mixed reactive gas is introduced into the plasma reactor (3), the substrate is heated by a halogen heater (63L (64)), and high frequency electric energy is applied to the pair of electrodes (68) and (68') to cause a plasma reaction. and a non-single crystal semiconductor represented by 5ixC,-x (0< to <1) to which type hydrogen or halogen elements are added ((13) in Figure 1 (A)).
N to a thickness of 0.1 to 1μ, for example 0.4μ
It was formed by laminating it on a type semiconductor. Furthermore, after this, the second
The first reactors (3) and (1) were sufficiently evacuated to 10-6 to 10-'torr using a turbo pump in the exhaust system (40). Again, the substrate (20) and the holder (IS
) into the first reaction chamber by opening the gate valve (18), then closing this gate valve again, and transferring the same N-type semiconductor (18) to the first reaction chamber.
4) as an amorphous structure on an I-type semiconductor.
They were laminated to a thickness of 0.00 mm to form an NIN bond.
かくしてN型半導体、I型半導体をそれぞれ独立の反応
室にて形成することにより、接合界面でおたがいの不純
物および半導体の混合を十分に排除することができた。By forming the N-type semiconductor and the I-type semiconductor in separate reaction chambers, it was possible to sufficiently eliminate impurities and the semiconductors from mixing with each other at the bonding interface.
この上面に、第1図(A)に示される如り、CTFとし
てのSnO□またはITOを500〜1500人の厚さ
に、さらにリードおよび電極となるクロムまたはアルミ
ニューム(500〜1500人)を電子ビーム蒸着法ま
たはスパンタ法により積層した。さらに、第2の電極(
22) 、複合ダイオード(2)として設ける領域を除
き、曲部を第2のフォトマスク■を用いてフォトエ/チ
ング法により除去して第2の電極を構成した。As shown in Fig. 1 (A), on this upper surface, SnO□ or ITO as CTF is coated to a thickness of 500 to 1500 mm, and chromium or aluminum (500 to 1500 mm thick) is further coated as leads and electrodes. Lamination was performed by electron beam evaporation method or spunter method. Furthermore, a second electrode (
22) Except for the region to be provided as the composite diode (2), the curved portion was removed by photoetching using a second photomask (2) to form a second electrode.
即ち第1図(八)において、ガラス基Fi(20)上の
透光性導電膜(17) 、 クロム電極(11)よりな
る第1の電極(21)、 N(12)I(13)N(1
4)半導体積層体よりなる旧N接合型複合ダイオード(
2) 、 CTF (15) 、クロムまたはアルミニ
ューム(16)よりなる第2の電極(22)よりなって
いる。このNIN構造の記号が第2図(B)に記されて
いる。That is, in FIG. 1 (8), a transparent conductive film (17) on a glass base Fi (20), a first electrode (21) consisting of a chromium electrode (11), N(12)I(13)N (1
4) Old N-junction type composite diode (
2) A second electrode (22) made of CTF (15), chromium or aluminum (16). The symbol of this NIN structure is shown in FIG. 2(B).
第3図(A)〜(D)に従来より公知のNIN接合型の
非線型素子の動作原理の概要を示す。FIGS. 3(A) to 3(D) outline the operating principle of a conventionally known NIN junction type nonlinear element.
第3図(八)はN(12)、I(13)、N(14)構
造を有する半導体(2)である。この場合はIll、I
、Nのすべての半導体は水素を含む珪素の非単結晶半導
体である。FIG. 3(8) shows a semiconductor (2) having an N(12), I(13), and N(14) structure. In this case, Ill, I
, N are all non-single crystal semiconductors of silicon containing hydrogen.
その厚さはN(12)700人、 I (13) 40
00人、N(14)700人である。電圧が端子(21
) 、 (22)間に印加されていない場合のエネルギ
バンド図を第3図(B)に示す。これに対して、もし基
板側端子(21)に比べて(22)に正の電圧(Va)
がかかると、第3図(C)のエネルギハンド構造となる
。すると電子(43)は障壁(41)が(41°)にそ
の高さを低くするに準じて順方向の電流として流れる。Its thickness is N (12) 700 people, I (13) 40
00 people, N(14) 700 people. The voltage is at the terminal (21
) and (22) are shown in FIG. 3(B). On the other hand, if there is a positive voltage (Va) at (22) compared to the board side terminal (21),
When , the energy hand structure shown in FIG. 3(C) is obtained. Then, the electrons (43) flow as a forward current as the barrier (41) lowers its height to (41°).
加えてNl界面(31)はN型半界体層(21)を構成
する不純物のリンの一部がI型半導体(23)内にプラ
ズマCvDでの被膜形成の際混入してしまうため、界面
近傍の1層がN−頭註に変成してしまう。このためNl
界面の+Vaの印加によるバリアの障壁が十分低くなり
、結果として第5図(51)の如く1〜2■の低いしき
い値電圧しか得られない電流特性が得られた。In addition, at the Nl interface (31), some of the impurity phosphorus constituting the N-type semi-field layer (21) is mixed into the I-type semiconductor (23) during film formation by plasma CvD. One layer in the vicinity is metamorphosed into an N-head note. For this reason, Nl
The barrier caused by the application of +Va at the interface became sufficiently low, and as a result, current characteristics were obtained in which only a low threshold voltage of 1 to 2 cm was obtained as shown in FIG. 5 (51).
この時、他の障壁(42) 、 (32) (第2図(
B))は障壁を構成せず、電流の流れに対しバリアを構
成しない。At this time, other barriers (42), (32) (Fig. 2 (
B)) does not constitute a barrier and does not constitute a barrier to the flow of current.
また、逆に端子(22)に負の電圧(−Va)が加わる
と(第3図(C))障壁(42)は(42’)となり、
そのN型半導体層(14)の電子(43”)が(42°
)より(13)へと流れる。かかる従来例の水素が添加
された珪素のみでのプラズマCVD法により形成する場
合は、1層(13)の珪素がN層(14)に混入し、こ
のN層(14)の界面近傍をN−化する傾向にするため
、中間領域(32)は巾広くなり、かつ−Vaが変わっ
てもバリアの高さく42’)は十分低くなり得ない。結
果として第5図(51′)のダイオードの逆流特性の如
きV−I特性となる。Conversely, when a negative voltage (-Va) is applied to the terminal (22) (Fig. 3 (C)), the barrier (42) becomes (42'),
The electrons (43”) of the N-type semiconductor layer (14) are (42°
) flows to (13). When forming the conventional plasma CVD method using only silicon to which hydrogen is added, one layer (13) of silicon is mixed into the N layer (14), and the vicinity of the interface of this N layer (14) is In order to tend to -, the intermediate region (32) becomes wide, and even if -Va changes, the barrier height 42') cannot be made sufficiently low. As a result, a VI characteristic like the reverse current characteristic of the diode shown in FIG. 5 (51') is obtained.
結果として第5図曲線(51) 、 (51°)に示す
如き、NIN構造を形成させたPIN接合のダイオード
の如き非対称の特性を得ることになりがちである。As a result, asymmetrical characteristics, such as those of a PIN junction diode formed with an NIN structure, as shown by curves (51) and (51°) in FIG. 5, tend to be obtained.
かくの如き非対称のダイオード特性を排除し、原点に対
し対称性を与えることが本発明の目的である。加えて1
層内に炭素を加えることにより、しきい値の大小の制御
を行うことが他の目的である。It is an object of the present invention to eliminate such asymmetric diode characteristics and provide symmetry with respect to the origin. In addition 1
Another purpose is to control the threshold value by adding carbon into the layer.
第4図(A)〜(D)に本発明の動作原理の概要を示す
。FIGS. 4(A) to 4(D) outline the operating principle of the present invention.
第4図(A)は水素が添加された非晶質珪素よりなるN
型半導体(厚さ500Å以下好ましくは100〜200
人)の第1の半導体N(12)、水素が添加された5i
xC+−x(0<X〈1)で示される真性または実質的
に真性の非晶質半導体よりなる第2の半導体I(13)
。Figure 4 (A) shows N made of amorphous silicon to which hydrogen is added.
type semiconductor (thickness 500 Å or less, preferably 100-200 Å
first semiconductor N(12), hydrogen-doped 5i
A second semiconductor I (13) made of an intrinsic or substantially intrinsic amorphous semiconductor represented by xC+−x (0<X<1)
.
第1の半導体と同一特性を有する第3の半導体N(14
)構造を有する半導体(2)である。その厚さはN(1
2) は100〜200 人、 I (13)は20
00〜4000人、N(14)は100〜200人であ
る。この場合の電圧が基板側端子(21)を基準として
(22)に印加されていない場合におけるエネルギバン
ド図を、第4図(8)に示す。この図面において、Nl
界面(31)、IN界面近傍のエネルギバンドにおける
伝導率は概略同一曲線性(31) 、 (32)を有し
ている。A third semiconductor N (14
) structure. Its thickness is N(1
2) is 100-200 people, I (13) is 20
00-4000 people, N(14) is 100-200 people. An energy band diagram in this case when the voltage is not applied to (22) with respect to the substrate side terminal (21) is shown in FIG. 4 (8). In this drawing, Nl
The conductivities in the energy bands near the interface (31) and the IN interface have approximately the same curvilinearity (31) and (32).
この場合の1層内へのDMS (ジメチルシラン)の添
加は1層内で一定とした。即ち第1図(C)に示す如(
1層形成の際、DMS/5i)I4= 1150とした
。In this case, the addition of DMS (dimethylsilane) to one layer was constant within one layer. That is, as shown in Figure 1 (C) (
When forming one layer, DMS/5i)I4 was set to 1150.
第4図(C)において、基板(21)に比べて軸2)に
正の電圧(+Va)を印加すると、第4図(C)のエネ
ルギハンド構造となる。すると電子(43)は、障壁(
41)が(41’ )にその高さを低くするに準じて順
方向の電流として流れる。そして第5図曲線(52)を
得る。In FIG. 4(C), when a positive voltage (+Va) is applied to the axis 2) compared to the substrate (21), the energy hand structure of FIG. 4(C) is obtained. Then, the electron (43) passes through the barrier (
41) flows as a forward current as the height is lowered to (41'). Then, a curve (52) in FIG. 5 is obtained.
また、逆に、端子(22)に負の電圧(−Va)が加わ
ると、第1図(D)に示されるごとく、障壁(42)が
(42’ ) と低くなり、そのN型半導体層(14
)の電子(43’)が(14)より(13)へと流れ、
第5図曲線(52’ )を得る。Conversely, when a negative voltage (-Va) is applied to the terminal (22), the barrier (42) becomes as low as (42'), as shown in FIG. 1(D), and the N-type semiconductor layer (14
) electron (43') flows from (14) to (13),
A curve (52') in FIG. 5 is obtained.
結果として、第5図に示す如き非線型特性(52)。As a result, a nonlinear characteristic (52) as shown in FIG. 5 is obtained.
(52’)を第4図(C) 、 (D)に対応して有せ
しめろことができる。(52') can be provided corresponding to FIGS. 4(C) and (D).
また、1層に炭素を添加したため、+Vaにおいては、
しきい値を1〜2vよりより高く、液晶ディスプレー等
に対し有効な例えば10以上にし得る。Also, since carbon was added to one layer, at +Va,
The threshold value can be higher than 1-2V, for example 10 or more, which is effective for liquid crystal displays and the like.
加えてこの1層中の炭素が5ixC+−Xと珪素と十分
結合するため、IN界面(32)における珪素のN層へ
の混合を防ぎ、逆方向側(−Va側)も(51’)より
(52’) としきい値を低く、かつ(52)と原点に
対し対称性を有せしめ得る。In addition, since carbon in this one layer sufficiently bonds with 5ixC+-X and silicon, it prevents silicon from mixing into the N layer at the IN interface (32), and the opposite side (-Va side) also (52') allows the threshold to be low and (52) to have symmetry with respect to the origin.
即ち、このNIN接合にあっては、立ち上がり電圧(し
きい値電圧) (100) 、 (100’ )はこの
第4図における障壁の高さく41) 、 (42)およ
び巾(31) 、 (32)により決められる。That is, in this NIN junction, the rise voltage (threshold voltage) (100), (100') is the barrier height 41), (42) and the width (31), (32) in FIG. ) is determined by
実施例2
本発明においては、実施例1における1層側のNl界面
、IN界面をより急峻とするため、第1図CD)に示す
ごとくに炭素の添加量を界面近傍に増加させた。即ち、
第2の半導体を形成する初期工程において、メチルシラ
ン/シランの比を多(して、プラズマ気相法で5〜30
人のきわめて薄い厚さにバリア(34)を形成させた。Example 2 In the present invention, in order to make the Nl interface and IN interface on the first layer side in Example 1 more steep, the amount of carbon added was increased near the interface as shown in FIG. 1 CD). That is,
In the initial step of forming the second semiconductor, the ratio of methylsilane/silane is increased (5 to 30% by plasma vapor phase method).
A barrier (34) was formed in the extremely thin thickness of a person.
すると、このしきい値(too) 、 (100°)が
さらに急峻となり、第5図の曲線(53) 、 (53
’)を得ることができた。Then, this threshold value (too), (100°) becomes even steeper, and the curves (53), (53
') was able to be obtained.
加えて、このNl界面、IN界面の双方に対して障壁を
作り、第2図(E)の構成とすると、V−1特性と第5
図曲線(54) 、 (54°)を得ることができた。In addition, if barriers are created for both the Nl interface and the IN interface, and the configuration shown in Figure 2 (E) is created, the V-1 characteristic and the 5th
Figure curves (54) and (54°) could be obtained.
この第5図のV−[特性を縦軸に対しログスケールとし
て第6図に対応して示す。すると、第2図(D) 、
(E)に示す如き界面に炭素を高濃度とし、不純物、構
成物のそれぞれの層での混合を防止するバリアを構成さ
せると、しきい値が+Vaと−Vaにおいて対称特性を
より有するに加えて、第6図での低電流領域である発生
領域(61) 、 (61°)は、より平坦になり、大
電流領域である(62) 、 (62’ )の拡散電流
領域はより急峻に立ち上がるため、rONJ。The V-[characteristics in FIG. 5 are shown on a log scale with respect to the vertical axis, corresponding to FIG. 6. Then, Figure 2 (D),
If carbon is concentrated at a high concentration at the interface as shown in (E) and a barrier is formed to prevent mixing of impurities and constituents in each layer, the threshold value will have more symmetrical characteristics at +Va and -Va. Therefore, the generation regions (61) and (61°), which are low current regions, in Fig. 6 become flatter, and the diffusion current regions (62) and (62'), which are high current regions, become more steep. To stand up, rONJ.
rOFF jの境界を示すしきい値(100) 、 (
100°)をより明確にすることができ得る。Threshold value (100) indicating the boundary of rOFF j, (
100°) may be made clearer.
「効果」
本発明は以上に示す如く、対称型のV−I特性を有する
複合ダイオードを構成せしめるため、1層とN層との界
面またはその近傍に炭素を添加したものである。さらに
この非線型素子はその応用である表示素子に用いる液晶
およびS/N比に適したしきい値を、1層への炭素の添
加量および1層の厚さの制御を行うことにより成就でき
た。さらに加えて、NI、IN接合界面に炭素を内部に
比べ多量に添加することにより、しきい値以下の電圧で
の電流を平坦にし、このしきい値以上の電圧での電流を
急峻にせしめる特性用のプロセス制御を行うことができ
る。"Effects" As described above, in the present invention, carbon is added at or near the interface between the first layer and the N layer in order to construct a composite diode having symmetrical VI characteristics. Furthermore, this nonlinear element can achieve a threshold value suitable for the liquid crystal and S/N ratio used in display elements, which is its application, by controlling the amount of carbon added to one layer and the thickness of one layer. Ta. In addition, by adding a larger amount of carbon to the NI/IN junction interface than inside, it has the property of flattening the current at voltages below a threshold value and making the current steeper at voltages above this threshold value. process control.
本発明において、1層内に炭素を添加した。しかし炭素
ではなく、酸素または窒素としてもよい。In the present invention, carbon was added within one layer. However, instead of carbon, oxygen or nitrogen may be used.
しかしこれらは絶縁物化しやすいため、その添加量の制
御がより微妙であり、製造のしやすさではメチルシラン
を用いる炭素に比べて困難さを有している。However, since these materials are easily converted into insulators, the amount of addition thereof must be controlled more delicately, and it is more difficult to manufacture them than carbon using methylsilane.
本発明の実施例ではプラズマ気相反応を示した。In the examples of the present invention, a plasma gas phase reaction was shown.
しかしメチルシランとジシラン(SizH+、) との
反応を用いることにより光気相反応をさせることが可能
である。However, by using the reaction between methylsilane and disilane (SizH+), it is possible to carry out a photogas phase reaction.
かかる場合は、基板を250〜300 ”Cに加熱し、
254nmまたは184nmの波長の光を照射すること
によりN型半導体または5ixC+−x(0<X<1)
で示される真性または実質的に真性の半導体を形成し得
る。In such a case, heat the substrate to 250-300"C,
N-type semiconductor or 5ixC+-x (0<X<1) by irradiating light with a wavelength of 254 nm or 184 nm
An intrinsic or substantially intrinsic semiconductor may be formed.
この場合も量産性を考慮すると、第2図に示す独立反応
炉方式が有効である。In this case as well, considering mass productivity, the independent reactor system shown in FIG. 2 is effective.
第1図は、本発明の複合ダイオードの縦断面図(A)
、 (B)および1層への炭素添加の濃度分布(C)。
(D) 、 (E)を示す。
第2図は本発明を用いたプラズマ気相反応装置の概要を
示す。
第3図は従来より公知のアモルスアスシリコンのみを用
いたNIN接合の動作特性を示す。
第4図は本発明の1層内に炭素を添加した[N接合型複
合ダイオードの非線形素子の動作原理を示す。
第5図1.第6図は従来の特性(51) 、 (51′
)および本発明の特性(52) 、 (52°)、 (
53) 、 (53°) 、 (54) 、 (54°
)を示す。FIG. 1 is a vertical cross-sectional view (A) of the composite diode of the present invention.
, (B) and concentration distribution of carbon addition to one layer (C). (D) and (E) are shown. FIG. 2 shows an outline of a plasma gas phase reactor using the present invention. FIG. 3 shows the operating characteristics of a conventionally known NIN junction using only amorphous silicon. FIG. 4 shows the operating principle of the nonlinear element of the present invention, which is an N-junction composite diode in which carbon is added in one layer. Figure 5 1. Figure 6 shows the conventional characteristics (51) and (51'
) and the characteristics of the present invention (52), (52°), (
53) , (53°) , (54) , (54°
) is shown.
Claims (1)
一対の逆向整流特性を有する半導体よりなる非線型素子
であって、前記半導体は一導電型を有する第1の非単結
晶半導体と、該半導体上の真性または実質的に真性の珪
素を主成分とする第2の非単結晶半導体と、該半導体上
の前記第1の非単結晶半導体と同一導電型を有する第3
の半導体とを積層して設ける半導体装置作製方法におい
て、第2の半導体はプラズマ気相反応、光気相反応また
は光プラズマ気相反応により、珪化物気体と、該気体に
メチルシランを添加することにより炭素が添加された珪
素を主成分とする第2の非単結晶半導体を形成すること
を特徴とする半導体装置作製方法。 2、特許請求の範囲第1項において、メチルシラン/シ
ラン≒1/200〜1/5の範囲で添加して設けたこと
を特徴とする半導体装置作製方法。 3、特許請求の範囲第1項において、第2の非単結晶半
導体を形成する初期工程または末期工程において、メチ
ルシランのみまたはメチルシラン/シラン>1として形
成することを特徴とする半導体装置作製方法。[Scope of Claims] 1. A nonlinear element comprising a pair of semiconductors having reverse rectification characteristics and exhibiting ohmic contact with a first electrode and a second electrode, wherein the semiconductor has a first conductivity type. a non-single-crystalline semiconductor on the semiconductor, a second non-single-crystalline semiconductor mainly composed of intrinsic or substantially intrinsic silicon, and a second non-single-crystalline semiconductor on the semiconductor having the same conductivity type as the first non-single-crystalline semiconductor on the semiconductor; 3rd having
In a method for manufacturing a semiconductor device in which a second semiconductor is formed by stacking a second semiconductor, a second semiconductor is formed by adding a silicide gas and methylsilane to the gas by a plasma gas phase reaction, a photovapor phase reaction, or a photoplasma gas phase reaction. A method for manufacturing a semiconductor device, comprising forming a second non-single crystal semiconductor whose main component is silicon to which carbon is added. 2. A method for manufacturing a semiconductor device according to claim 1, characterized in that methylsilane/silane is added in a range of approximately 1/200 to 1/5. 3. A method for manufacturing a semiconductor device according to claim 1, characterized in that in the initial step or final step of forming the second non-single crystal semiconductor, only methylsilane or methylsilane/silane>1 is formed.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59206081A JPS6184070A (en) | 1984-10-01 | 1984-10-01 | Manufacture of semiconductor device |
US07/000,155 US4744862A (en) | 1984-10-01 | 1987-01-02 | Manufacturing methods for nonlinear semiconductor element and liquid crystal display panel using the same |
US07/203,641 US4855805A (en) | 1984-10-01 | 1988-06-03 | Nonlinear semiconductor element, liquid crystal display panel using the same and their manufacturing methods |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59206081A JPS6184070A (en) | 1984-10-01 | 1984-10-01 | Manufacture of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6184070A true JPS6184070A (en) | 1986-04-28 |
JPH0516671B2 JPH0516671B2 (en) | 1993-03-05 |
Family
ID=16517506
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59206081A Granted JPS6184070A (en) | 1984-10-01 | 1984-10-01 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6184070A (en) |
-
1984
- 1984-10-01 JP JP59206081A patent/JPS6184070A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPH0516671B2 (en) | 1993-03-05 |
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